KR0158656B1 - Wet etching method for fabrication of semiconductor device - Google Patents
Wet etching method for fabrication of semiconductor device Download PDFInfo
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- KR0158656B1 KR0158656B1 KR1019950036007A KR19950036007A KR0158656B1 KR 0158656 B1 KR0158656 B1 KR 0158656B1 KR 1019950036007 A KR1019950036007 A KR 1019950036007A KR 19950036007 A KR19950036007 A KR 19950036007A KR 0158656 B1 KR0158656 B1 KR 0158656B1
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- sacrificial oxide
- metal wiring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
반도체 기판위에 절연막과 금속 배선을 차례로 형성한 후, 이 금속 배선을 식각하고, 이 금속 배선과 상기 절연막위에 희생 산화막을 증착한 후 이 희생 산화막을 식각하여 스페이서를 형성한 뒤, 패드 식각제로 상기 절연막과 스페이서를 식각하여 습식식각하는 방법은 초산, 불화암모늄, 순수 용액을 이용하여 알루미늄 합금의 플라즈마 식각시 발생되는 실리콘, 구리 불순물과 염소 가스와의 반응성 화합물이나, 혹은 실리콘, 구리 찌꺼기를 효과적으로 제거하고, 습식 식각시 발생되는 배선 측벽의 공격을 방지하기 위해 배선 식각 후 알루미늄 자연 산화막이 형성되지 않은 측벽부에 희생 산화막을 형성시켜, 습식식각 용액에서 잔류 물질 제거시 발생되는 배선 측벽의 공격을 효과적으로 방지할 수 있다.After forming an insulating film and a metal wiring on the semiconductor substrate in turn, the metal wiring is etched, a sacrificial oxide film is deposited on the metal wiring and the insulating film, and the sacrificial oxide film is etched to form a spacer, and then the insulating film is formed using a pad etchant. The wet etching method of etching spacer and spacer effectively removes reactive compounds of silicon, copper impurities and chlorine gas, or silicon and copper residues generated during plasma etching of aluminum alloy using acetic acid, ammonium fluoride and pure solution. In order to prevent attack of the wiring sidewalls generated during wet etching, a sacrificial oxide film is formed on the sidewalls where the aluminum natural oxide film is not formed after the wiring etching, thereby effectively preventing the attack of the wiring sidewalls generated when the residual material is removed from the wet etching solution. can do.
Description
제1도의 (a)∼(b)는본 발명에 따른 반도체 제조에 이용되는 습식 식각방법을 개략적으로 나타낸 단면도이다.1A to 1B are cross-sectional views schematically illustrating a wet etching method used for manufacturing a semiconductor according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기관 2 : 절연막1 semiconductor organ 2 insulating film
3 : 금속 배선 4 : 찌꺼기3: metal wiring 4: dregs
5 : 희생 산화막 6 : 패드 식각제5: sacrificial oxide film 6: pad etchant
[산업상 이용분야][Industrial use]
본 발명은 반도체 제조에 이용되는 습식 식각방법에 관한 것으로 더욱 상세하게는 예를 들어, 알루미늄 합금으로 구성된 금속배선을 잔류 물질없이 식각할 수 있으며, 반도체 제조에 이용되는 습식 식각방법에 관한 것이다.The present invention relates to a wet etching method used in semiconductor manufacturing, and more particularly, to a wet etching method used in semiconductor manufacturing, for example, a metal wiring composed of an aluminum alloy can be etched without residual materials.
[종래기술][Private Technology]
반도체 소자의 배선재료로 주로 이용되는 알루미늄-구리-실리콘, 알루미늄-실리콘 합금은 배선의 형성을 위하여 이용되는 염소 가스를 근원으로 하는 플라즈마 식각시, 반응성 물질의 서로 다른 증기압으로 인하여 배선이 식각된 절연층위에 실리콘, 구리 잔사가 존재한다. 이와같이 발생되는 찌꺼기는 후속 공정인 절연막 증착시 스탭 커버리지 불량이나 외관검사 불량을 야기시켜 수율을 감소시키는 원인이 된다. 따라서, 알루미늄 합금의 플라즈마 식각후 상기와 같은 형태의 찌꺼기가 남지 않는 후처리 방법이 요구된다. 알루미늄 합금 배선 식각후 발생되는 찌꺼기를 처리하는 종래의 기술에는 SF6가스나 CF4O2플라즈마로 처리하는 방법이 사용되고 있다.Aluminum-copper-silicon and aluminum-silicon alloys, which are mainly used as wiring materials for semiconductor devices, are insulated from wiring due to different vapor pressures of reactive materials during plasma etching based on chlorine gas used for wiring formation. Silicon, copper residues are present on the layer. The debris generated as described above causes a step coverage defect or a visual inspection defect during the deposition of the insulating film, which is a subsequent process, to reduce the yield. Therefore, there is a need for a post-treatment method in which no residue of the above form remains after plasma etching of an aluminum alloy. In the conventional technique for treating residue generated after etching aluminum alloy wiring, a method of treating with SF 6 gas or CF 4 O 2 plasma is used.
그러나 상기한 방법들은, 플라즈마로 인해 금속 배선이 손상되거나 알루미늄과 프레온 가스의 반응 화합물인 Al-F 폴리머가 배선측벽부에 과다하게 형성되어 상부 절연막의 스탭 커버리지가 불량하게 되므로서, 후속 배선의 단선을 유발시키는 문제점이 있다.However, in the above methods, the metal wiring is damaged due to the plasma or the Al-F polymer, which is a reaction compound of aluminum and freon gas, is excessively formed in the wiring side wall portion, resulting in poor staff coverage of the upper insulating film, thereby causing disconnection of subsequent wiring. There is a problem that causes.
[발명이 해결하려고 하는 과제][Problems that the invention tries to solve]
본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 금속배선을 식각하는 방법에 있어서, 알루미늄 합금을 플라즈마 식각할 때 플라즈마로 인해 금속 배선이 손상되거나 알루미늄과 프레온 가스의 반응 화합물인 Al-F 폴리머가 형성되지 않으며, 반도체 제조에 이용되는 습식 식각방법을 제공하는 것이다.The present invention is to solve the problems of the prior art as described above, an object of the present invention in the method of etching the metal wiring, when the plasma etching the aluminum alloy, the metal wiring is damaged due to the plasma or aluminum and freon gas The Al-F polymer is not formed as a reaction compound, and a wet etching method used for manufacturing a semiconductor is provided.
[과제를 해결하기 위한 수단][Means for solving the problem]
상기와 같은 본 발명의 목적을 달성하기 위하여, 본 발명은 반도체 기판위에 절연막과 금속 배선을 차례로 형성하고, 금속 배선을 플라즈마 식각하는 공정, 상기 금속 배선과 상기 절연막위에 희생 산화막을 증착하는 공정, 상기 희생 산화막을 식각하여 스페이서를 형성하는 공정, 패드 식각제로 상기 절연막과 스페이서를 식각하는 공정을 포함하는 반도체 제조에 이용되는 습식 식각방법을 제공한다.In order to achieve the object of the present invention as described above, the present invention is a step of sequentially forming an insulating film and a metal wiring on a semiconductor substrate, plasma etching the metal wiring, the step of depositing a sacrificial oxide film on the metal wiring and the insulating film, the Provided is a wet etching method for manufacturing a semiconductor, the method including etching a sacrificial oxide film to form a spacer, and etching the insulating film and the spacer with a pad etchant.
[실시예]EXAMPLE
반도체 기판위에 절연막과 금속 배선을 차례로 형성하고, 금속 배선을 플라즈마 식각한 후, 상기 금속 배선과 상기 절연막위에 희생 산화막을 증착한다. 이어서, 상기 희생 산화막을 식각하여 스페이서를 형성하고, 패드 식각제로 상기 절연막과 스페이서를 식각하는 반도체 제조에 이용되는 습식 식각방법을 제공한다.The insulating film and the metal wiring are sequentially formed on the semiconductor substrate, the metal wiring is plasma-etched, and then a sacrificial oxide film is deposited on the metal wiring and the insulating film. Next, a wet etching method is used to form a spacer by etching the sacrificial oxide layer, and to fabricate a semiconductor using the pad etchant to etch the insulating layer and the spacer.
본 발명에 있어서, 상기 패드 식각제는 인산, 질산, 초산의 비율이 인산 1∼2 중량부 : 질산 1∼2 중량부 : 초산 1∼2 중량부인 패드 식각제를 사용한다. 상기한 패드 식각제는 일반 산화막 식각제(B.O.E:buffered oxide etchant)보다 식각율이 낮아 산화막 식각율의 조정이 용이하여 바람직하다.In the present invention, the pad etchant uses a pad etchant wherein the ratio of phosphoric acid, nitric acid, acetic acid is 1 to 2 parts by weight of phosphoric acid: 1 to 2 parts by weight of nitric acid: 1 to 2 parts by weight of acetic acid. The pad etchant is preferable because the etching rate is lower than that of the general oxide etchant (B.O.E: buffered oxide etchant).
본 발명에 있어서, 상기 패드 식각제의 온도는 22℃∼80℃인 혼합용액을 사용한다. 상기한 온도 범위보다 높을 경우 식각율이 증가하고, 이 온도 범위보다 낮을 경우 식각율이 감소하는 문제가 있어 잔류 산화막을 제어하는 것이 용이하지 못하여 바람직하지 못하다.In the present invention, the temperature of the pad etchant is used a mixed solution of 22 ℃ to 80 ℃. If the temperature is higher than the above temperature range, the etching rate is increased, and if the temperature is higher than the temperature range, the etching rate is decreased. Therefore, it is not preferable to control the residual oxide film.
본 발명에 있어서, 상기 절연막이 1000Å 이하의 두께만큼 식각되도록 식각을 실시하는 것이 바람직하다. 상기 절연막이 1000Å 이상의 두께로 식각되면 금속 배선의 측벽에 영향을 줄 수 있어서 바람직하지 못하고, 500Å 이하의 두께로 식각되면 잔류물질제거능력이 저하되어 바람직하지 못하다.In the present invention, it is preferable to perform etching so that the insulating film is etched by a thickness of 1000 Å or less. If the insulating film is etched to a thickness of 1000 Å or more, it may not be preferable because it may affect the sidewall of the metal wiring, and if the etched to a thickness of 500 Å or less, the residual material removal ability may be deteriorated.
본 발명에 있어서, 상기 희생 산화막은 SiH4, PH3, B2H6, O2을 1:3:10:91의 비율로 구성한 가스분위기에서 화학적 기상 성장법으로 형성시킨다.In the present invention, the sacrificial oxide film is formed by chemical vapor deposition in a gas atmosphere composed of SiH 4 , PH 3 , B 2 H 6 , and O 2 in a ratio of 1: 3: 10: 91.
본 발명에 있어서, 상기 희생 산화막의 두께는 배선 두께의 60%이상으로 하는 것이 요구되는 스페이서 형성이 용이하여 바람직하다.In the present invention, the thickness of the sacrificial oxide film is preferred because it is easy to form a spacer required to be 60% or more of the wiring thickness.
본 발명에 있어서, 상기 희생 산화막을 식각하는 방법은 RIE플라즈마 식각법을 이용하는 것이 언더에치가 줄어들고 원하는 모양대로 식각할 수 있어서 바람직하다.In the present invention, the method of etching the sacrificial oxide film is preferable to use the RIE plasma etching method because the underetch is reduced and can be etched to the desired shape.
본 발명에 있어서, 상기 RIE 플라즈마 식각은 CHF3, CF4, Ar, O2의 가스를 이용하여 실시하는 것이 바람직하다.In the present invention, the RIE plasma etching is preferably performed using a gas of CHF 3 , CF 4 , Ar, O 2 .
이하 본 발명의 바람직한 실시예 및 비교예를 기재한다. 그러나 하기한 실시예 및 비교예는 본 발명의 이해를 돕기 위한 본 발명의 바람직한 일실시예일뿐 본 발명이 하기한 실시예에 한정되는 것은 아니다.Hereinafter, preferred examples and comparative examples of the present invention are described. However, the following examples and comparative examples are only preferred embodiments of the present invention to aid in understanding the present invention, and the present invention is not limited to the following examples.
[실시예 1]Example 1
제1도는 본 발명에 따른 습식 식각 방법을 공정 순서에 따라 나타낸 것이다.Figure 1 shows the wet etching method according to the invention in the order of the process.
공정 순서에 따라 우선 반도체 기판(1)의 일면에 절연막 형성 물질을 3000∼7000Å 두께로 증착하여 절연막(2)을 형성하고, 이 절연막(2)의 일면에는 알루미늄 배선을 형성하기 위한 물질을 소정의 두께로 증착하여 알루미늄 배선 형성층(3')을 형성한다. (제1도 (a)a).According to the process sequence, an insulating film forming material is first deposited on one surface of the semiconductor substrate 1 to a thickness of 3000 to 7000 Å to form an insulating film 2, and one surface of the insulating film 2 is provided with a material for forming an aluminum wiring. The thickness is deposited to form an aluminum wiring forming layer 3 '. (Figure 1 (a) a).
이러한 상태에서 상기 알루미늄 배선 형성층(3')을 AME8330A, Cl2, BCl3, CHF3를 1:4:0.5의 비율로 구성한 가스 분위기에서 Cl2플라즈마 식각하여 소정의 패턴을 갖는 알루미늄 배선(3)으로 형성한다.(제1도 (a)).In this state, the aluminum wiring forming layer 3 ′ is etched with Cl 2 plasma in a gas atmosphere having AME8330A, Cl 2 , BCl 3 , and CHF 3 in a ratio of 1: 4: 0.5, and has a predetermined pattern. (FIG. 1 (a)).
이 공정 단계에서 상기 절연막(2)의 노출 부위에는, 실리콘, 구리 불순물과 염소 가스와의 반응성 혼합물의 잔류물(4)이 잔존하게 된다.In this process step, residue 4 of the reactive mixture of silicon, copper impurities and chlorine gas remains in the exposed portion of the insulating film 2.
상기 알루미늄 배선(3)의 형성 단계에 이어 다음 단계로는, 상기 절연막(2)의 노출 부위 및 상기 알루미늄 배선(3)의 위로 희생 산화막 형성물질을 증착하여 희생 산화막(5)을 형성한다(제1도(b)).Subsequent to the forming of the aluminum wiring 3, the next step is to form a sacrificial oxide film 5 by depositing a sacrificial oxide film-forming material on the exposed portion of the insulating film 2 and the aluminum wiring 3. 1 degree (b)).
여기서 이 희생 산화막(5)을 형성하는 구체적인 방법은 SiH4, PH3, B2H6, O2를 1:3:10:91의 비율로 구성한 가스 분위기에서 화학적 기상 증착법으로 희생 산화막 형성물질을 상기 알루미늄 배선(3) 두께의 60% 이상되게 증착하여 형성하는 것이 바람직하다.Here, the specific method of forming the sacrificial oxide film 5 may be performed by chemical vapor deposition in a gas atmosphere including SiH 4 , PH 3 , B 2 H 6 , and O 2 in a ratio of 1: 3: 10: 91. It is preferable to form by depositing 60% or more of the thickness of the aluminum wiring (3).
이와 같이 하여 상기 희생 산화막(5)이 형성되면, 그 다음으로는 이 희생 산화막(5)을 식각하여 상기 알루미늄 배선(3)의 측벽부에 이 알루미늄 배선(3)을 보호하기 위한 스페이서(5')을 형성하게 되는데, 여기서 상기한 식각 방법으로는 RIE(Reactive Ion Etching) 플라즈마 식각 방법이 바람직하다(제1도 (c)a).When the sacrificial oxide film 5 is formed in this manner, the sacrificial oxide film 5 is then etched to protect the aluminum interconnect 3 by the sidewall portion of the aluminum interconnect 3. In this case, as the etching method, a reactive ion etching (RIE) plasma etching method is preferable (FIG. 1 (c) a).
다음으로는, 인산 1 중량부 : 질산 1 중량부 : 초산 1 중량부의 비율로 혼합된 식각제(6)에 상기 반도체 기판(1)을 포함한 구성물들을 10초 정도로 담그어 습식 식각을 실시한다(제1도 (c)).Next, a wet etching is performed by dipping the components including the semiconductor substrate 1 in the mixed etchant 6 in a ratio of 1 part by weight of phosphoric acid: 1 part by weight of nitric acid: 1 part by weight of acetic acid for about 10 seconds. (C)).
이처럼 습식 식각 공정이 실시되면, 이 과정에서 상기한 잔류물(4) 및 상기 스페이서(5')가 제거되므로, 이에 상기 반도체 기판(1)에는 잔류물(4)이 없는 절연막(2)과, 측벽부에 손상이 없는 알루미늄 배선(3)이 형성된다(제1도 (d)).When the wet etching process is performed as described above, the residue 4 and the spacer 5 ′ are removed in this process, so that the semiconductor substrate 1 has an insulating film 2 having no residue 4, An aluminum wiring 3 without damage is formed in the side wall portion (FIG. 1 (d)).
[효과][effect]
상기한 바와 같이 본 발명은 초산, 인산 및 질산을 이용하여 알루미늄 합금의 플라즈마 식각시 발생되는 실리콘, 구리 불순물과 염소 가스와의 반응성 화합물이나, 혹은 실리콘, 구리 찌꺼기를 효과적으로 제거하고, 습식 식각시 발생되는 배선 측벽의 공격을 방지하기 위해 배선 식각 후 알루미늄 자연 산화막이 형성되지 않은 측벽부에 희생 산화막을 형성시켜, 습식식각 용액에서 잔류 물질 제거시 발생되는 배선 측벽의 공격을 효과적으로 방지할수 있다.As described above, the present invention effectively removes reactive compounds of silicon, copper impurities and chlorine gas, or silicon and copper residues generated during plasma etching of an aluminum alloy using acetic acid, phosphoric acid, and nitric acid, and occurs during wet etching. In order to prevent the attack of the wiring sidewalls to be formed, a sacrificial oxide layer may be formed on the sidewalls where the aluminum natural oxide layer is not formed after the wiring etching, thereby effectively preventing the attack of the wiring sidewalls generated when the residual material is removed from the wet etching solution.
Claims (8)
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| KR1019950036007A KR0158656B1 (en) | 1995-10-18 | 1995-10-18 | Wet etching method for fabrication of semiconductor device |
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