KR0157528B1 - Wide expression apparatus using digital sampling velocity transmittance - Google Patents

Abstract

[Technical field to which the invention described in the claims belong]

The present invention relates to a device for displaying 4: 3 signals on a 16: 9 wide screen, and more particularly to a display device for displaying in 16: 9 wide format using a digital sample rate converter (SRC) method. Will.

[Technical Challenges to Invent]

Provides a device that can convert 4: 3 screens to 16: 9 on wide TVs without losing left and right data, and allows users to convert all screens according to the conversion of settings.

[Summary of the solution of the invention]

A / D converter 303 for converting a 4: 3 television signal into a 16: 9 television signal and digitalizing the input data of the input terminal 301, and the digitalized signal of the A / D converter 303. An interpolation filter unit 307 to interpolate, a filter control unit 309 to control filtering of the interpolation filter unit 309, a filtering clock CLK1 of the interpolation filter unit 307, and the filter control unit 309. Generates a count value recorded by the clock generation circuit unit 313 providing a control clock of the controller, a set value calculator 311 providing a coefficient set value to the filter control unit 309, and an output of the filter control unit 309. Consisting of a coefficient memory section 305.

[Important Uses of the Invention]

A device that displays 4: 3 television signals on wide 16: 9 televisions.

Description

Wide 16: 9 Display of 4: 3 Television Signal Using Digital Sampling Rate Conversion

1 is a conventional 8-Top filter control circuit diagram.

2 is a conventional filter control circuit diagram.

3 is a block diagram according to the present invention.

4 is a comparative example of a 16: 9 screen of a 4: 3 circuit diagram.

5 is a specific circuit diagram of the filter control unit 309 of FIG.

6 is a detailed circuit diagram of the clock generation circuit section 313 of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for displaying 4: 3 signals on a 16: 9 wide screen in a television receiver, and in particular, digital displays using a digital sample rate converter (SRC) method in 16: 9 wide format. A wide 16: 9 display of a 4: 3 television signal using sampling rate conversion.

The structure of the conventional sampling rate converter SRC is a value eight-top interpolation filter composed of registers r1 to r8 and multipliers M1 to M8 as shown in FIG. 1, and a second for controlling the interpolation filter. It consists of a filter control circuit composed of the 8-bit adder 201 and the register 202 of FIG. In FIG. 1, an 8-Top interpolation filter includes eight registers r1 to r8, multipliers M1 to M8 for multiplying the coefficients of the contents of the registers r1 to r8, and respective result values. It consists of an adder A1 for addition. The control circuit of the filter of FIG. 2 comprises an 8-bit adder 201 and an 8-bit register 202 for storing the addition result. The 8-Top interpolation filter of FIG. Multiply by The selection of the filter coefficients C0-C7 is selected from the position value of the filter control circuit in FIG. 2, and the multiplied result value is added and output from the adder A1. The filter control circuit adds the set value for determining the number of pixels of the input data stage 203 and the contents of the register 202 in the 8-bit adder 201, and the resultant value is again set and the register 202. ) Is added to the 8-bit adder 201. The control signal of the 8-bit adder 201 becomes a load signal of new data of the data stage 101 of the interpolation filter of FIG. 1, and the new data is input to the interpolation filter. On the other hand, the upper 3 bits of the registers r1-r8 become position values for selecting coefficients, and are configured to input coefficients already calculated from the signal to the multiplier M-M8. As described above, the conventional technology is a device for converting a screen that is originally inputted into a large screen using an interpolation filter, and thus, only a part of the screen may be configured, and thus, all screens cannot be processed simultaneously.

Accordingly, an object of the present invention is to provide a device capable of converting a 4: 3 screen to 16: 9 of a wide TV without losing left and right data, and converting all screens according to a change of a user setting. .

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram according to the present invention,

An A / D converter 303 for digitalizing the input data of the input terminal 301, an interpolation filter unit 307 for interpolating the signal digitalized by the A / D converter 303, and the interpolation filter unit 307 A filter control unit 309 for filtering control according to the interpolation processing;

A clock generation circuit unit 313 providing a sampling clock CLK1 for A / D conversion of the A / D converter 303 and a clock CLK2 of the filter control unit 309;

A set value calculator (311) for providing a coefficient set value to the filter control unit (309);

And a coefficient memory unit 305 for generating coefficient values recorded by the output of the filter control unit 309.

4 is a comparative example of 4: 3 and 16: 9 in television screen size.

4A is an exemplary diagram of screen size 4: 3, and (4B) is an exemplary diagram of 16: 9.

5 is a detailed circuit diagram of the filter control unit 309 of FIG.

A counter 501 that counts 256,

A subtractor 504 for subtracting the output screen of the output terminal 503 and the input screen of the input terminal 502,

A multiplier 505 that multiplies the output of the counter 501 by the output of the subtractor 504,

An 8-bit adder 506 that adds the output of the multiplier 505 to a previous initial generated value,

It consists of a register 507 that stores the output of the 8-bit adder 506.

FIG. 6 is a detailed circuit diagram of the clock generation circuit unit 313 of FIG. 3, and includes a clock generator 601 for oscillating a predetermined clock and providing the clock to the filter controller 309, and an output and an aspect ratio of the clock generator 601. And a subtractor 602 which subtracts the input value of the input terminal 603 and provides the sampling clock of the A / D converter 303.

Therefore, a specific embodiment of the present invention will be described in detail with reference to FIGS. 3 to 6, wherein the input signal is the sampling clock of the A / D converter 303 by the clock CLK1 of the clock generation circuit unit 313. It is provided and digitalized into 8 bits. The input signal has a 4: 3 screen as shown in FIG. 4 (A4), and the screen to be output therefrom is a 16: 9 screen as shown in FIG. To this end, the sampling operation clock of the A / D converter 303 uses three quarters of the clock generated by the clock generator 601 of FIG. 6 as the output of the clock generation circuit unit 313. In this case, 720 horizontal samples are reduced to 544 samples. The output of the A / D converter 303 is input to the interpolation filter unit 307. The interpolation filter unit 307 receives the generated data and converts 544 samples into 720 horizontal samples. The interpolation filter unit 307 used here uses an existing 8-top interpolation filter, and the coefficient of the filter is realized by using a coefficient value output from a separate coefficient memory (ROM) unit 305. . The filter control unit 309 in FIG. 5 generates various signals for the interpolation filter unit 307. The constant in FIG. 5 256 represents the maximum value of the filter coefficient, and the value is the magnitude when the input screen is output. Multiplied by. The resultant value is an initial setting value for determining the filter coefficient. The output of the 8-bit adder 506 is stored in the register 507 and this value is again input to the 8-bit adder 506. When the 544 is 720, the initial set value is 192, and the coefficient selection signal and the new data are loaded from the value. 6 shows the clock generation circuit unit 313. In the case of the clock of the output clock stage CLK2, 13.5 MHz, which is a standard clock of CCIR601, is used. Since the ratio of the screen size is determined, the clock of the input clock stage CLK1 becomes 13.5MHz x 3/4 when the 4: 3 screen is converted to 16: 9. This is generated and provided from a separate clock generator 601. Since the operation of the entire circuit is made variable by the user setting of the circuit, the coefficient of the filter can be modified by changing the data of the coefficient memory section 305.

As described above, the present invention can be applied to a wide TV by converting a 4: 3 original screen to 16: 9 without losing left and right data, and having a simple structure, it is easy to implement and a cost reduction is also possible. There is an advantage that the setpoint conversion can be applied to the conversion of all screens.

Claims (3)

An A / D converter 303 for converting a 4: 3 television signal into a 16: 9 television signal and digitizing the input data of the input terminal 301 of the television in a circuit; and digitalizing the A / D converter 303 Generation circuit section 313 providing an interpolation filter section 307 for interpolating the signal, a clock CLK2 of the filter control section 309, and an A / D conversion sampling clock CLK1 of the A / D converter 303. ) And a filter control unit 309 for generating a control signal for interpolation filtering of the interpolation filter unit 307 by the generation clock CLK2 of the clock generation circuit unit 313 and the filter control unit 309. 4: using a digital sampling rate conversion, characterized in that it comprises a set value calculator (311) for providing a set value, and a coefficient memory (305) for generating a count value recorded by the output of the filter control section (309). Wide 16: 9 display with 3 television signals. The counter of claim 1, wherein the filter control unit 309 counts n, a subtractor 504 for subtracting an output screen and an input screen, an output of the counter 501, and a subtractor 504. A multiplier 505 multiplying the output of < RTI ID = 0.0 >, < / RTI > Wide 16: 9 display of 4: 3 television signal using digital sampling rate conversion, characterized in that the configuration. The clock generator 601 of claim 1, wherein the clock generator 313 oscillates a predetermined clock and provides the clock generator 601 to the clock CLK2 of the filter controller 309, and an output and an aspect ratio input terminal of the clock generator 601. A subtractor 602 configured to subtract the input value of 603 to provide the sampling clock CLK1 of the A / D converter 303 to widen the 4: 3 television signal using the digital sampling rate conversion. 16: 9 display.