KR0157346B1 - Program protecting method for nonvolatile semiconductor memory - Google Patents

Abstract

1. the technical field to which the invention described in the claims belongs;

A nonvolatile semiconductor memory.

2. The technical problem to be solved by the invention;

Provides a program protection method that can eliminate malfunctions when a program is prevented.

3. Summary of the Solution of the Invention;

Applying a program voltage to a selected word line to program a selected memory cell, applying a pass voltage for not programming a memory cell that should not be programmed to be connected to the selected word line, and before applying the pass voltage Applying a pre-charge voltage for precharging cells, applying ground power to bit lines of the selected memory cells, and applying power voltages to bit lines of the unselected memory cells. It is provided.

4. Significant use of the invention;

It is suitably used for nonvolatile semiconductor memory.

Description

Program Prevention Method of Nonvolatile Semiconductor Memory

1 is a schematic circuit diagram of a nonvolatile semiconductor memory.

2 is a cross-sectional view of a floating gate MOS transistor.

3 shows a comparison of a pass voltage application signal between a conventional nonvolatile semiconductor memory and a nonvolatile semiconductor memory according to the present invention.

FIG. 4 compares the channel potential of the conventional nonvolatile semiconductor memory with the pass voltage of the nonvolatile semiconductor memory according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to a nonvolatile semiconductor memory device that is electrically erasable and programmable.

Many devices controlled by modern computers or microprocessors require the development of high density electrically erasable and programmable nonvolatile semiconductor memory devices (hereinafter referred to as EEPROMs).

1 shows a memory cell array of NAND flash memory.

Referring to FIG. 1, floating gate MOS transistors (referring to MOS transistors having a source, a drain, a floating gate, and a control gate; hereinafter referred to as memory transistors) are the source of the first selection transistor ST1 and the drain of the second selection transistor ST2. The drain-source passages are composed of memory transistors M1 to M8 connected in series. The gates of the first and second selection transistors ST1 and ST2 and the control gates of the memory transistors M1 to M8 are SL1 and SL2 and word lines under first and second selections perpendicular to the bit lines BL1 to BLn. It is connected to each of WL1 to WL8. Therefore, the memory transistors M1 to M8 are located at intersections between the word lines WL1 to WL8 and the bit lines BL1 to BLn, respectively. Drains of the first select transistors ST1 are connected to the corresponding bit lines BL1 to BLn, respectively, and sources of the second select transistors ST2 are connected to the common source line CSL. As a result, the memory cell array is composed of memory cells. A case in which one of the memory cells is to be selected and programmed will be described with only four bit lines BL1 to BL4 shown in the drawing among the bit lines BL to BLn. When the selected memory cell is referred to as the memory transistor M22, a high program voltage of about 18 to 20V is applied to the selected word line WL2 to allow electrons to tunnel from the channel region of the memory cell M22 to the floating gate. The non-selected memory cells M12, M32, and M42, which are commonly connected to the selected word line WL2 to which the program voltage is applied and remain erased, or whose program is completed, are no longer programmed even when the high program voltage is applied. In order to satisfy this condition, a power supply voltage VCC is applied to the bit lines BL1, BL3, and BL4 connected to the unselected memory cells M12, M32, and M42. Apply the ground power supply VSS. On the other hand, a pass voltage of about 8V to 11V is applied to the unselected word lines WL1 and WL3 to WL8, and the pass voltage is the non-selected memory cells M12 and the potential applied to the unselected bit line BL2. The unselected word lines WL1 and WL3 to 1V to 2V higher than the threshold voltages (Vt) of the unselected memory cells M12, M32 and M42 so as to be sufficiently delivered to the sources and drains of the M32 and M42. The voltage applied to WL8. A more detailed description will be presented with reference to FIG. 2 below.

2 is a cross sectional view of a floating gate mode transistor.

Referring to FIG. 2, the floating gate mode transistor includes a channel region formed between the N-type regions 2 and 3 and the N-type regions 2 and 3 formed by being heavily doped in the substrate 1. 4) and a floating gate 5 formed on the substrate 1 and a control gate 6 formed on the floating gate 5.

In order to program a memory cell that desires data, the program protection operation for the unselected memory cells M12, M32, and M42 should be performed well. The program protection is common to the gates of the unselected memory cells M12, M32, and M42. The program voltage is applied so that sufficient voltage for Fowler-Nordheim tunneling may not be induced between the channel region 4 and the floating gate 5. This reduces the voltage difference between the channel region 4 and the floating gate 5 by using the capacitor coupling effect of the potential of the channel region 4 by the pass voltage. can do. In addition, the conventional NAND type flash memory device having a page buffer structure applies the program protection operation to the unselected memory cells M12, M32, and M42 when performing a program operation. If the amount of change that increases the potential of the region is small, sufficient program protection will not be achieved. In addition, as the number of programs increases, a stress (VPGM STRESS) increases in program voltages in the non-selected memory cells M12, M32, and M42, and even if a memory cell that should not be programmed is programmed, the program is performed, causing a malfunction. Let's do it. To eliminate the cause of the malfunction, there is a method of increasing the channel potential by increasing the pass voltage by increasing the pass voltage, but in this case, the stress caused by the pass voltage causes the pass voltage to continue to increase above a certain level. Has the problem that it is impossible.

Accordingly, an object of the present invention is to provide a method for reducing stress caused by a program voltage without increasing the pass voltage.

Another object of the present invention is to provide a method of increasing channel potential during program prevention by precharging the channel potential to a predetermined level before the pass voltage and the program voltage are applied.

According to the inventive concept of the present invention, a program voltage is applied to a selected word line to program a selected memory cell, and a memory cell not to be programmed to be connected to the selected word line is programmed. Applying a pass voltage, applying a pre-charge voltage for precharging the memory cells before applying the pass voltage, applying ground power to the bit line of the selected memory cell, The bit line has a program prevention method characterized by applying a power supply voltage.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

It should be noted that like elements and parts in the figures represent the same numerals wherever possible.

The present invention will be explained with reference to FIG. 1, which shows a cell array of NAND flash memory.

Summarizing the problem occurring when the program prevention method is applied with reference to FIG. 1, unselected word lines in the selected string (refering to memory cells between the common source line CSL and the second selection transistor ST2). Compared to when the memory cells connected to WL1 and WL3 to WL8 are in an on state, the final channel potential is lowered, so that the stress caused by a high program voltage increases when a plurality of programs are repeatedly executed. This will cause unwanted program behavior. In order to solve this problem, the channel potential of the memory cells is precharged to a predetermined level before the pass voltage and the program voltage are applied, so that the channel potential is increased by the charge coupling effect. This method applies a voltage for precharging bit lines BL1 to BLn before the program voltage and the pass voltage are applied. This figure is shown in FIG.

3 shows a conventional pass voltage application signal and a precharge signal applied before the pass voltage application according to the present invention.

Referring to FIG. 3, the precharge signal has a voltage value between 4 and 8 volts.

4 is a diagram comparing the difference between the conventional pass voltage band threshold voltage and the pass voltage band threshold voltage according to the present invention.

Referring to the drawings, it can be seen that the NAND flash memory according to the present invention has a high threshold voltage at a low pass voltage.

As described above, the NAND flash memory according to the present invention has an advantage of reducing stress caused by the program voltage without increasing the pass voltage. In addition, there is an advantage that can eliminate the cause of malfunction when the program is prevented.

Claims (3)

CLAIMS 1. A method for programmatically erasing memory cells and programming-protecting non-selected memory cells of a nonvolatile semiconductor memory, the method comprising: applying a pass voltage so as not to program a memory cell that should not be connected to the selected word line; And applying a precharge voltage to precharge the memory cell before. The method of claim 1, wherein the pass voltage has a voltage value between 8 volts and 11 volts. The method of claim 1, wherein the precharge voltage has a voltage value between 4 volts and 8 volts.