KR0156434B1 - Frequency fourth-multiplication circuit - Google Patents

Abstract

The present invention relates to a quadruple circuit for quadrupling two pulse signals having a phase difference of 90 °, and outputs a quadruple pulse of A phase pulse and B phase pulse using four D-flip flops and an OR gate. It can be designed with a simple configuration to reduce costs and reduce the assembly process, is not sensitive to the error of the encoder, it is composed only of digital elements and can easily interface with the digital system.

Description

Four times frequency multiplier

1 is a block diagram of a conventional multiplication circuit.

FIG. 2 is a part timing diagram of FIG. 1.

3 is a block diagram of a conventional multiplication circuit.

4 is a part timing diagram of FIG.

5 is a configuration diagram of a quadruple circuit according to the present invention.

6 is a part timing diagram of FIG. 5.

* Explanation of symbols for main parts of the drawings

1: 1D-flip flop 2: 2D-flip flop

3: 3D-flip flop 4: 4D-flip flop

5: ORA gate 6: 5D-flip flop

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to quadrupling circuits, and more particularly to quadrupling circuits for quadrupling two pulse signals having a 90 [deg.] Phase difference.

As shown in FIG. 1, the conventional four-multiplier circuit includes a first D-flip flop 51 in which an A-phase pulse Fa is input to an input terminal D and a clock signal is input to a clock terminal CLOCK. An output terminal Q1 of the first D-flop flop 51 and an input terminal D, and a second D-flip flop 52 through which the clock signal is input to a clock terminal CLOCK; A 3D-flip-flop 53 in which a B-phase pulse Fb having a 90 ° phase difference from Fa is input to the input terminal D, and the clock signal is input to the clock terminal CLOCK, and the 3D The output terminal Q1 and the input terminal D of the flip flop 53 are connected, and the fourth D-flip flop 54 is inputted with the clock signal CLOCK.

Further, the output signals Fa1, Fa2, Fb1, of the A-phase pulse Fa, the B-phase pulse Fb, and the first, second, third, and fourth D-flop flops 51, 52, 53, and 54 A plurality of inverters 55 for inverting Fb2, and the A-phase pulse Fa, the B-phase pulse Fb, the first, second, third, and fourth D-flop flops 51, 52, 53, 54 Output signals Fa1, Fa2, Fb1, Fb2 and a plurality of AND gates 56 to which the output signals of the plurality of inverters 55 are input, and a plurality of AND gates 56 to which the output signals of the AND gate 56 are input. JK-flip-flop that outputs an up / down signal by inputting an OR gate 57 and an output signal of the OR gate 57 to input terminals J and K, and the clock signal to a clock terminal CLOCK. It consists of 58.

Referring to the operation of the quadruple circuit configured as described above with reference to the timing diagram of FIG. 2, the A-phase pulse Fa and the B-phase pulse Fb respectively rise at the rising edge of the clock signal, and the 1D-flip-flop An output signal Fa1 of 51 is a signal in which the A-phase pulse Fa is delayed by one clock, and an output signal Fa2 of the second D-flip flop 52 is two clocks of the A-phase pulse Fa. This is a delayed signal.

In addition, the 3D-flip flop 53 is a signal in which the B-phase pulse Fb is delayed by one clock, and the output signal Fa2 of the 4D-flip flop 54 is the two-phase pulse Fb in two clocks. This is a delayed signal.

The A-phase pulse Fa and the B-phase pulse Fb are passed through the inverter 55, the AND gate 56, and the OR gate 57, and then output as quadrupled pulses. The JK-flip flop 58 Will output an up / down signal.

However, the conventional multiplier circuit has a problem in that the complexity of the configuration increases the cost due to components, has a time delay due to the multi-stage gate between the input and the output, and reacts sensitively to the error of the encoder.

Another conventional quadrature circuit has a plurality of exclusive oar gates 61, 62, and 63, in which phase A and B phase pulses having a phase difference of 90 ° are input as shown in FIG. Resistors (R) and capacitors (C), a plurality of D-flip flops (64, 65), inverters (66, 67, 68, 69) for inverting the pulse signal, up 4 multiply pulses and down 4 4 is composed of a plurality of AND gates 70 and 71 for outputting a multiplication pulse. FIG.

However, the conventional multiplication circuit of the related art has a problem in that the duty ratio of the output multiplication pulse is not constant because the delay time varies depending on the temperature because the delay is made by the resistor and the condenser.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and designed with a simple configuration to reduce the cost and assembly process, and is not sensitive to the error of the encoder, it is composed only of digital elements and easy to use digital system The purpose of the present invention is to provide a quadrupling circuit that can interface easily.

The multiplication circuit of the present invention for achieving the above object comprises a first D-flip flop is applied a signal of the 'high' level to the input terminal, the A-phase pulse is input to the clock terminal and cleared by the clock signal; A second D flip-flop that is applied with a signal of a 'high' level to an input terminal and to an inverted A-phase pulse to a clock terminal and is cleared by a clock signal; A 3D-flip-flop that is applied with a 'high' level signal as an input step, a B-phase pulse is input to the clock terminal, and is cleared by the clock signal; A fourth D flip-flop that is applied with a 'high' level signal to an input terminal and is inverted to a clock terminal with a B-phase pulse input and cleared by a clock signal; And an OR gate for inputting a signal of an output terminal of the first, second, third, and fourth 4D flip-flops and outputting a multiplication pulse.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a four-multiplier circuit according to the present invention, in which a signal of the 'high' level is applied to the input terminal D, an A phase pulse is input to the clock terminal CLOCK, and the clock signal is the clear terminal CLEAR. 1D-flip flop (1) input to; A 2D-flip where a 'high' level signal is applied to the input terminal D, an A phase pulse (A / phase pulse) inverted to the clock terminal CLOCK, and a clock signal is input to the clear terminal CLEAR. It is comprised by the flop 2.

In addition, the 3D-flip-flop (3) to which a high level signal is applied to the input terminal (D), the B-phase pulse is input to the clock terminal (CLOCK), and the clock signal is input to the clear terminal (CLEAR); The 4D-flip-flop (where the high level signal is applied to the input terminal D, the B-phase pulse (B / phase pulse) inverted to the clock terminal CLOCK) is input, and the clock signal is input to the clear terminal CLEAR ( 4); And an OR gate for inputting signals of the output terminals Q1, Q2, Q3, and Q4 of the first, second, third, and fourth D flip-flops 1, 2, 3, and 4, and outputting a multiplication pulse. It consists of (5).

In addition, the four-multiplier circuit described above has a fifth D flip-flop that inputs an A phase pulse to an input terminal D, an B phase pulse to a clock terminal CLOCK, and outputs an up / down signal to an output terminal Q. It is comprised including (6).

Referring to the operation and effect of the present invention configured as described above with reference to the timing diagram of Figure 6, the output terminal (Q1) of the 1D-flip flop (1) outputs a signal of the 'low' level while the A-phase pulse When the rising edge is inverted to the 'high' level, when the clock signal is falling, it is creeped and outputs a signal inverted from the 'high' level to the 'low' level.

In addition, the output terminal Q2 of the 2D flip-flop 2 outputs a 'low' level signal and is inverted to a 'high' level when the A / phase pulse is a rising edge, and when the clock signal is a falling edge. Cree outputs a signal that is inverted from the 'high' level to the 'low' level.

In addition, the output terminals Q3 and Q4 of the 3D-flip-flop 3 and the 4D-flip-flop 4 are also inverted to the 'high' level at the rising edges of the B-phase pulse and the B / phase pulse, respectively, and are clock signals. It outputs a signal inverted to the 'low' level at the falling edge of.

The signals output from the output terminals Q1, Q2, Q3, and Q4 of the first, second, third and fourth D flip-flops 1, 2, 3, and 4 described above are combined at the OR gate 5, and The OR gate 5 outputs a multiplication pulse of the A-phase pulse and the B-phase pulse.

At this time, the 5D-flip flop 6 outputs a 'high' level signal as an up / down signal when the A-phase pulse precedes the B-phase pulse, and as an up / down signal when the B-phase pulse precedes the A-phase pulse. It outputs a low level signal and indicates the direction of rotation of the motor.

As described above, the present invention can output four multiply pulses of A-phase pulse and B-phase pulse by using four D-flip flops and OR gates, thereby reducing costs and reducing the assembly process by designing a simple configuration. In addition, it is not sensitive to the error of encoder and consists only of digital elements, so it can easily interface with digital system.

Claims (2)

A first D flip-flop (1) to which a high level signal is applied to the input terminal (D), an A-phase pulse is input to the clock terminal (CLOCK), and cleared by a clock signal; A second D flip-flop 2 that is supplied with a 'high' level signal to the input terminal D and an A-phase pulse inverted to the clock terminal CLOCK and is cleared by the clock signal; A 3D-flip-flop 3 which is applied with a 'high' level signal to the input terminal D and a B-phase pulse is input to the clock terminal CLOCK and cleared by the clock signal; A 4D-flip-flop (4) to which a 'high' level signal is applied to the input terminal (D) and an inverted B-phase pulse is input to the clock terminal (CLOCK) and cleared by the clock signal; And an OR gate for inputting signals of the output terminals Q1, Q2, Q3, and Q4 of the first, second, third, and fourth D flip-flops 1, 2, 3, and 4, and outputting a multiplication pulse. 4 multiplication circuit characterized by consisting of (5). The D-flip flop (6) according to claim 1, wherein an A-phase pulse is input to the input terminal (D), a B-phase pulse is input to the clock terminal (CLOCK), and an up / down signal is output to the output terminal (Q). Quadruple circuit, characterized in that configured to include.