KR0156153B1 - Sram & its manufacturing method - Google Patents

Abstract

The SRAM cell according to the present invention is a process of isolating a plurality of active regions and field regions in a surface of a semiconductor substrate, and forming a common gate electrode and a plurality of impurity regions respectively on and in the active regions. Forming a second bulk transistor, forming a gate oxide film on the common gate electrode, forming a conductive layer forming a thin film transistor body on the gate oxide film, and forming the conductive layer into the first and second bulk transistors. Two thin film transistors are formed by etching back the upper portion of the common gate electrode and the upper portions of the common gate electrodes, and leaving the upper portion of each of the common gate electrodes of the second bulk transistor only on the transistor connection portions that overlap each other by a predetermined length. It is made, including the process.

Description

SRAM and its manufacturing method

1 is an equivalent circuit diagram of a conventional SRAM cell.

2A is a layout view of bulk transistors that are components of a conventional SRAM cell.

2b is a layout view of thin film transistors that are components of a conventional SRAM cell.

FIG. 3 is a layout plan view of the thin film transistors of FIG. 2b stacked on the bulk transistors of FIG. 2a.

4 is a cross-sectional view of a conventional SRAM cell taken along line IV-IV of FIG.

5 is a cross-sectional view of a conventional SRAM cell taken along the line VV of FIG.

6 is a layout plan view of an SRAM cell according to the present invention;

FIG. 7 is a cross-sectional view of the SRAM cell taken along the line VII-VII of FIG. 6. FIG.

8 is a cross-sectional view of the SRAM cell taken along the line VII-VII of FIG.

9A to 9G are sectional views of the manufacturing process of the SRAM cell taken along the line VII-VII of FIG.

10A to 10G are sectional views of the manufacturing process of the SRAM cell taken along the line VII-VII of FIG.

* Explanation of symbols for main parts of the drawings

1 semiconductor substrate 2 active region

2a: field region 3: first gate oxide film

4: cap nitride film 5: common gate electrode

6 sidewall oxide film 7: first impurity region

9: second impurity region 10: first BPSG layer

11: second gate oxide film 12: Vcc connection

13 conductive layer 14 transistor connection portion

15: intermediate insulating film 17: the first contact hole

18: Vss line 19: the second BPSG layer

21: second contact hole 23: bit line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to an SRAM cell and a manufacturing method thereof.

Typically, an SRAM cell consists of four transistors (eg, two access transistors and two drive transistors) and two polysilicon load resistors, or six transistors.

In particular, the 4M or higher integrated cell is generally configured in a CMOS type consisting of four NMOS transistors and two PMOS transistors.

1 is an equivalent circuit diagram of a conventional SRAM cell of CMOS type.

In the figure, four NMOS transistors Q ₁ to Q ₄ are formed on a semiconductor substrate, and two PMOS transistors Q ₅ and Q ₆ are formed in the form of a thin film transistor on the NMOS transistors.

Referring to the accompanying drawings, a method for manufacturing a conventional SRAM cell having such a configuration is as follows.

FIG. 2A is a layout plan view of bulk transistors as a component of a conventional SRAM cell, and FIG. 2B is a layout plan view of thin film transistors as a component of a conventional SRAM cell.

FIG. 3 is a layout plan view of an SRAM cell having a structure in which the thin film transistors of FIG. 2b are stacked on the bulk transistors.

FIG. 4 is a cross-sectional view of the SRAM cell taken along the line IV-IV of FIG. 3, and FIG. 5 is a cross-sectional view of the SRAM cell taken along the line V-V of FIG.

According to the drawings, a conventional method of manufacturing an SRAM cell is prepared by first defining a semiconductor substrate 31 and defining active regions 32 and field regions 32a on the semiconductor substrate 31.

Next, a first gate oxide layer 33 is formed on the active regions 32.

Subsequently, polysilicon and capgate nitride film 34 are sequentially deposited on the gate oxide film 33, and the first gate electrode 35 of the bulk transistor is defined by a photoetch process.

Subsequently, sidewall oxide layers 37 are formed on both sides of the first gate electrode 35.

Next, first polysilicon is implanted into the active region to form first and second impurity regions 39 and 41.

Then, the first intermediate insulating film 43 is deposited on the entire surface of the substrate, and then etched to expose a predetermined portion of the substrate 31.

A second polysilicon is deposited on the first intermediate insulating layer 43 to contact the first impurity region 39 to form a Vss line 44.

Subsequently, the second intermediate insulating layer 45 and the third polysilicon are sequentially deposited on the Vss line 44.

The third polysilicon layer is then patterned by a photoetch process to define the second gate electrode 46 of the thin film transistor.

Then, the second gate oxide film 47 and the fourth polysilicon are deposited on the entire surface of the substrate, and then the offset mask 48 is covered thereon.

Subsequently, the body 49 of the thin film transistor having a source region, a drain region, and a channel region is formed by doping the p-type impurity thereon.

Subsequently, heat treatment is performed to improve the characteristics of the transistor to increase grain size.

After the photosensitive and etching process, the wiring process is completed to complete the SRAM cell.

The SRAM cell formed by the above manufacturing process sequence has the following problems.

First, when the thin film transistor is formed on the bulk transistor, a second gate electrode must be formed separately from the first gate electrode, thereby increasing the number of cell providing processes.

In addition, since the offset mask position of the thin film transistor depends on the arrangement state of the bulk transistor, the exact offset alignment is difficult, so the characteristics of the thin film transistor tend to be poor.

In addition, since the second gate electrode for the thin film transistor and the thin film transistor body must be formed on the bulk transistor, the wiring step becomes difficult because the cell step becomes larger.

The present invention has been made to solve the above problems, and an object of the present invention is to use a common gate electrode of a bulk transistor as a gate electrode of a thin film transistor to reduce the number of cell manufacturing process SRAM cell and its manufacturing method To provide.

Another object of the present invention is to provide an SRAM cell and a method of manufacturing the same, which facilitates offset alignment and improves characteristics of a thin film transistor.

It is still another object of the present invention to provide an SRAM cell and a method of manufacturing the same, which reduce wiring steps and facilitate the wiring process.

An SRAM cell according to the present invention for achieving the above object comprises a semiconductor substrate, active regions defined within the surface of the semiconductor substrate, two gate electrodes formed on top and each of these active regions, and a plurality of impurity regions. First bulk transistors, two second bulk transistors each comprising a plurality of impurity regions and a common gate electrode formed in each of an upper portion and a surface of the active regions separated by a predetermined length from the two first bulk transistors, It includes two thin film transistors formed on two second bulk transistors and using the common gate electrode as an electrode and formed on the cavity gate electrode to form a thin film transistor body.

A method of manufacturing an SRAM cell according to the present invention comprises the steps of preparing a semiconductor substrate, isolating and forming a plurality of active regions and field regions in the surface of the semiconductor substrate, a common gate electrode in each of the top and the surface of the active regions; Forming a plurality of first and second bulk transistors by forming a plurality of impurity regions, forming a gate oxide film of a thin film transistor on the common gate electrode, and forming a conductive layer forming a thin film transistor body on the front surface of the substrate. And a Vcc connection portion that overlaps each upper portion of the first and second bulk transistors with each other by a predetermined length, and the conductive layer so as to remain only in a transistor connection portion that overlaps an upper portion of each common gate electrode of the second bulk transistor by a predetermined length. Etching to form a thin film transistors .

The present invention will be described in detail with reference to the accompanying drawings.

6 is a layout plan view of an SRAM cell according to the present invention.

FIG. 7 is a cross-sectional view of the SRAM cell taken along the line VII-VII of FIG. 6, and FIG. 8 is a sectional view of the SRAM cell taken along the line VII-VII of FIG.

According to the drawings, an SRAM cell according to the present invention comprises four first and second bulk transistors formed on the semiconductor substrate 1 and two thin film transistors formed on the two second bulk transistors. It is composed.

Each of the four first and second bulk transistors includes a first gate oxide film 3 formed on active regions 2 defined in the surface of the semiconductor substrate 1, and on the first gate oxide film 3. The formed common gate electrodes 5 and first and second impurity regions 7 and 9 formed in the surface of the semiconductor substrate 1 and used as source and drain regions.

The sidewall oxide film 6 is formed on both sides of the common gate electrode 5.

Further, the first BPSG layer 10 is formed in the corrugated portions between the sidewall oxide films 6.

On the other hand, each of the two thin film transistors uses a common gate electrode 5 of the second bulk transistor as a gate electrode, and a second gate oxide film 11 formed on the common gate electrode 5, the second The conductive layer 13 is formed on the gate oxide film 11 and used as a source region, a drain region, and a channel region.

Here, the conductive layer 13 is connected to the Vcc connection portion 12 overlapping a predetermined portion of each of the first bulk transistors and the second bulk transistors.

In addition, the conductive layer 13 is connected to a transistor connecting portion 14 overlapping a predetermined portion of each upper portion of the second bulk transistors.

An intermediate insulating film 15 is formed on the conductive layer 13.

A Vss line 18 is formed on the intermediate insulating film 15, and the Vss line 18 is connected to the first impurity region 7 of the second bulk transistors.

The second BPSG layer 19 is formed on the Vss line 18.

In addition, a bit line 23 is formed on the second BPSG layer 19 to be in contact with the first impurity region 7 of the first bulk transistors.

A method of manufacturing an SRAM cell according to the present invention having the above configuration will be described in detail with reference to FIGS. 9A to 9G and 10A to 10G.

9A to 9G are cross-sectional views of the manufacturing process of the SRAM cell of FIG. 6, and FIG. 10A to 10g are cross-sectional views of the manufacturing process of the SRAM cell, of FIG.

In the method for manufacturing an SRAM cell according to the present invention, first, as shown in FIGS. 9A and 10A, first, a semiconductor substrate 1 is prepared, and then active regions 2 and a field region in the surface of the semiconductor substrate 1 are prepared. Field (2a) is defined by limiting it through the local oxidation (LOCOS) process.

Next, after forming the first gate oxide film 3 on the active regions 2, the first gate oxide film 3 is contacted by restricting a predetermined portion of the active region.

Subsequently, as shown in FIGS. 9B and 10B, polysilicon is deposited on the first gate oxide film 3 to a predetermined thickness.

Then, the cap nitride film 4 is deposited on the polysilicon layer, and then the common gate electrode 5 is formed through a photoetch process.

Subsequently, an oxide film is deposited on the entire surface of the substrate and then etched through an anisotropic dry etching process to form sidewall oxide films 6 on both sides of the common gate electrode 5.

The first and second impurity regions 7 and 9 are then formed on the semiconductor substrate 1 by doping n ⁺ impurity on the active region 2 to form the source and drain regions. 2 Complete the bulk transistors.

Subsequently, the first BPSG layer 10 is formed by depositing a BPSG or USG material on the corrugated portion of the sidewall oxide film 6 so as to planarize the substrate surface.

Next, as shown in FIGS. 9C and 10C, the first BPSG layer 10 is etched back so that the cap nitride film 4 formed on the common gate electrode 5 is exposed.

Subsequently, the cap nitride film 4 is removed by a wet etching method so that only the predetermined portion of the common gate electrode of each of the second bulk transistors ends, that is, the PMOS type thin film transistors.

Then, the exposed upper portions of the first and second bulk transistors are oxidized to form a second gate oxide layer 11 of the thin film transistors.

Subsequently, polysilicon is deposited on the entire surface of the substrate by a predetermined thickness.

Subsequently, the polysilicon layer is etched back so as to remain only on the first and second bulk transistors, the Vcc connector 12, and the transistor connector 14, thereby forming a conductive layer 13 used as a channel region, a source region, and a drain region. .

In this case, the Vcc connection part 12 is formed by overlapping a mask pattern on each of the first and second bulk transistors by a predetermined length and then contacting the conductive layer 13.

In addition, the transistor connection part 14 is formed by overlapping a mask pattern on each of the second bulk transistors by a predetermined length and then contacting the conductive layer 13.

As shown in FIGS. 9d and 10d, an intermediate insulating layer 15 is then coated on the entire surface of the substrate and then etched back to expose the first impurity region 7 of the second bulk transistors. 17).

9E and 10E, polysilicon is deposited on the intermediate insulating layer 15 to contact the first impurity region 7 through the first contact hole 17, and then etched it back. To form the Vss line 18.

As shown in FIGS. 9F and 10F, a second BPSG layer 19 is formed by applying a BPSG material to the entire surface of the substrate.

Next, the second BPSG layer 19 is etched back to expose the first impurity region 7 of the first bulk transistors to form a second contact hole 21 for metal contact.

Claims (18)

Semiconductor substrate: active regions defined in the surface of the semiconductor substrate: two first bulk transistors each comprising a common gate electrode and two impurity regions formed on and in each of these active regions, respectively: the first two bulk transistors Two second bulk transistors each having a common gate electrode and two impurity regions respectively formed on the top and the surface of each of the active regions separated by a predetermined length from each other and formed on the two second bulk transistors. An SRAM cell comprising an electrode as an electrode and comprising two thin film transistors formed of a conductive layer formed on the common gate electrode to form a transistor body. The SRAM cell of claim 1, wherein the conductive layer comprises a source region, a drain region, and a channel region of a thin film transistor. The SRAM cell of claim 1, wherein the conductive layer includes a Vcc connection portion overlapping a portion of the conductive layer formed on each of the first and second bulk transistors by a predetermined length. 4. The SRAM cell of claim 3, wherein the conductive layer portion on the second bulk transistor overlapping the Vcc connection portion forms a conductive layer of the thin film transistor. The SRAM cell of claim 1, wherein the conductive layer includes a transistor connection part overlapping a portion of the conductive layer formed on each of the second bulk transistors by a predetermined length. 6. The SRAM cell of claim 5, wherein the conductive layer portion on the second bulk transistor overlapping the transistor connection portion forms a conductive layer of the thin film transistor. 7. The SRAM cell of claim 6, wherein a conductive layer portion of each of the second bulk transistors except for the portion overlapping the Vcc and transistor connections forms a channel region of the thin film transistor. The SRAM cell according to claim 1, wherein a capzilization film is formed on a predetermined portion of each of the common gate electrodes of the second bulk transistors. 10. The SRAM cell of claim 8, wherein the encapsulation film is in contact with the transistor connection portion. 10. The SRAM cell of claim 8, wherein the encapsulation film insulates the two thin film transistors from each other. A process for providing a semiconductor substrate, comprising: separating a plurality of active regions and field regions within a surface of the semiconductor substrate: forming a common gate electrode and two impurity regions in the upper and the surface of the active regions, respectively, At the same time as forming one bulk transistors, two second bulk transistors are formed by forming a common gate electrode and two impurity regions in an upper portion and a surface of each of the active regions separated by a predetermined length from the plurality of first bulk transistors. A process of forming a gate oxide film on the entire surface of the substrate. A process of forming a conductive layer forming a thin film transistor body on the gate oxide film. The conductive layer is formed on top of a common gate electrode of the plurality of first and second bulk transistors. Vcc connection portions which overlap each of these upper portions by a predetermined length, and the second bulk Production process of the SRAM cell formed by a step of forming two thin-film transistors by etching back a common gate electrode to the top of the registers be left solely to the transistor connecting to overlap by a predetermined length 12. The method of claim 11, wherein the forming of the common gate electrode comprises depositing a polysilicon layer on active regions: depositing a cap nitride layer on the polysilicon layer to etch a predetermined portion by a photoetching process. Manufacturing method of SRAM cell comprising The method of claim 11, wherein the forming of the impurity regions comprises forming a sidewall oxide film on both sides of the common gate electrode, and implanting impurities into each active region to form first and second impurity regions in each active region. Method of manufacturing an SRAM cell comprising the step of. The method of claim 12, wherein etching the cap nitride layer comprises applying a BPSG layer to the corrugated portion of the common gate electrode side so as to planarize the entire surface thereof, and applying the BPSG layer to expose the cap nitride layer on the common gate electrode. And etching the cap nitride layer so as to remain only in a predetermined portion of the upper portion of the common gate electrode of the second bulk transistor. 15. The method of claim 14, wherein the cap nitride film is etched by a wet etching process. The method of claim 11, wherein the forming of the Vcc connectors comprises: forming a conductive layer on the front surface of the substrate, and forming a mask pattern on the conductive layer such that upper portions of the first and second bulk transistors overlap each other by a predetermined length. And etching back the conductive layer so as to remain only on the first and second bulk transistors including the mask pattern. The method of claim 11, wherein the forming of the transistor connections comprises forming a conductive layer on the entire surface of the substrate, and forming a mask pattern on the conductive layer so that the upper portions of the second bulk transistors overlap each other by a predetermined length. And etching back the conductive layer so as to remain only on the first and second bulk transistors including the pattern. 18. The method of claim 17, wherein the forming of the transistor connection portion comprises disposing one end of the mask pattern in contact with the cap nitride film portion.