KR0155330B1 - Structure of evaluation system for digital base band of cdma subscriber - Google Patents

Abstract

The present invention relates to an evaluation system architecture for a digital baseband system of a CDMA mobile station.

To enhance the competitiveness of the CDMA system, especially the vocoder responsible for encoding and decoding voice signals in the digital baseband of a mobile station, a modem for performing codes, modulation, demodulation and decoding functions, and call processing software based on IS-95 are performed. The first chip of the microcontroller, which is in charge of controlling the entire system, comes first.

However, it is necessary to check whether the digital baseband system of the mobile station performs the call processing algorithm according to the standard in connection with the base station, and at the same time, to check the function at the system level after the 1 chip of each separately manufactured ASICs. Evaluation system is required.

Evaluation system according to the present invention is a basic and essential system to be carried out with the 1chip of CDMA mobile base station digital baseband system, the function check of vocoder including loop-back test, and the call processing program of modem ASIC by message logging. It can also be used for the development of call processing programs themselves.

The evaluation system according to the present invention is the only system having a structure that can check only the digital baseband providing the CDMA source technology in association with the call processing algorithm without including the analog baseband, the IF unit and the RF unit. Its simplicity and simplicity of use due to not including the analog part is characterized by.

Description

Evaluation System Architecture for Digital Baseband System of CDMA Mobile Station

1 is a CDMA mobile baseband baseband evaluation system architecture

2 is a detailed configuration diagram of the PCB in FIG.

3 is a general flow diagram of the signals in the evaluation system.

4 is a serial input timing diagram of DSP2.

5 is a serial output timing diagram of DSP2.

6 is a parallel input timing diagram of DSP2.

7 is a parallel output timing diagram of DSP2.

8 is a codec timing diagram (short frame synchronization mode).

9 is an interface timing diagram between DSP2 and a codec.

10 is a software architecture for a digital baseband evaluation system of a CDMA mobile station.

11 is for the interface between CPU1 and DSP2, (a) data flow, (b) software configuration.

12 shows the structure of (a) command packet and (b) response packet between CPU1 and DSP2.

The present invention relates to an evaluation system structure for a digital baseband system of a CDMA mobile station, and more particularly, to evaluate the performance of a digital baseband system of a CDMA mobile station that satisfies the provisional standard IS-95 of a broadband spread spectrum cellular system. ) Structure of the system.

Code Division Multiple Access (CDMA) mobile communication system is a broadband spread spectrum cellular that supports 10 times more subscribers with digital system reliability than analog frequency division multiple access (FDMA) mobile communication system that is currently being serviced. System.

In order to enhance the competitiveness of the CDMA system, a vocoder which codes and decodes a voice signal in a mobile digital baseband, a modem that performs a code, modulation, demodulation, and decoding function, and call processing software based on IS-95 are used. One chip of the microcontroller that executes and takes charge of system-wide control comes first.

However, it is necessary to check whether the digital baseband system of the mobile station performs the call processing algorithm according to the specification in connection with the base station, and at the same time, to check the function at the system level after the 1 chip of each separately manufactured ASICs. An evaluation system is required.

The evaluation system for only the modem portion of the mobile station digital baseband system has been described in detail in the previously published patent 94-35485, but a more advanced evaluation system is required to check the functions including the encoding and decoding of the vocoder speech signal. Shall be.

The present invention is the only system having a structure that can check only the digital baseband providing the CDMA source technology, in association with the call processing algorithm, without including the analog baseband, the IF unit, and the RF unit. It is an object of the present invention to provide an evaluation system structure for the digital baseband system of a CDMA mobile station for ease of use due to the absence of a portion.

The evaluation system according to the present invention is a basic and essential system to be performed along with the one-chip of the CDMA mobile base station baseband system, and the function of the vocoder including the loop-back test and message logging. It can be used to check whether the modem ASIC executes the call processing program and to develop the call processing program itself.

Before describing the present invention in detail, the overall configuration of the CDMA system will be briefly described.

CDMA, a type of digital cellular communication system, consists of a mobile station, a base station, and a switching station, and a dual mobile station consists of an RF system, an IF system, an analog baseband, and a digital baseband.

Major components of the digital baseband include an Integrated Mobile-Station Modem (IMM) 1 ASIC, a digital signal processor (DSP 2) that performs a variable rate speech processing algorithm, and a 16-bit microcontroller (CPU1).

IMM 1, which is responsible for the modulation and demodulation of CDMA broadband volcanic spectrum signals, consists of an encoder, a modulator, a demodulator, and a Viterbi decoder.

One embodiment of the overall structure of the hardware and software of the CDMA mobile base station baseband evaluation system according to the present invention, and one embodiment of the detailed structure of the PCB portion for processing the function of the mobile station in the digital baseband in real time concept Same as 1 degree and 2 degree.

On the host PC, data that has passed through the base station, multipath fading channel, and AGC (Automatic Gain Controller) is stored in a file, which is input / output to the PCB which is responsible for the function of the mobile station for each interrupt. The Diagnostic Monitor, the keypad of the mobile station and the ringer of the mobile station replace the function with the CRT, keyboard and speaker of the host PC.

The call processing program is converted to binary format, stored in a file on the host PC's hard disk, and then moved to SRAM, which acts as an EPROM at system startup.

The evaluation system controller (software) is responsible for controlling other software and exchanging 10-bit address and 8-bit data with the PCB via the ISA bus.

In addition, various data inputted and outputted are stored or displayed on the LCD according to selection.

That is, it is in charge of LCD, keypad, signal generator drive routine and control of address, data and control signal.

Programmable CHIPX8 and programmable CLKIN using a counter drive IMM1 and CPU1, and TCXO_CLK is also programmable.

The programmable CHIPX8 is about 10 KHz to 100 KHz, and accordingly, TCXO_CLK and CLK_IN are also scaled down together. In each cycle of programmable CHIPX8, IMM 1 and the host PC interrupt the 8-bit latch to send and receive RXI RXQ and TXIQ data.The time calculated by counting the occurrence of event data and CHIPX8 is counted. You can optionally save to a file on your PC hard disk.

The address of the latch is determined by the address decoder, and the reset register determines whether the evaluation system is driven.

The test mode of IMM 1 is fixed to IMM 1 mode.

1 Kbyte of DPRAM is used for message logging.Up to 128 bytes (I / O map) of messages after each message has been logged, it moves to RAM on the host PC with destination synchronized DMA and displays them on the LCD. After completion of the running test mode, all messages in RAM on the host PC are saved in a file on the host PC. In order to signal the end of each message in the IMM 1 program, a specific value is written to the specific address of the DPRAM, which is checked by the host PC's drive routine at regular intervals to confirm completion of the message, and then moved to RAM on the host PC.

After moving, clear the specific value of specific address.

PCS6 / and BHE / of CPU 1 are applied to CS1 / and CS2 / of DPRAM (I / O map). Instead of using Qualcomm's user interface routines, LCDs, keypads, and beeper driver drivers can be created separately for PCs to handle break functions from the IMM 1 program or break commands from the keypad. Therefore, CPU 1 causes IMM 1 to remain in its current state and then suspends its operation until it enters a continue state.

The break function on IMM 1 puts CPU 1 in power-down mode and IMM 1 in sleep mode, where the data file on the host PC is not interrupted (equivalent to the latch-enable interrupt) and stops working. do.

A break command entered from the keypad holds programmable CLKIN and programmable CHIPX8, effectively deactivating CPU 1 and IMM 1.

One embodiment of the overall flow of signals in the evaluation system is shown in FIG. Because of the underlying conflict between interrupt-based CPU programs and DOS interrupts, data in the hard disk is entered at every interrupt into IMM 1 of the evaluation system at a rate of approximately 50 kbps.

This data on the forward link is demodulated / decoded by the interaction of IMM 1 and CPU 1 and stored in the hard disk of the host PC.

The stored data is input to DSP 2 of the evaluation system and its output is again input to the u-law codec in the evaluation system.

The output of the u-law codec is directly connected to the speaker so that QCELP decoded speech can be heard.

The voice on the reverse link input from the microphone is voice encoded, modulated and stored in the hard disk on the host PC through the above and the reverse process.

Here, one part of the IMM in the evaluation system is difficult to operate in real time, while the Vocoder can be operated in real time, so that the host PC plays an intermediate role.

In other words, the host PC plays the role of a vocoder with the IMM 1 and the CPU 1 and the CPU with the vocoder.

Therefore, it is possible to perform a rope-back test by the vocoder alone, and it does not consider the operation in the microprocessor mode and the use as the In Circuit Emulator (ICE).

The connection of DSP 2 is as follows, and one embodiment of the timing of DSP 2 is shown in FIGS.

1.Set to LOW w.o.interconnection (2-pin)

prom_out (36), mp / mcb (90)

2.Set to HIGH w.o.interconnection (2-pin)

emu_int / (20), addr_out (38)

3. Interconnect (19-pin)

Reset / (14) Host PC

External interrupt (ext_int) VC_FR_REF (58: IMM 2): Supplied by the host PC, only 20ms pulse or substantially the first pulse after the initialize vocoder command is valid, after which 160 input PCM samples are regarded as one frame.

-pio [7: 4] (27:30) ⇔host PC

-piop [3: 0] (32:35) Host PC

-po_sync / (39) Host PC (by ASM in command) cf) VC_WR

-pi_syne / (40) Host PC (by ASM out command) cf) VC_RD

-serial_out (53) ⇒DR (8: CODEC)

-so_sync (54) = FSR (7: CODEC)

-so_clk (55) = BCLKR (9: CODEC)

-si_clk (56) = BCLKT (12: CODEC)

-si_syne (57) = FST (14: CODEC)

-serial_in (59) DT (13: CODEC)

-clk (66) MHz XTAL

The codec (e.g. MC145480) has a 2.048 MHz CODEC_CLK (BCLKT /

BCLKR) (originally supplied as CHIPX8 * 5/24) and CODEC_SYNC at 8KHz

(FST / FSR) (CODEC_CLK / 256), and ignores the advance / retard timing adjustment information for phase adjustment of CODEC_CLK and CODEC_SYNC sent from the symbol combiner of IMM 1 to the interleaving / deinterleaving unit. do.

In other words, fixed CODEC_CLK and CODEC_SYNC are used instead of CODEC_CLK and CODEC_SYNC from IMM 1.

8 shows one embodiment of the codec timing of the short frame synchronization mode, and FIG. 9 shows one embodiment of the interface timing between the DSP 2 and the codec.

An embodiment of the software configuration for the evaluation system according to the present invention is shown in FIG. 10, the configuration of which is connected to the base station emulation software portion which processes data obtained from the base station and the multipath fading channel simulator and the emulation system PCB portion. It is divided into interface modules that perform functions.

In this case, the reception operation includes the function of the Viterbi decoder.

In addition, the software interface between CPU 1 and DSP 2 is always triggered by CPU 1, which is the overall sequence of vocoder initialization, pre / de-emphasis, TX / RX speech data, and vocoder sleep.

An example of the configuration of (a) data flow and (b) software for the interface between CPU 1 and DSP 2 is shown in FIG. An example of the configuration of a packet is shown in FIG.

Tx and Rx frame commands are as follows.

The evaluation system according to the present invention is a basic and essential system to be performed along with one chip of a CDMA mobile base station baseband system. Whether the call processing program of the modem ASIC is performed by checking the function of the vocoder including loop-back-test and logging the message. It can also be used for inspection and development of call processing programs themselves.

As described above, the evaluation system of the present invention is the only system having a structure that can check only the digital baseband providing the CDMA source technology in association with the call processing algorithm without including the analog baseband, the IF unit, and the RF unit. There is simplicity of use due to the simplicity of the whole hardware and not including the analog part.

Claims (4)

CDMA mobile base station baseband evaluation system structure and programmable chip configured to access the mobile station's functions in hardware in the PCB section and the data file that functions as the base station and the 3-path fading channel on the host PC as interrupt driven software. And evaluation system architecture for a digital baseband system of a CDMA mobile station, including an interface device for driving modem ASICs and microcontrollers using programmable CLKIN and enhancing user functionality on the host PC. The CDMA mobile station digital baseband system of claim 1, wherein the PCB unit is configured to drive a message buffer for checking whether a call processing algorithm is performed, a modem ASIC, and a vocoder at a maximum speed within the allowable range. Evaluation system structure. The software structure of claim 1, wherein the software structure between the CPU and the DSP for signal flow in the evaluation system comprises: a base station emulation software portion for processing data obtained from the base station and a multipath fading channel simulator, and an emulation system printed circuit board portion; An evaluation system structure for a digital baseband system of a CDMA mobile station, characterized in that it comprises an interface module that performs a connection function. 4. The evaluation system structure of claim 3, wherein the receiving operation in the base station emulation software portion includes a function of a Viterbi decoder.