KR0153920B1 - Atm physical layer processor for atm communication at pseudo synchronous digital hierachy - Google Patents

Abstract

The present invention relates to a modular ATM physical layer processing apparatus for performing asynchronous transfer mode (ATM) communication on a Plesiochronous Digital Hierarchy (PDH), comprising: a transmission frame information insertion unit (201), a circuit Matching unit 202, physical layer framer 203, transmitting side FIFO 204, receiving side FIFO 205, local oscillator 206, framer control unit 207, FIFO control unit 208, receiving frame information extracting unit 209, status / alarm display section 210, upper layer matching section 211, operation setting register 212, board ID output section 213, and the ITU-TG.703 standard of the International Telecommunication Union and Forum users defined in ATM Forum can effectively configure physical interface for B-ISDN suitable for asynchronous delivery mode communication using quasi-synchronous digital hierarchy according to G.704 and G.804. Network Matching (User Network Interface) Specification By following the UTOPIA physical interface, which is a matching standard between the ATM layer and the physical layer, which is suitable and part of the standard, the additional additional circuit can be minimized. It can be easily used for any physical layer change by implementing the physical layer independently without any change, and the Motorola series can be applied not only to the processor but also to the internal series processor, so it can be used not only for the shelf-type development system but also for the design of the ATM board for the PC. This has a possible effect.

Description

ATM physical layer processing device for asynchronous delivery mode communication on pseudo-synchronous digital hierarchy

1 is a block diagram of a system to which the present invention is applied.

2 is a schematic configuration diagram of an ATM physical layer processing apparatus according to an embodiment of the present invention.

3 is a diagram illustrating a signal definition of a higher layer matching unit according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

201: transmission frame information insertion unit 202: line matching unit

203: physical layer framer 204: transmitting side FIFO

205: receiving side FIFO 206: local oscillator

207: framer control unit 208: FIFO control unit

209: Receive plane information extractor 210: Status / alarm display unit

211: upper layer matching unit 212: operation setting register

213: Board ID Output

The present invention relates to a modular ATM physical layer processing apparatus for Asynchronous Transfer Mode (ATM) communication on a Plesiochronous Digital Hierarchy (PDH).

Recommendations on how to map ATM cells to existing pseudo-synchronous digital hierarchy (PDH) are provided in ITU-T G.804. Looking at the provisions relating to the class 2048kbit / s and 44.736 Mbit / s related to the present invention.

In order to map ATM cells to 2048 kbit / s, the 2048 kbit / s basic frame type in ITU-T G.704 recommendation shall be followed. ATM cells are mapped between bits 9 through 128 and bits 256 through bits 256 (i.e., 15 through timeslots (TS) and 15 through timeslots 17 through 31) on the basic frame.

Time slot 0 is used for the operation management function (OAM) of the network, and it is used for notifying whether the frame boundary identification has failed or for performance monitoring, remote end reception failure, cell boundary identification failure, performance reporting, etc. Burn is used for signaling. For cell rate control, when there are less than one cell to be transmitted in the ATM layer according to ITU-T I.432 recommendation, idle cells are transmitted and filled with the payload capacity of the frame. It provides the function to generate and insert HEC (Header Error Control) value for header error control. The ATM cell payload is to be scrambled before it reaches 2048 kbit / s. The receiving side performs reverse scrambling again to recover the original payload. Cell boundary identification shall be performed in accordance with the HEC (Header Error Control) mechanism in accordance with the ITU-T I.432 Recommendation. It also discards cells when there is an error in header detection and headers, and passes only valid cells to higher layers. The operation management function of the physical layer monitors and displays the far end block error (FEBE), the far end reception failure, and the cell boundary identification failure.

In order to map ATM cells to 2048 kbit / s, the 2048 kbit / s basic frame format according to ITU-T G.704 Recommendation shall be followed. In order to transmit an ATM cell through a 44.736 Mbit / s transmission device, it must comply with a physical layer convergence protocol (PLCP) for the ATM physical layer. The PLCP consists of 125 uS frames within a 44.736 Mbit / s standard payload. PLCP has no fixed mapping relationship between frames and 44.736 Mbit / s frames. That is, the PLCP may start at any position within the 44.736 Mbps flow path load. PLCP frames are defined in ITU-T G.804 as A1, A2 bytes for framing, Path Overhead Indicator (POI), Path Overhead (POH), and PLCP Payload. Consists of. Even at 44.736 Mbit / s, it has cell rate matching, HEC (Header Error Control) generation, cell boundary identification, cell header verification, and header extraction with error as recommended in ITU-T I.432. Allocating octets for operation management.

Accordingly, the present invention conforms to the ITU-T G.703, G.704, and G.804 standards of the International Telecommunication Union, and the ATM User Network Interface Specification prescribed by the ATM Forum. In order to comply with UTOPIA (Universal Test Operations Physical Layer Interface for ATM) physical interface, which is a matching standard between ATM layer and physical layer, it is possible to minimize additional additional circuits and By separating the low-speed ATM physical layer, the ATM physical layer processing device can be used to implement asynchronous transfer mode communication on a synchronous digital layer that can be easily utilized for any physical layer change by implementing the physical layer independently without changing the ATM layer. The purpose is to provide.

The present invention for achieving the above object provides a matching signal between the physical layer and the ATM layer of the upper layer, upper layer matching means for providing a data signal, an address signal, and a control signal for processor matching; FIFO control means for receiving transmission and reception related control signals of the upper layer matching means and outputs transmission and reception FIFO control signals; Transmitting side FIFO means for buffering the cell data of the upper layer matching means and outputting the buffered data by the control signal of the FIFO control means; Operation setting register means for performing a control register function for controlling a state of each functional unit through software in a microprocessor through the upper layer matching means; Board identification output means for outputting, to said upper layer matching means, a unique number of a specific board for initialization, status monitoring, configuration, etc. of a physical layer in an operation program; Transmission frame information insertion means for storing and inserting path overhead information inserted into a frame type defined in the ITU-T G.804 standard; Framer control means coupled to the upper layer matching means for providing a chip select signal for setting a register of a physical layer or for detecting an alarm signal and for monitoring performance and for providing a control signal for accessing a physical layer of a processor; State / alarm display means for receiving the framer control means and displaying the state of the physical layer; Receives the output of the transmitting side FIFO, calculates and sets the HEC (Header Error Control) field of the transmitting cell, and inserts the path overhead information of the transmitting frame information inserting unit to fit the transmission frame according to the PLCP frame format. Converts the signal into a bipolar (B3ZS) signal according to the speed of the transmission line and outputs it, receives the bipolar signal, converts it into an internal TTL signal, and breaks the received signal (Line Code Violation), Framing bit error, parity bit, alarm detection, Far End Receive Failure, etc. are detected and stored in the error counter for output, and frame reconstruction using PLCP frame type is recommended in ITU-T I.432. Physical layer framer means for detecting and outputting a cell using a header check sequence (HES); After the gain control and impedance matching for transmitting the output of the physical layer framer means through the transmission device, the signal is transmitted through an Alternate Mark Inversion (AMI) code, and a loss of signal for the signal received from the network. Line matching means for detecting a signal and converting the AMI coded signal into a bipolar (B3ZS) signal inversely and outputting the signal to the physical layer framer means; Local oscillating means for generating a clock required by a physical layer protocol processor in the physical layer itself and outputting the clock to the line matching means; Frame information extracting means defined in the ITU-T G.804 standard from the physical layer framer means; And a receiving side FIFO means for receiving and buffering the output of the physical layer framer means and outputting the buffer to the upper layer matching means under the control of the FIFO control means.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a configuration diagram of a system to which the present invention is applied, in which 101 is an ATM terminal device, 102 is a terminal correspondence unit, 103 is a system bus, 104 is a control unit (CPU), 105 is an ATM protocol processor, and 106 is The inventor's ATM physical layer processing unit 107 represents an exchange. Basically, in order to perform ATM cell-based communication, an exchanger using a switching system based on synchronous digital hierarchy (SDH) method should be used. However, this system is a step before transitioning to synchronous digital hierarchical method. The purpose is to communicate with ATM using a switching network using digital hierarchy. The devices required to construct a modular subscriber matching device for asynchronous delivery mode (ATM) communication on a pseudo-synchronous digital hierarchy (PDH) include conventional 1544 kbit / s (T1) or 2048 kbit / s as specified in FIG. The (E1) -based exchange 107 and the ATM terminal matching device 108 are composed of a control unit 104, a terminal correspondence unit 102, an ATM protocol processing unit 105, and an ATM physical layer processing unit 106, and mutually It consists of a system bus 103 for connection. The application of the present invention is a part that performs a physical matching function between the ATM protocol processing unit 105 and the exchange 107. The ATM protocol processing unit 105 corresponds to the ATM layer and the upper layer in the ATM layer model. The UTOPIA interface defined in the forum was applied to the present invention and redefined in the module structure.

2 is a block diagram of an ATM physical layer processing apparatus for matching with a pseudo-synchronous digital hierarchy according to an embodiment of the present invention.

In the figure, 201 is a transmission frame information insertion unit, 202 is a circuit matching unit, 203 is a physical layer framer, 204 is a transmitting side FIFO, 205 is a receiving side FIFO, 206 is a local oscillator, 207 is a framer control unit, 208 is a FIFO control unit, 209 Denotes a reception plane information extractor, 210 denotes a status / alarm display unit, 211 denotes an upper layer matching unit, 212 denotes an operation setting register, and 213 denotes a board ID output unit.

The physical layer framer 203 is a functional block that is responsible for inserting a frame for the physical layer convergence protocol (PLCP) format. The physical layer framer 203 provides a pre-insert function as a sender function, an alarm insertion function, a diagnostic function, and a FEAC (Far End). Alarm Channel) Code insertion function, path overhead insertion function, ATM cell interchange function, HCS (Header Check Sequence) generation and insertion function, idle cell insertion function, transmission cell counting function are provided and 4 cells can be buffered inside. It has a built-in FIFO. Receive side functions include alarm detection function, Line Code Violation (LCV) counting, framing error detection, parity error detection, far-end block error count, PLPP (Physical Layer Protocol Processor) based cell extraction, LOF (Loss of) Frame), BIP-8 (Bit Interleaved Parity) error detection function, cell descrambling, HCS error detection function, idle cell removal function, received idle cell count function, HCS error cell count function, 4 to buffer received cell Contains a cell FIFO.

The circuit matching unit 202 is an Alternate Mark Inbersion (AMI) signal (44.736 Mbit / s) or HDB3 (High Density Bipolar 3) signal (2048 kbit / s) used to transmit a physical signal on a pseudosynchronous digital hierarchy. Is a block that converts the signal into a Bipolar with 3 zeros substitution (B2ZS) signal used by a physical layer protocol processor. The line matching unit 202 has a function of satisfying the 75 ohm line characteristics specified in ITU-T G.703, and inserts a transformer so that the network side signal and the terminal side signal can be separated during line matching. Doing. In addition, it is possible to detect a signal for determining the presence or absence of a received signal, and includes a function to extract data and clock from the received signal.

The transmitting side FIFO 204 buffers a cell between the physical layer framer 203 and the higher layer matching unit 211. Since the write clock speed of the internal 4-cell FIFO on the transmitting side of the physical layer framer 203 is lower than the clock to be transmitted by the upper layer, the circuit is inserted to match the clock difference.

The receiving side FIFO 205 buffers a cell between the physical layer framer 203 and the higher layer matching unit 211. Since the read clock speed of the internal 4-cell FIFO of the physical layer framer 203 is lower than the clock to be received by the upper layer, the circuit is inserted to match the clock difference.

The transmission frame information inserting unit 201 is a functional block for inserting inserted path overhead information in a frame form defined in the ITU-T G.804 standard.

The reception plane information extraction unit 209 is a functional block for extracting and processing path overhead information inserted into a frame form defined in the ITU-T G.804 standard.

The framer controller 207 is a functional block that provides a chip select signal for setting a register of a physical layer or detects an alarm signal and monitors performance, and provides a control signal for accessing a physical layer of a processor.

The FIFO control unit 208 provides a function for controlling the transmitting side FIFO 204 and the receiving side FIFO 205, has a built-in clock division function, and transmits and receives signals related to transmission and reception on the UTOPIA interface between upper layer matching units 211. It consists of a circuit for matching.

The status / alarm display unit 210 is a circuit for displaying the state of the physical layer, and provides a Loss of Signal (LOS), a Loss of Frame Alignment (LOF), a TXD indicating a cell transmission state, and an RXD signal representing a cell reception. do.

Local oscillator 206 is a block within the physical layer itself that provides its own oscillation circuitry to provide the clock needed by the physical layer protocol processor.

The operation setting register 212 provides a function of setting and reading the states of the physical layer framer 203, the line matching unit 202, and the transmit / receive FIFOs 204 and 205 from a microprocessor to software, and provides an 8-bit flip-flop device. And data buffers. Signals that can be set include the case of the line matching unit 202, the selection of a valid transmission distance, a signal transmission prohibition, the initialization of the transmission / reception FIFOs 204 and 205, and the operation of driving LEDs for the visible status indication when a specific state occurs during operation The layer framer 203 is used for bits selecting 13 or 14 nibble insertions to create a Physical Layer Convergence Protocol (PLCP) frame.

The board ID output unit 213 outputs a unique number of a specific board for initialization, status monitoring, configuration, etc. of the physical layer in the operation program. need. That is, the ATM protocol processing unit 105 of FIG. 1 can process various physical layers such as STM-1 or DS1, DS3, E1, E3. On the other hand, the matching method with the ATM protocol processing unit 105 transmits and receives all data to and from the ATM cell, so the ATM layer or more can be processed by common software, and the physical layer can be configured and operated differently according to the board ID.

The upper layer matching unit 211 provides a signal between the physical layer and the ATM layer, which is a higher layer, has a data signal, an address signal, and a control signal for processor matching, and a signal for supplying power to the modular physical layer. And extension signals.

Referring to the operation of the present invention configured as described above, first, the transmission process from the ATM layer to the network side processes all signals between the ATM physical layer processor 106 and the ATM protocol processor 105 in the upper layer matching unit 211. The higher layer matching unit 211 stores the 53-byte cell received from the ATM layer in the transmitting side FIFO 204. The transmitting side FIFO 204 can buffer up to 256 cells of 9 bits, thus storing up to four cells. The transmitting side FIFO 204 has SOC (Start Of Cell) information in the first byte of 53 bytes, and if the internal transmission FIFO of the physical layer framer 203 is valid, the transmitting FIFO 204 controls the cell under the control of the physical layer framer (208). 203).

The physical layer framer 203 stores the four internal cells in the FIFO, calculates and sets the HEC (Header Error Control) field of the transmitting cell, and inserts path overhead information of the transmission frame information insertion unit 201. To map the PLCP frame format to the transport path according to the PLCP frame format. According to the internal operation of the physical layer framer 203, the PLCP frame is output to the line matching unit 202 as a bipolar (B2ZS) signal in accordance with the speed of the transmission path.

The circuit matching unit 202 passes through gain control and impedance matching for transmission through a transmission device, and then transmits the signal through an AMI (Alternate Mark Inbersion) code.

Next, referring to the transmission process from the network side to the ATM layer, the line matching unit 202 detects a loss of signal with respect to the received signal and reversely converts the AMI coded signal into a bipolar (B3ZS) signal. The conversion is output to the physical layer framer 203.

The physical layer framer 203 converts a bipolar signal into an internal TTL signal, detects a signal loss (Loin Code Violation) with respect to the received signal, and detects a signal loss state. It also detects framing bit errors, parity bits, alarm detection, and far end receive failures and stores them in the air counter.

The error counter value of the physical layer framer 203 is read by the processor for operation management. After restoring the frame using the PLCP frame of the receiving side of the physical layer framer 203, the cell is detected by using a header check sequence (HCS) recommended in ITU-T I.432, and then inside the physical layer framer 203. Is stored in the receiving FIFO and output to the receiving side FIFO 205.

The reception frame information extractor 209 extracts and processes path overhead information from the physical layer framer 203.

The receiving side FIFO 205 transmits the received cell under the control of the FIFO control unit 208 to the ATM protocol processing unit 105 through the upper layer matching unit 211.

3 illustrates a signal definition of the higher layer matching unit 211.

The upper layer matching unit 211 defines a UTOPIA interface standard for matching the microprocessor interface function and the ATM layer, and defines a signal for performance monitoring and control of the physical layer. This connector uses 96-pin 3-row male straight DIN connector.

TDAT [7: 0] A data line that sends outgoing data from the ATM layer to the physical layer. TDAT 7 is the most significant bit (MSB). Used when operating with the default 8-bit data width.

Tri-state Input signal.

TDAT [15: 8] is a data line that sends outgoing data from the ATM layer to the physical layer. TDAT 7 is the most significant bit (MSB). Used when operating with 16-bit data width for extension.

TXCLK is a transmission clock sent from the ATM layer to the physical layer.

The TSOC is a Transmit Start of Cell signal.

It is logical '1' in validity and '1' in the first byte of a 53-byte cell.

TXEN * is a signal indicating that there is valid data in TDAT [7: 0].

TXFUL * indicates that the transmit buffer is full in the physical layer. Logical '0' when valid. It must be asserted at least 4 cycles before the TDAT is unacceptable.

TCLAV indicates that the sending FIFO is empty.

TPRTY represents odd parity information for TDAT.

TXREF represents the operation clock signal of the ATM layer.

The LOSLED * signal represents a Loss of Signal alarm signal and is an open collector signal. Logical '0' when valid.

The LPOLED * signal indicates a Loss of Pointer alert signal and is an open collector signal. Logical '0' when valid.

The TXDLED * signal represents the transmit data status signal and is an open collector signal. Logical '0' when valid.

The RXDLED * signal represents the received data status signal and is an open collector signal. Logical '0' when valid.

The CONFAIL signal is a board hernia signal and is a logic '0' when valid.

The BVA [11: 1] signal is an 11-bit microprocessor address bus.

BVA [8: 1] uses an internal framer or line tie to the address bus, and BVA [11: 9] is used for address decoding for chip selection.

BAS * is an address strobe signal and is a logic '0' during operation.

BDS1 * is a data strobe signal and is a logic '0' during operation.

BDS0 * is a data strobe signal and is a logic '0' during operation.

BWR * Write signal; logic '0' during operation.

BDSEL * is a physical layer daughter board select signal and is a logic '0' during operation.

BD [0: 7] is a microprocessor 8-bit data bus signal.

DTACKP * is a physical layer common data response (DTACK) signal.

INT1 * is interrupt signal '1' and logic '0' during operation.

INT2 * is interrupt signal '2' and logic '0' in operation.

RESET * is a hardware or software reset signal.

RDAT [7: 0] is a bus used to transmit received data to the ATM layer with 8-bit data width. RDAT7 is MSB and Tri-state signal.

RDAT [15: 8] is a bus used to transmit received data to the ATM layer with 16-bit data width. Reserved for expansion.

RXCLK is a receive clock to synchronize with RDAT.

RSOC is the first octet signal of the receiving cell. Logical '1' when valid and logical '1' only in the first byte of the first byte cell of a 53 byte cell.

RXEN * indicates that the receive FIFO of the ATM layer is in a receivable state.

RXEMT * indicates that the receive FIFO of the physical layer is empty.

RCLAV indicates that there is a cell in the receive FIFO of the physical layer.

RPRTY is an odd parity bit for RDAT.

RXREF is an 8KHz clock signal divided by the physical layer.

RCLK is a 19.44 MHz clock signal divided by eight for the physical layer receive clock.

ALE is an address latch enable signal and is a signal line for an Intel processor.

VCC is a + 5V signal for DC power supply.

GND is the ground signal for DC power supply.

-5V is -5V signal for DC power supply.

ECL_GND is the ECL ground signal for DC power supply.

Effects of the present invention configured and operated as described above are as follows.

First, effectively construct a physical interface for B-ISDN suitable for asynchronous delivery mode communication using quasi-synchronous digital hierarchy according to ITU-TG.703, G.704 and G.804 standards of the International Telecommunication Union. can do.

Second, additional additional circuits are required because they conform to the ATM Forum User Network Interface specification defined by the ATM Forum and follow the UTOPIA physical interface, which is a matching standard between the ATM layer and the physical layer. It can be minimized.

Third, by separating the various medium- and low-speed ATM physical layer that is currently being standardized, it can be easily utilized for any physical layer change by implementing the physical layer independently without changing the ATM layer.

Fourth, the Motorola series can be applied not only to processors but also to internal processors, so it can be used not only for the shelf-type development system but also for designing ATM boards for PCs.

Claims (1)

A higher layer matching means (211) for providing a signal between the physical layer and the ATM layer, which is a higher layer, and providing a data signal, an address signal, and a control signal for processor matching; FIFO control means (208) for receiving transmission and reception related control signals of the upper layer matching means (211) and outputs transmission and reception FIFO control signals; Transmitting side FIFO means (204) for buffering the cell data of the upper layer matching means (211) and outputting it by the control signal of the FIFO control means (208); Operation setting register means (212) for controlling a register function for controlling a state of each functional unit through software in the microprocessor through the upper layer matching means (211); Board identification output means 213 for outputting a unique number of a specific board for initialization, status monitoring, configuration, etc. of the physical layer in the operation program to the upper layer matching means 211; Transmission frame information insertion means 201 for storing and inserting path overhead information inserted into a frame type defined in the ITU-T G.804 standard; Framer control means connected to the upper layer matching means 211 to provide a chip select signal for setting a register of the physical layer or to detect an alarm signal and to monitor the performance and to provide a control signal for the physical layer access of the processor ( 207); State / alarm display means (210) for receiving an output of the framer control means (207) to display a state of a physical layer; The output of the transmitting side FIFO 204 is input to calculate and set a HEC (Header Error Control) field of a transmitting cell, and inserts path overhead information of the transmitting frame information inserting unit 201 according to a PLCP frame format. Maps to PLCP frame format suitable for transmission path, converts to bipolar (B3ZS) signal according to transmission speed, outputs, receives bipolar signal, converts into internal TTL signal, and breaks the received signal (Line Code Violation, signal loss status, framing bit error, parity bit, alarm detection, Far End Receive Failure, etc. are detected and stored in the error counter, and the frame is restored using the PLCP frame type. Physical layer framer means 203 for detecting and outputting cells using a Header Check Sequence (HES) recommended in T I.432; After the gain control and impedance matching for transmitting the output of the physical layer framer means 203 through the transmission stop, the signal is transmitted through an Alternate Mark Inversion (AMI) code, and a signal loss state (Loss) is received for the signal received from the network. Line matching means (202) for detecting a signal, converting an AMI coded signal into a bipolar (B3ZS) signal and outputting the signal to the physical layer framer means (203); Local oscillating means (206) for generating a clock required by a physical layer protocol processor in the physical layer itself and outputting it to the line matching means (202); Received frame information extracting means (209) for extracting and processing path overhead information inserted into a frame form defined in the ITU-T G.804 standard from the physical layer framer means (203); And a receiving side FIFO means 205 which receives and buffers the output of the physical layer framer means 203 and outputs the buffer to the higher layer matching means 211 under the control of the FIFO control means 208. ATM physical layer processing apparatus for asynchronous transfer mode communication in a pseudo-synchronous digital hierarchy.