KR0153914B1 - Phase detector using reference clock - Google Patents

Abstract

The present invention relates to a phase change state detector of a phase aligner using a reference clock, comprising: read clock generation means for providing a read clock having the same phase so that the phases are output to the output system clock and the output reference clock; Write clock generation means for generating a data buffer enable clock using a system clock and a reference clock; Data buffer means for latching input data and outputting output data by an input system clock and an input reference clock from the write clock generation means; A phase for receiving a write clock address from the write clock generating means and a read clock address from the read clock generating means, and inputting an input system clock, a reference clock, an output system clock, and an output reference clock to output a phase state detection signal; Characterized in that it comprises a state sensing means.

Description

Phase Change Status Detector of Phase Aligner Using Reference Clock

1 is a block diagram of a bus.

2 is a block diagram of a phase aligner according to the present invention.

3 is a block diagram of the present invention.

4 is a timing diagram of FIG.

5 is a configuration diagram of a data buffer unit.

6 is a timing diagram of FIG.

7 is a block diagram of a read clock generator.

8 is a timing diagram of FIG.

9 is a schematic diagram of a phase state detector.

10 is a timing diagram of FIG.

* Explanation of symbols for main parts of the drawings

1: write clock generator 2: read clock generator

3: data buffer section 4: phase state detector

91: clock generator 92: phase state detector

According to the present invention, when the phase difference between the read clock and the write clock exceeds the buffer size for absorbing the phase difference of the phase aligner, the phase aligner using the reference clock for monitoring the state thereof is used. A change state detector.

The phase sorter using the reference clock has a difference between the write clock and the read clock depending on the buffer size of the phase sorter. Therefore, when the phase difference between the two clocks exceeds the size of the buffer, the clock and the write clock can monitor their status. This is to monitor when the phase difference between and is out of the limited range of the data buffer.

The phase aligner using the reference clock increases the amount of data transmitted / received between boards as a function of processing on the board increases when processing a large amount of transmit / receive data to be processed by a transmission device in a broadband transmission network. Therefore, the increase of board-to-board connection signal and high-speed signal transmission are indispensable for this process. However, as its high-speed signal connections increase, signals input to one board are transmitted from multiple boards, so on boards where these input signals are input, even though each input signal is synchronized with the system clock of the device (these signals When transferred in the form of a bus, a phase difference between signals input into a board occurs due to phase delays such as impedance mismatching and propagation delay between modules.

1 is composed of a system reference clock and system clock parallel data. The system reference clock is a clock that indicates the reference of parallel data. It is mainly 8KHz or 2KHz and corresponds to one period of the system clock. The system reference clock and parallel data are located in the poll of the system clock. Therefore, since the first position of the parallel data is indicated by the system reference clock, when multiple buses are inputted to one module in different phases, the positions of the parallel data are located at different positions. Therefore, a phase aligner using the reference clock is used to align the phase between these buses with the reference clock of the input module.

The phase difference between the input signals can be ignored when the pulse period of the signal is low in case of a low speed signal, but when the signal is 50 MHz or more, the pulse period becomes too small, and on the input board, the phase difference between these signals is out of this pulse period. It is difficult to simultaneously latch the first data on each bus with the reference clock. Therefore, the phase aligner absorbs the phase difference of each bus in the form of FIFO and aligns the phase of each bus with the same phase when the reference clock of the module inputting each bus is later than the reference clock of the input buses. do.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase change state detector of a phase aligner using a reference clock that absorbs the difference in propagation delay between various buses generated by electrical characteristics when high-speed signals are connected by performing phase alignment using a reference clock. There is.

In order to achieve the above object, the present invention includes a read clock generating means for providing a read clock of the same phase in order to output the phases of the output system clock and the output reference clock; Write clock generation means for generating a data buffer enable clock using a system clock and a reference clock; Data buffer means for latching input data by the input system clock and the input reference clock from the write clock generation means and outputting output data; A phase for receiving a write clock address from the write clock generating means and a read clock address from the read clock generating means, and inputting an input system clock, a reference clock, an output system clock, and an output reference clock to output a phase state detection signal; Characterized in that it comprises a state sensing means.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2 is a structural diagram of a phase aligner having a phase state detector according to the present invention, in which 1 is a write clock generator, 2 is a read clock generator, 3 is a data buffer unit, and 4 is a phase for detecting a phase state. Each state detector is shown.

In a phase aligner having a phase state detector for detecting the phase difference between the input system clock and the input reference clock and the output reference clock of the output system clock, the write clock generator 1 has the input data in parallel as shown in FIG. When input to the data buffer unit, a write clock address for latching parallel data in the data buffer unit 3 is generated using the input reference clock and the input system clock which are system reference clocks.

As shown in FIG. 3, it consists of an N-division counter 31, the x: N demux 32, the retiming part 33, and the write phase synchronizer 34. As shown in FIG.

The N division counter 31 is a count circuit in which N count signals are generated according to the number of stages of the data buffer unit 3, which is shown as an output signal of the eight division counter shown in FIG.

The x: N demux unit 32 outputs the output signal of the N division counter 31 by one clock size of an input system clock capable of enabling each stage of the data buffer unit through a decoding circuit, Its timing diagram is the same as b in FIG. Since the retiming unit may have a cleat in the signal waveform output from the decoding circuit, the retiming unit performs a function of retiming to remove the signal waveform in synchronization with one clock of the input system clock as shown in FIG.

In the write phase synchronizer 34, when the input reference clock and the input clock are always input in the same phase, the initial reference point of the N division counter 31, that is, the point where the counter becomes zero, is located at the input reference clock. In order to be generated, the input reference clock is operated as a counter reset signal. The phase timing of FIG. 3 is shown in FIG.

The data buffer unit 3 is configured of a D flip-flop in a scan form by using a buffer enable signal generated by the write clock generator 1 and a clock corresponding thereto. The D flip-flop is composed of N D flip-flops according to one bit of data in accordance with N divisions. The number of N D flip-flops is the number of stages in the data buffer, which must be configured to suit the system.

The number of data buffers varies depending on how many bits the number of data bits of the input bus is. This configuration is the same as FIG.

6 is a timing diagram of an output data signal in which the input data bus is written to the data buffer section 3 by the write clock signal and then aligned with the read reference clock by the read clock. In this timing diagram, a timing diagram of a signal to which input parallel data is output centering on the 12-stage data buffer section 3 is shown. The input parallel data is latched by the buffer enable signal to a scan flipped D flip-flop into the input system clock and the input reference clock. When input data A is written at timing a in FIG. 6, the output signal of the D flip-flop # 1 of the data buffer section becomes a-1, and data is latched sequentially in the twelve data buffer sections 3. In b, the first data of the next 12th data is latched. This latched data is demuxed by the read clock address generated by the read clock to form one output data signal. Its setting point is shown in c. Therefore, the signals input in parallel are waited in the data buffer section by the output reference clock for the input reference clock. Therefore, the phases are aligned and output to the output reference clock for the input signals of various phases.

The read clock generation unit 2 muxes the data latched in the data buffer unit by using the output system clock and the output reference clock of the corresponding board, and outputs the phase aligned with the read system clock and the reference clock. do. In this part, the structure is similar to that of the write clock generator. In order to output the data of each input bus in the same phase, the signal output from the data buffer configured for each input bus is read as the same read clock (MUX: encoding). do.

The read clock re-times the N division counter 71 and the division clock (a signal in FIG. 8) generated therefrom to the output system clock to align the signal having a slight phase difference. This signal is the same as the read clocks # 1 to 3 in FIG. In addition, the reference clock is input to the reset terminal of the N division counter 71 so as to always generate a read clock in the same phase as the reference clock. Therefore, the configuration thereof is shown in FIG. 7, and the timing relationship thereof is shown in FIG. 8.

The write clock generator 1 and the read clock generator 2 generate a write address signal and a read address signal of the data buffer unit 3, which generates an N division counter 71 suitable for the number of buffers of the data buffer unit. The generated signal is generated through a decoding circuit to generate a buffer enable clock of the data buffer section. The data buffer section 3 uses this signal to latch the input data onto the D flip-flop. The latched data uses the read clock address signal generated by the read clock generator 2 to cause a malfunction of the data buffer unit 3 due to a phase change or a phase change of the read clock in the output system clock and the output reference clock. To this end, the phase state detector 4 uses the output reference clock to determine the position of the input reference clock and display its status.

In Fig. 9, the configuration of the phase state detector is shown. Its configuration consists of a clock generator 91 and a phase state detector 92.

The clock generator 91 generates a clock that can represent the stable regions 1 and 2 having 4/7 clock cycles prior to the output reference clock as shown in FIG. The signal of / 2 is implemented by its circuit using a counter and shift register.

Therefore, in the phase state detector, if the input reference clock is located in the stable region 1/2, the logic to indicate the H state is configured, and if other input signals exist, the logic to display the L state is configured (DF / F). do. When the input reference clock is present in the stable region, this circuit operates the output signal obtained by ANDing the stable region signal and the input reference clock as a set of D flip-flops so that its output becomes H. The latch reference clock latches the input reference clock so that the L signal becomes a phase detection signal. This phase state detection signal operates every reference clock period so that it can be counted and recognized by the processor. This signal can also be used to generate an interrupt.

The output reference clock and the output system clock are used to generate a stable region and a latch clock suitable for a data buffer section having a buffer size of 12 stages. The clock generator 91 of the phase state detector may use the output reference clock to shift the output system clock to an output system clock to easily design a stable region clock and a latch clock using a known technique. The clocks generated as described above output two states under the control of a processor. Its phase relationship is shown in FIG.

In FIG. 10, when the mode selection signal is 0, the phase of the signal input to the phase aligner is in the stable region 1, and thus, the phase difference has a stable phase difference. In the latch clock 1, the latch clock corresponding to w1 to w8 has an input reference clock. When latched, it is indicated as a phase state detection signal by latching using a discrimination signal to indicate that it is in an unstable region. When the mode select signal is 1, the buffer size of the data buffer is 12, and it is sufficiently used. Even if the input clock is located in a larger range than the stable region 1, it can be sufficiently absorbed by the data buffer. Its operation is the same as with mode selection 0.

A feature of the present invention is firstly a function for detecting a condition outside of its stable phase range in a circuit for aligning phases of buses input in different phases to a reference clock of one system clock. Second, it has phase range control within the data buffer size of the phase aligner. Third, each bus has a function for detecting a condition out of a stable phase range.

In addition, the circuit of the present invention is similar to the circuit for detecting the FIFO underrun / overrun, which is often used in the FIFO, but due to the propagation delay generated when interfacing high speed signals with multiple modules, Phase propagation due to the size of the data buffer in the phase aligner absorbing these phase alignments because the phase delay between the signals input from one module to the other module is different because the propagation delay is more than one cycle of the high speed signal transmission speed. Is a circuit for detecting a condition out of a limited range of phase difference according to the size of the data buffer and performs a function of initializing the buffer by using the detected state.

The phase state detector operated as above processes a large amount of signals in one board and is useful for detecting the phase state of the phase aligner using the reference clock used when the signals connected between these boards operate at high speed. By using the phase state detection signal to display on the microprocessor, it is possible to inform the operator operating such equipment to inform the abnormal state of the phase generated when the board-to-board connection.

Claims (5)

Read clock generation means (2) for providing read clocks of the same phase so that the phases are outputted in alignment with the output system clock and the output reference clock; Write clock generating means (1) for generating a data buffer enable clock using a system clock and a reference clock; Data buffer means (3) for latching input data by the input system clock and input reference clock from the write clock generation means (1) and outputting output data; The write clock address from the write clock generation means 1 and the read clock address from the read clock generation means 2 are input, and the input system clock and reference clock, the output system clock and the output reference clock are input as phase states. Phase change state detector of a phase aligner using a reference clock, characterized in that it comprises a phase state detection means (4) for outputting a detection signal. 2. The write clock generating means (1) according to claim 1, further comprising: an N division counter (31) for inputting an input system clock to generate N count signals; A demultiplexer (DMUX) 32 for demultiplexing the clocks generated by the N division of the N division counter 31 to generate a clock enable signal of the data buffer means 3; A retiming unit (33) for receiving a clock enable signal from the demultiplexer (32) to remove an error of the output signal waveform and to output a buffer enable signal; When the input reference clock and the input clock are always input in the same phase, the input reference clock is set so that the initial position of the N division counter 31 (the point at which the counter becomes zero) occurs at the position where the input reference clock is located. And a write phase synchronizer (34) for inputting the counter reset signal and outputting the counter to the N division counter (31). The data buffer means (3) according to claim 1, wherein the data buffer means (3) uses a buffer enable signal generated by the write clock generation means (1) and a clock corresponding thereto, and is configured in a scan form, and has one data bit in accordance with N division. N D flip-flops 51 to 5N, each of which is configured to be N; A multiplexer which receives a signal latched by the scan enable buffer enable signals from the N D flip-flops 51 to 5N and a read clock and a system clock from the read clock generation means 2, and multiplexes and outputs the read clock and the system clock; 52. A phase change state detector of a phase aligner using a reference clock, comprising: a reference clock; 2. The apparatus of claim 1, wherein the read clock generation means (2) comprises: an N division counter (71) for inputting N outputs and outputting an N system clock; A retiming unit 72 for receiving an N-divided signal from the N-dividing counter 71 to retime to align a signal having a phase difference; And a read phase synchronizer 73 for inputting a reference clock to the reset terminal of the N division counter 71 so as to receive the output system clock and the output reference clock and always generate a read clock in the same phase. Phase change state detector on a phase aligner using a reference clock. The clock generator (91) according to claim 1, wherein said phase state detecting means (4) generates a clock capable of representing a stable region clock in advance of an output reference clock using a mode selection signal as an input and using an output reference clock. ; And a phase state detector (92) for receiving a stable region clock from the clock generator (91), an input reference clock and a discrimination signal, and outputting a phase state detection signal. Phase change state sensor.