KR0153680B1 - A circuit for generating metering pulses - Google Patents
A circuit for generating metering pulsesInfo
- Publication number
- KR0153680B1 KR0153680B1 KR1019950027114A KR19950027114A KR0153680B1 KR 0153680 B1 KR0153680 B1 KR 0153680B1 KR 1019950027114 A KR1019950027114 A KR 1019950027114A KR 19950027114 A KR19950027114 A KR 19950027114A KR 0153680 B1 KR0153680 B1 KR 0153680B1
- Authority
- KR
- South Korea
- Prior art keywords
- clock
- output
- metering pulse
- resistance value
- waveform generator
- Prior art date
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M15/00—Arrangements for metering, time-control or time indication ; Metering, charging or billing arrangements for voice wireline or wireless communications, e.g. VoIP
- H04M15/82—Criteria or parameters used for performing billing operations
- H04M15/8264—Pulse based
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/22—Arrangements for supervision, monitoring or testing
- H04M3/24—Arrangements for supervision, monitoring or testing with provision for checking the normal operation
- H04M3/248—Arrangements for supervision, monitoring or testing with provision for checking the normal operation for metering arrangements or prepayment telephone systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q1/00—Details of selecting apparatus or arrangements
- H04Q1/18—Electrical details
- H04Q1/30—Signalling arrangements; Manipulation of signalling currents
- H04Q1/32—Signalling arrangements; Manipulation of signalling currents using trains of dc pulses
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M2215/00—Metering arrangements; Time controlling arrangements; Time indicating arrangements
- H04M2215/78—Metric aspects
- H04M2215/7866—Pulse based
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/1313—Metering, billing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13214—Clock signals
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Meter Arrangements (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
Abstract
본 발명에 따른 메터링 펄스 발생회로는 클럭선택신호에 따라 소정의 저항값을 선택하는 클럭선택부(21); 상기 클럭선택부(21)의 출력을 입력받아 상기 클럭선택부(21)에서 선택된 듀티비 및 주파수의 파형을 발생하는 예측파형 발생부(22); 및 상기 예측파형 발생부(22)의 출력을 증폭하는 출력증폭기(23)로 구성되어 클럭선택신호에 따라 시스템이 요구하는 TeleTAX방식의 메터링 펄스를 발생시켜 공급할 수 있으므로 시스템규격에 대한 적응성이 향상되고, 회로구성이 간단하여 저렴하게 구현할 수 있다.The metering pulse generation circuit according to the present invention includes a clock selector 21 for selecting a predetermined resistance value according to a clock selection signal; A prediction waveform generator 22 receiving the output of the clock selector 21 and generating a waveform having a duty ratio and a frequency selected by the clock selector 21; And an output amplifier 23 for amplifying the output of the predictive waveform generator 22 to generate and supply a teleTAX-type metering pulse required by the system according to a clock selection signal, thereby improving adaptability to system standards. In addition, the circuit configuration is simple and can be implemented inexpensively.
Description
제1도는 종래의 메터링 펄스 발생회로를 도시한 블럭도.1 is a block diagram showing a conventional metering pulse generation circuit.
제2도는 본 발명에 따른 메터링 펄스 발생회로를 도시한 블럭도.2 is a block diagram showing a metering pulse generating circuit according to the present invention.
제3도는 본 발명에 따른 일실시예이다.3 is one embodiment according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 클럭발생부 12 : 분주회로11: clock generator 12: frequency divider circuit
13 : 대역통과필터 14 : 출력증폭부13 band pass filter 14 output amplifier
15,24 : SLIC 21 : 클럭선택부15,24: SLIC 21: Clock selector
22 : 예측파형 발생부 23 : 출력증폭회로22: prediction waveform generator 23: output amplifier circuit
본 발명은 위성통신 지상시스템(DAMA-SCPC)과 같은 공중통신장치에서 과금을 위해 사용되는 메터링 펄스를 발생하는 회로에 관한 것이다.The present invention relates to a circuit for generating a metering pulse used for charging in a public telecommunication device such as a satellite communications terrestrial system (DAMA-SCPC).
위성통신 지상시스템은 위성체를 이용하여 음성전화와 저속의 데이타 서비스를 제공하기 위한 통신장치로, 중심국과 다수의 중계국이 분산되어 통신하도록 되어 있다. 이러한 위성통신 지상시스템에 있어서 일반 가입자를 대상으로 서비스를 이용하는 시간에 따라 과금을 하기 위해서는 과금선호 즉, 메터링 펄스가 필요하다.Satellite communication terrestrial system is a communication device for providing voice telephony and low-speed data services using satellites. A central station and a plurality of relay stations are distributed to communicate with each other. In such a satellite communication terrestrial system, billing preference, that is, metering pulse, is required to charge according to the time of using the service for general subscribers.
일반적으로, 메터링 펄스 방식은 역 베터리(reverse battery)방식과 텔리택스(TeleTAX)방식이 있는데, 통상의 교환기에서는 역 베터리 방식이 널리 사용되고 있다.In general, the metering pulse method includes a reverse battery method and a TeleTAX method, and a reverse battery method is widely used in a general exchanger.
텔리택스(TeleTAX)방식에 따른 종래의 메터링펄스 발생회로는 제1도에 도시된 바와 같이 클럭발생부(11); 상기 클럭발생부(11)에서 발생된 클럭을 분주하는 분주회로(12); 상기 분주회로(12)의 출력에서 소정 주파수대만 통과시켜 잡음을 제거하는 대역통과필터(BPF:13); 상기 대역통과된 신호를 증폭하여 메터링 펄스(TTXIN)를 출력하는 출력증폭부(14)로 구성되어 가입자선로 접속회로(SLIC: SUbscriber Line Interface Circuit)에 메터링 펄스를 제공한다.The conventional metering pulse generation circuit according to the TeleTAX method includes a clock generator 11 as shown in FIG. A divider circuit 12 for dividing a clock generated by the clock generator 11; A band pass filter (BPF) 13 for removing noise by passing only a predetermined frequency band at the output of the frequency divider circuit 12; It is composed of an output amplifier 14 for amplifying the band-passed signal to output a metering pulse (TTXIN) to provide a metering pulse to a subscriber line connection circuit (SLIC).
이러한 종래의 메터링 펄스회로는 그 구성이 복잡하여 제작비용이 증가하고, 신뢰도가 낮은 문제점이 있다.This conventional metering pulse circuit has a problem in that its construction is complicated, so that the manufacturing cost increases and the reliability is low.
이에 본 발명은 텔리택스(TeleTAX)방식으로 메터링 펄스를 발생하기 위한 메터링 펄스 발생회로를 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a metering pulse generation circuit for generating a metering pulse in a teletax (TeleTAX) method.
상기와 같은 목적을 달성하기 위하여 본 발명의 회로는 클럭선택신호에 따라 소정의 저항값을 선택하는 클럭선택부; 상기 클럭선택부의 출력을 입력받아 소정 듀티 및 주파수의 파형을 발생하는 예측파형 발생부; 상기 예측파형 발생부의 출력을 증폭하는 출력증폭기로 구성되는 것을 특징으로 한다.In order to achieve the above object, the circuit of the present invention includes a clock selector for selecting a predetermined resistance value according to a clock select signal; A prediction waveform generator which receives the output of the clock selector and generates a waveform having a predetermined duty and frequency; And an output amplifier for amplifying the output of the predictive waveform generator.
즉, 본 발명은 클럭선택신호에 따라 예측파형 발생부에 연결되는 듀티저항값과 주파수저항값을 선택하여 예측파형 발생부에서 발생되는 메터링신호의 주파수와 듀티비를 조절하고, 예측파형 발생부에서 발생된 신호를 증폭하여 출력하도록 된 것이다.That is, the present invention adjusts the frequency and duty ratio of the metering signal generated by the prediction waveform generator by selecting the duty resistance value and the frequency resistance value connected to the prediction waveform generator according to the clock selection signal, and the prediction waveform generator It is to amplify and output the signal generated by.
이하, 첨부된 도면을 참조하여 본 발명을 자세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
본 발명에 따른 메터링 펄스 발생회로는 제2도에 도시된 바와 같이, 클럭선택신호에 따라 소정의 저항값을 선택하는 클럭선택부(21); 상기 클럭선택부(21)의 출력을 입력받아 상기 클럭선택부(21)에서 선택된 듀티비 및 주파수의 파형을 발생하는 예측파형 발생부(22); 상기 예측파형 발생부(22)의 출력을 증폭하는 출력증폭기(23)로 구성되어 있다.The metering pulse generation circuit according to the present invention includes a clock selector 21 for selecting a predetermined resistance value according to a clock selection signal, as shown in FIG. A prediction waveform generator 22 receiving the output of the clock selector 21 and generating a waveform having a duty ratio and a frequency selected by the clock selector 21; An output amplifier 23 that amplifies the output of the predictive waveform generator 22 is configured.
또한 본 발명의 실시예는 제3도에 도시된 바와 같이, 클럭선택부(21)가 클럭선택(SEL)신호에 따라 연결 혹은 차단되는 복수개의 스위칭소자(U2~U5)로 구현되고, 예측파형 발생부(22)가 상기 클럭선택부(21)의 저항값에 의해 파형을 발생하는 집적회로소자(예컨데, ICL8038: U7)로 구현되며, 상기 출력증폭회로(23)는 연산증폭기(예컨데, OP470GS: U8)로 구현된다.In addition, the embodiment of the present invention, as shown in Figure 3, the clock selector 21 is implemented by a plurality of switching elements (U2 ~ U5) connected or disconnected in accordance with the clock selection (SEL) signal, the prediction waveform The generator 22 is implemented as an integrated circuit device (eg, ICL8038: U7) that generates a waveform by the resistance value of the clock selector 21, and the output amplifier circuit 23 is an operational amplifier (eg, OP470GS). Is implemented as U8).
이어서, 상기와 같이 구성되는 본 발명의 실시예가 동작하는 것을 설명한다.Next, an embodiment of the present invention configured as described above operates.
먼저, TeleTAX방식의 과금에 사용되는 메터링 펄스는 비평형 12KHz 혹은 16KHz가 규격으로 정해져 있으므로, 시스템의 요구에 따라 클럭선택신호(SEL)로 어느 하나의 주파수를 선택한다. 예컨데, 클럭선택신호(SEL)가 로직 1이면 12KHz의 TeleTAX신호가 선택되고, 클럭선택신호(SEL)가 로직 0이면 16KHz의 TeleTAX가 선택된다.First, the metering pulse used for TeleTAX charging is set to non-equilibrium 12KHz or 16KHz as the standard. Therefore, one frequency is selected by the clock selection signal SEL according to the system requirements. For example, if the clock select signal SEL is logic 1, a 12 KHz TeleTAX signal is selected. If the clock select signal SEL is logic 0, a 16 KHz TeleTAX is selected.
즉, 클럭선택신호(SEL)가 로직 1이 되면 클럭선택부(21)의 스위칭소자(U4, U5)가 온되고, 스위칭소자(U2, U3)가 오프되어 듀티 사이클을 결정하기 위한 저항값은 R3과 R5의 합이 되고, 주파수를 결정하기 위한 저항값은 R4와 R6의 합이 된다.That is, when the clock select signal SEL becomes logic 1, the switching elements U4 and U5 of the clock selector 21 are turned on and the switching elements U2 and U3 are turned off to determine the resistance value for determining the duty cycle. It is the sum of R3 and R5, and the resistance value for determining the frequency is the sum of R4 and R6.
반대로, 클럭선택신호(SEL)가 로직 0이 되면 클럭선택부(21)의 스위칭소자(U4, U5)가 오프되고, 스위칭소자(U2, U3)가 온되어 듀티 사이클을 결정하기 위한 저항값은 R1과 R5의 합이 되고, 주파수를 결정하기 위한 저항값은 R2와 R6의 합이 된다.On the contrary, when the clock selection signal SEL becomes logic 0, the switching elements U4 and U5 of the clock selection unit 21 are turned off, and the switching values U2 and U3 are turned on to determine the resistance value for determining the duty cycle. It is the sum of R1 and R5, and the resistance value for determining the frequency is the sum of R2 and R6.
예컨데, R1=330, R2=330, R3=2.2K, R4=2.2K, R5=5,62K, R6=5,62K라하면, 클럭선택신호(SEL)가 로직 1일 경우에 듀티저항값과 주파수저항값은 각각 2.2K + 5.62K = 7.82K가 되고 로직 0일 경우에 듀티저항값과 주파수저항값은 각각 330 +5.62K = 5.95K가 된다.For example, if R1 = 330, R2 = 330, R3 = 2.2K, R4 = 2.2K, R5 = 5,62K, R6 = 5,62K, the duty resistor value and The frequency resistance value is 2.2K + 5.62K = 7.82K, respectively, and at logic 0, the duty resistance value and the frequency resistance value are 330 + 5.62K = 5.95K, respectively.
예측파형 발생부(22)는 클럭선택부(21)에서 선택된 듀티저항값과 주파수저항값에 따라 12KHz나 16KHz중 하나의 정현파신호를 발생시켜 SNWOUT단자를 통해 출력한다. 이때 발생되는 주파수는 SWSDJ단자에 연결되는 저항(R7)과 TMGCAP에 연결되는 커패시터(C1)에 의해 정해진다.The predictive waveform generator 22 generates a sinusoidal signal of 12 KHz or 16 KHz according to the duty resistance value and the frequency resistance value selected by the clock selector 21 and outputs it through the SNWOUT terminal. The frequency generated at this time is determined by the resistor R7 connected to the SWSDJ terminal and the capacitor C1 connected to the TMGCAP.
예컨데, R7 = 82.5K이고, C1 = 3.3 nF이라면 예측파형 발생부(22)에서 발생되는 주파수는 다음 식1과 같다.For example, if R7 = 82.5K and C1 = 3.3 nF, the frequency generated by the predictive waveform generator 22 is expressed by Equation 1 below.
상기 식1에 따라 클럭선택신호(SEL)가 로직 1일 경우 발생되는 주파수는 f = 0.33 ÷ (7.82K × 3.3nF) ≒ 12 KHz이고, 클럭선택신호(SEL)가 로직 0일 경우 발생되는 주파수는 f = 0.33 ÷ (5.95K × 3.3nF) ≒ 16.807 KHz이다. 그리고 발생되는 파형의 듀티비는 DTYCLE단자에 연결되는 저항값과 FREQADJ에 연결되는 저항값이 같으므로 50%가 된다.According to Equation 1, the frequency generated when the clock selection signal SEL is logic 1 is f = 0.33 ÷ (7.82K × 3.3nF) ≒ 12 KHz, and the frequency generated when the clock selection signal SEL is logic 0. Is f = 0.33 ÷ (5.95 K × 3.3 nF) ≒ 16.807 KHz. The duty ratio of the generated waveform is 50% because the resistance value connected to the DTYCLE terminal and the resistance value connected to the FREQADJ are the same.
이와 같이 예측파형 발생부(22)에서 발생되는 파형은 +/-15V범위의 사인파로서, 출력증폭회로(23)에서배만큼 증폭되어 가입자측(SLIC: 24)으로 출력된다. 예컨데, R8 = 68K, R9 = 12K라 하면 예측파형 발생부의 출력은 출력증폭기(23)에서 약 0.176배로 반전 증폭된다.As such, the waveform generated by the predictive waveform generator 22 is a sine wave in the range of +/- 15V, and is output from the output amplifier circuit 23. It is amplified by twice and output to the subscriber side (SLIC) 24. For example, if R8 = 68K and R9 = 12K, the output of the predictive waveform generator is inverted and amplified by about 0.176 times in the output amplifier 23.
즉, 가입자보드(SLIC)로 출력되는 메터링 펄스(TTXIN)는 약 +/-2V정도의 12KHz 혹은 16KHz신호이므로, 출력증폭기(23)에서 적절하게 증폭도를 조절하여 규격에 맞춘다.That is, since the metering pulse TTXIN output to the subscriber board (SLIC) is a 12KHz or 16KHz signal of about +/- 2V, the amplification degree is appropriately adjusted in the output amplifier 23 to meet the standard.
이상에서 살펴본 바와 같이 본 발명에 따른 메터링 펄스발생회로는 클럭선택신호에 따라 시스템이 요구하는 TeleTAX방식의 메터링 펄스를 발생시켜 공급할 수 있으므로 시스템규격에 대한 적응성이 향상되고, 회로구성이 간단하여 저렴하게 구현할 수 있는 효과가 있다.As described above, the metering pulse generating circuit according to the present invention can generate and supply a teleTAX type metering pulse required by the system according to the clock selection signal, so that the adaptability to the system standard is improved, and the circuit configuration is simple. Inexpensive to implement.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950027114A KR0153680B1 (en) | 1995-08-29 | 1995-08-29 | A circuit for generating metering pulses |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950027114A KR0153680B1 (en) | 1995-08-29 | 1995-08-29 | A circuit for generating metering pulses |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970013695A KR970013695A (en) | 1997-03-29 |
| KR0153680B1 true KR0153680B1 (en) | 1998-11-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019950027114A KR0153680B1 (en) | 1995-08-29 | 1995-08-29 | A circuit for generating metering pulses |
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| KR (1) | KR0153680B1 (en) |
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1995
- 1995-08-29 KR KR1019950027114A patent/KR0153680B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR970013695A (en) | 1997-03-29 |
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