KR0153373B1 - Data recovering circuit adaptive to communication environment - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a majority voting logic data recovery circuit in a wireless communication system.

2. The technical problem to be solved by the invention

It is a technique for solving the degradation of reliability caused by data restoration without considering the communication environment.

3. Summary of Solution to Invention

The frame quality is measured from the received signal and reflected in the majority decision, thereby restoring data differentially according to the state of the signal.

4. Important uses of the invention

It is used for data recovery at the receiver of a wireless communication system.

Description

Data restoration circuit adaptive to communication environment

1 is a block diagram of a conventional data recovery circuit.

2 is a block diagram of a data recovery circuit according to the present invention.

3 is a detailed view of a flame quality measuring instrument in FIG. 2.

4A to 4H are input / output timing diagrams of the data recovery circuit.

5 is an input / output timing diagram of a flame quality measuring instrument.

The present invention relates to a majority voting logic data recovery circuit in a wireless communication system, and more particularly, to a data recovery circuit using a measurement of frame quality.

In a typical data communication apparatus, various methods are used to detect or recover data errors occurring in a transmission section. A majority decision is one of them. This majority decision is performed to correct the data error by repeatedly transmitting the information to be sent an odd number of times and taking the state (1 or 2) of bits occupied by a large number of information at the receiving end even if this signal causes an error in the transmission section. Used as a way.

However, when transmitting data from a wireless communication device, a bit error or burst error may occur due to fading or interference of adjacent channels, and in this case, a received signal level Or bitstream stability is a very important factor in determining data errors.

1 is a configuration diagram of a conventional data restoration circuit. In the case of adopting the majority vote method of selecting two of the three, each frame separated by the frame detector 105 of the receiver is stored in three memory banks 106 to 108, respectively, and the three logical products logic 111 to 113 and one. The logic sum logic 114 of S is used to output data having a plurality of values from the memory banks 106 to 108. This is well known by the following equation:

F = AB + AC + BC ........... (1)

However, in this method, since the communication environment is not taken into consideration, the data A, B, and C of each frame input to the decision logic 109 may be the desired data or the unwanted data, that is, the data having an error. The decision logic 109 can only be driven. As a result, when the condition of the signal input to the receiver is bad, there is a disadvantage in that the reliability of the restored data is lowered.

Accordingly, an object of the present invention is to provide a highly reliable data recovery circuit in consideration of a communication environment in a receiver of a wireless communication system.

The present invention for achieving the above object is characterized by restoring data differentially according to the state of the signal by measuring the frame quality from the received signal and reflecting it in the majority decision.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In addition, in the following description, many specific details such as components of specific circuits are shown, which are provided to help a more general understanding of the present invention, and the present invention may be practiced without these specific details. It will be obvious to those skilled in the art.

In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

2 illustrates an embodiment of a data recovery circuit according to the present invention, and includes a demodulator 202 for demodulating and outputting a received signal from a radio signal transmitted from other equipment, and restoring a clock signal from the demodulated signal. A clock restorer 203 for outputting a recovered clock and a clock shifted 1/2 of the restored clock, a data restorer 204 for restoring data from an output signal of the demodulator 202, and the clock restorer; A frame detector 205 for receiving a clock from the device 203 and detecting and outputting the start of a frame from the output of the data decompressor 204, and receiving a clock from the output of the clock decompressor 203 and receiving the clock. A plurality of memories that receive the beginning of the frame from the output of the detector 205 and sequentially store the data recovered from the output of the data decompressor 204 according to each frame Receive clocks from the clock restorer 203, receive frame information from the output of the frame detector 205, and receive data recovered from the output of the data restorer 204. A frame quality measurer 211 that measures and outputs the quality of each frame, and a frame quality measurer that measures the quality of each frame and the restored data corresponding to each frame stored in the plurality of memory banks 206 to 208. And a decision unit 109 for performing logical operation on the output signal of 211 to determine final data.

The determination unit 109 temporarily stores and outputs an output signal of the frame quality measuring unit 211 in response to an output signal of the frame detector 205 and the memory bank 206. And arithmetic units 215 to 217, 218 for logically calculating all the first data stored in the subfield 208 and the corresponding frame quality signal.

The holding units 212 to 214 may include a plurality of latches 212 to 214 that temporarily store quality information of a corresponding frame in response to the frame quality detection signal whenever each frame data is stored in the corresponding memory bank. Can be.

The calculation units 215 to 217 and 218 multiply the recovered data of each frame output from the plurality of memory banks 206 to 208 by the quality measurement signal of each frame output from the holding units 212 to 214. A plurality of multipliers 215 to 217 to output and the outputs of the multipliers 215 to 217 are summed to reflect the quality of a frame of data transmitted a plurality of times to finally determine the received data. It may be configured as a summer 218 to determine the final data.

FIG. 3 is a detailed circuit diagram of the frame quality meter of FIG. 2, in which a signal shifted by three quarters of the recovered clock received from the data recoverer 204 and provided by the clock recoverer 203 is illustrated in FIG. A zero crossing detector 510 for receiving a zero crossing reset signal 505 from an output of the frame detector 205 and setting a predetermined period (window) in which data is polled or rised. And a counter 520 that receives a clock signal from 203, receives a counter enable signal 501 from the frame detector 205, and counts and outputs a good signal output from the zero crossing detector 510. do.

The zero crossing detector 510 logically operates an edge detector 530 that detects whether a falling edge or a rising edge exists within or outside a window section, and an output of the edge detector 530 to output a good signal. Circuit 515.

The edge detector 530 includes flip-flops 511 to 514 to input the window clock 503 as an enable signal, input the output signal 504 of the data restorer 204 as a clock, and input the frame detector ( The output signal of 205 is inputted as a reset signal of flip-flops 511 to 514 to detect whether an edge occurs within a window section of a predetermined section.

Referring back to FIG. 2, the frame query measurer 211 having the above-described configuration is operated by the counter enable signal 501-for one frame period-detected from the frame detector 205. FIG. The zero crossing detector 510 uses the edge detector 530 to have a rising or falling edge at the data restorer output 504 during a high or low period of the window clock 503 output from the clock restorer 203. It is detected whether it is generated and whether data is normally detected during one clock period. The conditions for determining whether the data is normal are as follows.

First, it is good if there is one edge (rising or polling) in the window and no edge occurs outside the window.

Second, it is good if no edge is generated inside or outside the window.

Third, if an edge occurs outside the window, it is bad.

Fourth, if an edge occurs more than once in the window, it is bad.

The detected signal is measured only during one clock period by the zero crossing reset signal 505, and the counter 520 counts the good signal of the zero crossing output 506 during the counter enable 501 period. The frame quality for one frame period is output.

4A to 4H are input / output timing diagrams of the data restoration circuit, FIG. 4A is a waveform of the restored data 301 to 304, FIG. 4B is a waveform of the detected frame synchronization signal, and FIGS. 4C to 4E are the first 4F to 4H are waveforms of the first to third frame quality measurement signals 305 to 307, and FIG. 4I shows the finally determined data (the waveforms of the third frame memory bank enable signals 302 to 304). 308).

5 is an input / output timing diagram of a flame quality measuring instrument. FIG. 5a is a waveform of a counter enable signal 501, FIG. 5b is a waveform of an output signal of the clock restorer 203, and FIG. 5c is a waveform of a window clock. 5d is a waveform of a reception data, FIG. 5e is a waveform of a zero crossing reset signal, FIG. 5f is an output waveform of the zero crossing detector 510, and FIG. 5g is an output waveform of the counter 520. FIG.

A process of restoring data adaptively to a communication environment will be described with reference to the above configuration.

The radio signal transmitted from other equipment is introduced through the antenna 200 and the signal is converted into a low frequency signal by the radio receiver 201. The low frequency signal is input to the demodulator 202 to demodulate and output a baseband signal. The baseband signal performs an acquisition tracking operation of first detecting an edge of the baseband signal and extracting a clock of the received data based on the baseband signal in order to recover stable data from the clock restorer 203. . The clock signal restored in this way is used as a clock signal in all subsequent data processing.

On the other hand, the data decompressor 204 outputs the restored data 301 as shown in FIG. 4A by shaping the baseband signal in synchronization with the restored clock signal. The reconstructed data 301 is input to the frame detector 205, which detects the beginning of the frame from the reconstructed data 301 and is as shown in FIGS. 4C to 4E. The first to third frame memory bank enable signals 302 to 304 are generated, the frame data is sequentially stored in the first to third frame memory banks 206 to 208, and the counter enable signal 501 is generated. Enable the counter 520 in the frame query measurer 211.

The frame quality measurer 211 measures whether the edge of each bit is present in a desired window or not, and integrates the result for one frame period to measure how stable frame information is received while maintaining a stable signal state. It is a device to output digital value.

The clock and data recovered through the clock recoverer 203 and the data recoverer 204 are input to the frame detector 205. The frame detector 205 receives the signal to find the beginning of the frame and remains high for one frame period, as shown in FIG. 5A, the counter enable signal 501 and the memory bank enable signal. Outputs 302 to 304. At this time, the window as shown in FIG. 5C, which is shifted by the recovery clock 502 and the recovery clock 502, as shown in FIG. 5B, output from the clock restorer 203, by 1/2. The clock 503 is input to the edge detector 530.

The edge detector 530 detects an edge by inputting received data as shown in FIG. 5D. If no frame is detected initially, the reset signal 505 of the zero crossing detector 510 output from the frame detector 205 becomes high, so that the output of the logic circuit combining the output of the edge detector 530 becomes high. do.

When the frame detector 205 finds the start of the frame, the zero crossing detector reset signal 505, as shown in FIG. 5E, generates a high pulse at every rising edge of the window clock 503, so that the signal The output of the edge detector 530 is made low. The flip-flop 511 makes the output high when there is a rising edge occurring in the data decompressor output signal 504 during the period in which the window clock 503 is high, and the flip-flop 512 makes the window clock 503 high. The output is made high when there is a falling edge occurring in the data restorer output signal 504 in the period where the high), and the edge detector 513 outputs the data restorer in the period when the window clock 503 is low. If the signal 504 has a falling edge, the output goes low, and the flip-flop 514 has a falling edge in the output signal 504 of the data restorer 204 during the period when the window clock 503 is low. Will make the output high.

The signals cause the output 506 to be high only when no edges are generated both within and outside the window by the logic circuit 515 and only when there is an edge only within the window (whether falling edge or rising edge). . This means that data is normally received and this signal only counts high by the clock recovered during the counter enable signal 501 during one frame period generated from the frame detector 205.

The zero crossing detector output signal 506, as shown in FIG. 5F, is used to process the data stored in the memory banks 206 to 208 when the data stored in the memory banks 206 to 208 is processed by the majority vote logic. Used as a signal to determine quality. The frame quality detection signal 507 outputted from the counter 520, as shown in FIG. 5G, is associated with the corresponding frame memory bank enable signals 302 to 304 so that each frame is connected to the memory banks 206 to 208. Is stored in the latches 212 to 214 so that the signal state of each frame is maintained by the latches 212 to 214. Then, when all the data of each frame is stored in the memory banks 206 to 208, the first data in each of the memory banks 206 to 208 is output by the recovered clock. These outputs are respectively passed to the first to third multipliers 215 to 217 to be multiplied by the frame quality signals 305 to 307 held in the first to third latches 212 to 214. Since the signals 305 to 307 are digital values of the signal states of the received frames, weights are given to the data according to the reception states measured for each frame during the multiplication process.

The signals are then all added at adder 218. This added result determines the data 308. This data 308 is finally output through the buffer 210.

In conclusion, when the frame quality detection result indicates that the signal is in a good state, the data output to the memory bank is regarded as reliable information, and the weight is given a lot. By giving less weight, reliable data can be recovered.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

Claims (8)

A demodulator for demodulating data from a radio signal transmitted from another device, a data decompressor for restoring data from an output of the demodulator, and detecting frame start from an output signal of the demodulator and sequentially storing frame data in a corresponding memory bank A frame detector; a clock restorer for restoring a clock from an output signal of the demodulator; and a frame detector for receiving the frame data of the frame detector in response to an output clock of the clock restorer; In a wireless communication system having a plurality of memory banks to be stored in the frame, the frame quality measuring unit for measuring the reception state of the frame information of the data recovered from the data restorer to generate a frame quality measurement signal, and the output of the frame detector In response to a signal Group data restoration characterized by the logic of the output of the frame-quality measurement of the recovered data stored in the memory bank operation part configured to determine that the adaptive majority decision circuit for data transmission environments. A demodulator 202 for demodulating and outputting a received signal by removing a carrier signal from a radio signal transmitted from another device, a clock restorer 203 for restoring and outputting a clock signal from the demodulated signal, and the demodulator 202 A data detector (204) for restoring and outputting data from the output of the < RTI ID = 0.0 >) < / RTI > and a frame detector for receiving a clock from the clock restorer (203) and detecting the start of a frame from the output of the data restorer (204). 205 and data received from the output of the clock decompressor 203 and the beginning of the frame from the output of the frame detector 205 and the data reconstructed from the output of the data decompressor 204 for each frame. Receive the clocks from the plurality of memory banks 206 to 208 and the clock restorer 203 and sequentially output them to the output of the frame detector 205. A frame quality measurer 211 for receiving frame information, receiving data restored from the output of the data reconstructor 204, measuring and outputting the quality of each frame, and stored in the plurality of memory banks 206 to 208. And a decision unit 109 for performing logical operation on the restored data corresponding to each frame and the output signal of the frame query measurer 211 measuring the quality of each frame to determine final data. Circuit. The method of claim 1, wherein the determination unit 109 temporarily stores and outputs an output signal of the frame quality meter 211 in response to an output signal of the frame detector 205. A holding unit 212 to 214, and arithmetic units 215 to 217 and 218 for logically calculating all first data stored in the memory banks 206 to 208 and a corresponding frame quality signal. Data recovery circuit. 4. The plurality of latches of claim 3, wherein the holding units 212 to 214 each include a plurality of latches for temporarily storing the quality information of the corresponding frame in response to the frame quality detection signal whenever each frame data is stored in the memory bank. 212 to 214). The memory of claim 3, wherein the calculators 215 to 217 and 218 are configured to recover the recovered data of each frame output from the plurality of memory banks 206 to 208, and to output each frame from the holding units 212 to 214. The multipliers 215 to 217 multiplied by the quality measurement signals of the multiplier and the outputs of the multipliers 215 to 217 are summed to finally determine the quality of the frame of the data transmitted a plurality of times. And a summer (218) for reflecting and determining more accurate final data. The apparatus of claim 1 or 2, wherein the frame quality measurer 211 receives the output data of the data reconstructor 204 and is provided with the reconstructed clock provided by the clock restorer 203. A zero crossing detector 510 which receives a shifted signal by 1/2 and sets a predetermined period at which data polling or rising occurs, and receives a zero crossing reset signal 505 from an output of the frame detector 205 and the clock; And a counter for receiving a clock signal from the reconstructor 203, receiving a counter enable signal 501 from the frame detection 205, and counting and outputting a signal output from the zero crossing detector. Circuit. The zero crossing detector 510 is configured to logic an edge detector 530 for detecting whether a falling edge or a rising edge is present inside or outside the window section, and the output of the edge detector 530. And a logic circuit (515) for calculating and outputting a good signal. 8. The data recovery circuit according to claim 7, wherein the edge detector (530) comprises flip-flops (511 to 514).