KR0151184B1 - Planation method of semiconductor device - Google Patents
Planation method of semiconductor device Download PDFInfo
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- KR0151184B1 KR0151184B1 KR1019940031210A KR19940031210A KR0151184B1 KR 0151184 B1 KR0151184 B1 KR 0151184B1 KR 1019940031210 A KR1019940031210 A KR 1019940031210A KR 19940031210 A KR19940031210 A KR 19940031210A KR 0151184 B1 KR0151184 B1 KR 0151184B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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Abstract
본 발명은 메가 비트 DRAM급 이상에서 금속플러그와 금속플러그 사이의 반도체 소자의 평탄화 공정으로서, 특히 에치백공정을 하지 않고 금속 플러그상의 스핀 온 글라스 두께를 감소시킬 수 있는 반도체 소자의 평탄화 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planarization process of a semiconductor device between a metal plug and a metal plug above a mega bit DRAM class, and more particularly, to a planarization process of a semiconductor device capable of reducing the thickness of a spin on glass on a metal plug without an etch back process. .
상기 목적을 달성하기 위한 반도체 소자의 평탄화 방법은 절연막상에 금속플러그를 형성하는 공정, 상기 금속 플러그 및 절연막상에 걸쳐 제1ILD층을 증착하는 공정, 상기 제1ILD층상에 SOG 도포층을 형성하는 공정, 상기 SOG 도포층에 불순물 이온 주입하고 열처리하여 SOG 도포층을 수축시키는 공정, 상기 수축된 SOG 도포층상에 제2ILD층을 증착하는 공정을 포함하여 이루어짐을 특징으로 한다.In order to achieve the above object, a planarization method of a semiconductor device includes forming a metal plug on an insulating film, depositing a first ILD layer on the metal plug and the insulating film, and forming a SOG coating layer on the first ILD layer. And shrinking the SOG coating layer by implanting impurity ions into the SOG coating layer and performing heat treatment, and depositing a second ILD layer on the contracted SOG coating layer.
따라서, 본 발명의 반도체 소자 평탄화 방법은 다음과 같은 효과가 있다.Therefore, the semiconductor device planarization method of the present invention has the following effects.
첫째, 에치백공정을 하지 않고 Siloxane group SOG필름에 불순물 이온주입을 한 후 베이크를 진행함으로써 금속 플러그상의 SOG 두께를 쉽게 조절할 수 있다.First, it is possible to easily control the thickness of the SOG on the metal plug by injecting impurity ions into the Siloxane group SOG film without performing an etch back process and then baking.
둘째, 불순물 이온주입된 SOG 공정은 공정이 간단하여 공정관리가 용이하며 이물질이 발생하지 않기 때문에 이물질에 대한 영향을 받지 않아 반도체 소자의 높은 수율을 얻을 수 있다.Second, since the impurity ion implanted SOG process is simple, it is easy to manage the process, and since no foreign matters are generated, it is not affected by foreign matters and thus a high yield of a semiconductor device can be obtained.
Description
제1도는 종래의 반도체 소자의 평탄화 공정단면도1 is a cross-sectional view of a planarization process of a conventional semiconductor device
제2도는 본 발명의 반도체 소자의 평탄화 공정단면도2 is a cross-sectional view of the planarization process of the semiconductor device of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 절연막 22 : 금속플러그21: insulating film 22: metal plug
23 : 제1ILD층 24 : SOG 도포층23: 1st ILD layer 24: SOG coating layer
25 : 불순물(F-) 이온주입 26 : 제2ILD층25 impurity (F − ) ion implantation 26: second ILD layer
본 발명은 메가 비트(Mega Bit)급 이상에서 금속플러그와 금속플러그 사이의 반도체 소자의 평탄화 공정으로서, 특히 에치 백(Etch Back) 공정을 하지 않고 금속 플러그상의 스핀 온 글라스(Spin On Glass : 이하 SOG라 약칭함) 두께를 감소시킬 수 있는 반도체 소자의 평탄화 방법에 관한 것이다.The present invention is a planarization process of a semiconductor device between a metal plug and a metal plug in a mega bit or more, in particular, spin on glass (SOG) on a metal plug without an etch back process. The present invention relates to a planarization method of a semiconductor device capable of reducing thickness.
일반적으로 SOG는 이중 금속 배선층(Double Level Metallization)에서 첫 번째 금속상의 거친 지형(poor topology)을 평탄화하는데 쓰이는 가장 간단한 방법중에 하나이다.In general, SOG is one of the simplest methods used to planarize the rough topology of the first metal in double level metallization.
이와 같은 SOG는 크게 Silicate group SOG와 Siloxane group SOG로 분리되고 소자의 크기가 축소됨에 따라 선폭, 선과 선사이의 간격이 줄고, 비아 홀(Via Hole)의 크기도 줄어들고 있어 16M DRAM급 이상에서는 Silicate group SOG에 비해 크랙(crack)에 대한 높은 저항성을 갖으며, 내흡수성 및 평탄화가 극히 우수한 Siloxane group SOG를 사용한다.Such SOG is largely divided into Silicate group SOG and Siloxane group SOG, and as the size of the device is reduced, the line width, the distance between lines and lines are decreasing, and the size of via hole is decreasing. Compared to using a crack (silkane group SOG), which has high resistance to cracks and excellent absorption and planarization.
이하 첨부된 도면을 참고하여 종래의 반도체 소자의 평탄화 방법을 설명하면 다음과 같다.Hereinafter, a planarization method of a conventional semiconductor device will be described with reference to the accompanying drawings.
제1도는 종래의 반도체 소자의 평탄화 공정단면도를 나타낸 것으로, 제1도(a)에서와 같이 절연막(1)상에 증착된 금속을 사진 식각공정으로 금속 플러그 형성영역을 패터닝하여 금속 플러그(2)를 형성한다.FIG. 1 is a cross-sectional view of a planarization process of a conventional semiconductor device. As shown in FIG. 1 (a), a metal plug formation region is patterned by patterning a metal plug formation region by a photolithography process on a metal deposited on an insulating film 1. To form.
제1도 (b)에서와 같이 상기 금속플러그(2)층과 노출된 절연막 전영역에 금속플러그와 SOG의 직접적인 접촉을 방지하기 위하여 제1유전체층(3)(Inter Layer Dielectric : 이하 ILD이라 약칭함)을 증착한다.As shown in FIG. 1 (b), the first dielectric layer 3 (hereinafter referred to as ILD) is used to prevent direct contact between the metal plug and the entire surface of the exposed insulating layer with the metal plug and SOG. E).
그리고, 금속플러그의 단차 때문에 생긴 낮은 피복률(poor step coverage)을 개선하기 위하여 평탄화 공정의 일환으로써 제1도 (c)에서와 같이 Siloxane group SOG스핀(spin)을 진행하여 SOG 도포층(4)을 형성하고, 상기 SOG 도포층(4)을 기판온도 450℃에서 25분간 열처리(Bake)한다.In order to improve low pore step coverage due to the step of the metal plug, as in part of the planarization process, as in FIG. The SOG coating layer 4 is heat-treated (baked) at a substrate temperature of 450 ° C. for 25 minutes.
이어서 제1도 (d)에서와 같이 플러그(2)상의 SOG 두께를 낮추기 위하여 SOG 에치백 공정으로 금속 플러그상에 형성된 SOG 도포층(4)을 완전하게 제거하고, 제1도(e)에서와 같이 상기 에치백된 노출표면 전영역에 제2ILD층(5)을 증착, 반도체 소자의 평탄화를 형성한다.Subsequently, in order to lower the thickness of the SOG on the plug 2, as shown in FIG. 1 (d), the SOG coating layer 4 formed on the metal plug is completely removed by the SOG etchback process, and in FIG. As described above, the second ILD layer 5 is deposited on the entire exposed surface of the etched back surface, thereby forming planarization of the semiconductor device.
그러나 이와같은 종래의 반도체 소자의 평탄화 방법에 있어서는 다음과 같은 문제점이 있었다.However, such a conventional planarization method of a semiconductor device has the following problems.
즉, Siloxane group SOG을 사용하므로써, 크랙(crack)이 발생하지 않고 내흡수성 및 평탄화가 우수하지만 에치백 공정을 해야하므로 공정이 복잡하며 공정을 콘트롤하기 어렵다.In other words, by using the Siloxane group SOG, cracks do not occur and the water absorption and planarization are excellent, but the etchback process is required, which makes the process complicated and difficult to control the process.
뿐만 아니라 에치백 공정중에 많은 이물질이 발생하게 된다.In addition, many foreign substances are generated during the etch back process.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 16M DRAM급 이상에서도 Siloxane group SOG를 사용할 때 에치 백(Etch Back)공정을 하지 않고, 금속플러그상의 SOG 두께를 감소시키고 또한 평탄화할 수 있는 반도체소자의 평탄화방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is possible to reduce and flatten the thickness of the SOG on the metal plug without an etch back process when using the Siloxane group SOG even in 16M DRAM or higher. It is an object of the present invention to provide a planarization method of a semiconductor device.
이와 같은 목적을 달성하기 위한 본 발명의 반도체 소자 평탄화방법은 절연막상에 금속플러그를 형성하는 공정, 상기 금속 플러그 및 절연막상에 걸쳐 제1ILD층을 증착하는 공정, 상기 제1ILD층상에 SOG 도포층을 형성하는 공정, 상기 SOG 도포층에 불순물 이온 주입하고 열처리하여 SOG 도포층을 수축시키는 공정, 상기 수축된 SOG 도포층상에 제2ILD층을 증착하는 공정으로 이루어짐을 특징으로 한다.The semiconductor device planarization method of the present invention for achieving the above object comprises the steps of forming a metal plug on the insulating film, depositing a first ILD layer over the metal plug and the insulating film, and applying an SOG coating layer on the first ILD layer And forming a second ILD layer on the contracted SOG coating layer by shrinking the SOG coating layer by implanting impurity ions into the SOG coating layer and heat treatment.
상기와 같은 본 발명의 반도체 소자의 평탄화 방법을 첨부된 도면을 참고하여 설명하면 다음과 같다.Referring to the accompanying drawings, the planarization method of the semiconductor device of the present invention as described above is as follows.
제2도는 본 발명의 반도체 소자의 평탄화 방법을 나타낸 공정단면도이다.2 is a process cross-sectional view showing the planarization method of the semiconductor device of the present invention.
제2도 (a)에 도시된 바와 같이 절연막(21)상에 금속층을 증착하고, 사진 식각공정으로 상기 금속층을 선택적으로 제거하여 금속 플러그(22)를 형성한다.As shown in FIG. 2A, a metal layer is deposited on the insulating layer 21, and the metal layer is selectively removed by a photolithography process to form a metal plug 22.
그리고, 상기 금속 플러그(22)와 SOG의 직접적인 접촉을 방지하기 위하여 제2도 (b)에서와 같이 제1ILD층(23)을 증착하고 이어서 제2도 (c)에서와 같이 금속플러그(22)의 단차 때문에 생기는 낮은 피복률(poor step coverage)을 개선하기 위하여 평탄화공정으로써 SOG 스핀(spin)공정을 진행하여 SOG 도포층(24)을 형성하고, 기판온도 450℃에서 25분간 열처리(Bake)한다.In order to prevent direct contact between the metal plug 22 and the SOG, the first ILD layer 23 is deposited as shown in FIG. 2B, and then the metal plug 22 as shown in FIG. 2C. In order to improve the low step coverage due to the step difference, the SOG spin process is performed as a planarization process to form the SOG coating layer 24, and heat treatment is performed at a substrate temperature of 450 ° C. for 25 minutes. .
이에 의해서 SOG 도포층(24)은 평탄화된다.As a result, the SOG coating layer 24 is planarized.
여기서 SOG는 Siloxane group SOG를 사용한다.Here, the SOG uses a Siloxane group SOG.
제2도 (d)에서와 같이 상기 SOG 도포층(24)에 불순물(F-) 이온주입(25)을 실시한다.As shown in FIG. 2 (d), impurity (F − ) ion implantation 25 is applied to the SOG coating layer 24.
이때 불순물(F-) 이온주입은 30∼90KeV 에너지, 도즈(dose)량이 E11∼E15atom/㎠ 조건하에서 실시한다.At this time, the impurity (F − ) ion implantation is performed under conditions of 30 to 90 KeV energy and dose amount of E 11 to E 15 atom / cm 2.
제2도 (e)에서와 같이 상기 불순물(F-) 이온주입된 SOG도포층(24)을 열처리(Bake)한다. 이에 따라서 상기 불순물(F-) 이온주입된 Siloxane SOG 특성이 변화된다.As in FIG. 2 (e), the SOG coating layer 24 implanted with the impurity (F − ) ion is heat-treated. Accordingly, the characteristics of the Siloxane SOG into which the impurity (F − ) is implanted are changed.
이와 같이 F-가 주입된 SOG 도포층(24)을 열처리를 하면 SOG 도포층(24)이 수축(Film shrinkage) 된다.As described above, when the SOG coating layer 24 into which F − is injected is heat-treated, the SOG coating layer 24 is contracted.
또한 SOG 도포층(24)이 수축(shrinkage)됨으로써 금속 플러그(22)상의 SOG 도포층(24)의 두께는 상당히 감소하게 된다.In addition, as the SOG coating layer 24 shrinks, the thickness of the SOG coating layer 24 on the metal plug 22 is significantly reduced.
이로써 SOG 도포층(24)을 에치백하지 않고도 에치백 공정을 진행하게 된 효과를 얻을 수 있다.Thereby, the effect which advances the etch back process can be acquired, without etching back the SOG coating layer 24.
상기 SOG 도포층(24)의 수축이 일어나는 이유는 열처리(Bake) 공정중 OH기의 증발(Evaporation)로써 설명할 수 있다.The shrinkage of the SOG coating layer 24 may be explained by evaporation of the OH group during the heat treatment (Bake) process.
OH기의 증발에 대한 설명을 하기전에 이온이 주입되지 않은 Siloxane group SOG와 이것을 열처리 하였을 때의 원소들이 본딩(Bonding)결합을 나타내면 다음과 같다.Before explaining the evaporation of the OH group, the following examples show the bonding bond between the Siloxane group SOG without ion implantation and the elements when heat-treating it.
다음으로 이온주입된 Siloxane group SOG와 이것을 열처리 하였을 때의 원소들의 본딩(Bonding)결합을 나타내면 다음과 같다.Next, the bonding bonds of the ion implanted Siloxane group SOG and the elements when heat-treated are as follows.
상기에 나타낸 바와 같이 이온주입되지 않은 Siloxane group SOG는 베이크(Bake)공정을 하여도 OH기의 증발(Evaporation)이 잘 이루어지지 않음을 알 수 있다.As described above, it is understood that Siloxane group SOG, which is not ion-implanted, is not well evaporated even in the baking process.
그러나 F-가 주입된 SOG 도포층(24)은 베이크(Bake) 진행중 F-CH3가 형성되면서 CH3가 OH기를 잡고 있는 힘을 감소시켜주기 때문에 OH기의 증발(Evaporation)이 촉진된다.However, since the F - injected SOG coating layer 24 reduces the force of CH 3 holding the OH group while F-CH 3 is formed during baking, evaporation of the OH group is promoted.
즉, C-F가 결합하려는 에너지가 C-O가 결합하려는 에너지 보다 크기 때문에 OH기가 CH3에서 떨어져나오고 F-가 CH3와 결합하는 것이다. 그리고 베이트 공정시에 H-O의 결합에너지보다 H-F의 결합에너지가 더 크기 때문에 H도 떨어져 나온다.That is, since the energy to CF is greater than the binding energy to the combined CO OH groups coming off the CH 3 F - to combine with a CH 3. In addition, since the bonding energy of HF is greater than that of HO in the bait process, H is also released.
이와 같이 떨어져 나온 OH기나 H는 H2나 H2O와 같은 형태로 증발하게 된다. 즉, SOG 도포층(24)에서 수분성분이 증발하게 되므로 SOG 도포층(24)이 수축하게 되는 것이다. 그리고 F-가 주입된 SOG 도포층(24)을 수축시키기 위해서 열처리 공정을 함과 동시에 SOG 도포층(24)도 평탄화되고 따라서 전체적으로 소자가 평탄하게 된다.Thus separated OH group or H will evaporate in the form of H 2 or H 2 O. That is, since the moisture component is evaporated from the SOG coating layer 24, the SOG coating layer 24 is contracted. In addition, the SOG coating layer 24 is also flattened while the heat treatment process is performed to shrink the SOG coating layer 24 into which F − is injected.
다음에 에치백 효과가 일어난 SOG 도포층(24)상에 제2도 (f)에서와 같이 제2ILD(26)을 증착하여 반도체 소자의 평탄화를 형성한다.Next, the second ILD 26 is deposited on the SOG coating layer 24 having the etch back effect as shown in FIG. 2 (f) to form a planarization of the semiconductor device.
상기와 같은 본 발명의 반도체 소자 평탄화 방법은 하기와 같은 효과가 있다.The semiconductor device planarization method of the present invention as described above has the following effects.
첫째, 에치백(Etch-Back)공정을 하지않고 Siloxane group SOG필름에 불순물(F-) 이온주입을 한 후 베이크(Bake)를 진행함으로써 금속 플러그상의 SOG 두께를 쉽게 조절할 수 있다.First, the thickness of the SOG on the metal plug can be easily controlled by performing a bake after impurity (F − ) ion injection into the Siloxane group SOG film without performing an etch-back process.
둘째, 불순물(F-)이온주입된 SOG(F-implanted SOG)공정은 공정이 간단하여 공정관리가 용이하며 이물질이 발생하지 않기 때문에 이물질에 대한 영향을 받지않아 반도체 소자의 높은 수율을 얻을 수 있다.Second, the impurities (F -) ion-implanted SOG (F - implanted SOG) processes are unaffected on this substance does not generate a foreign matter, and is easy to process control by the process is simple, it is possible to obtain a high yield of the semiconductor element .
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| KR1019940031210A KR0151184B1 (en) | 1994-11-25 | 1994-11-25 | Planation method of semiconductor device |
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