KR0151182B1 - Silicon film patterning method by recrystalization of polysilicon - Google Patents
Silicon film patterning method by recrystalization of polysilicon Download PDFInfo
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- KR0151182B1 KR0151182B1 KR1019940027732A KR19940027732A KR0151182B1 KR 0151182 B1 KR0151182 B1 KR 0151182B1 KR 1019940027732 A KR1019940027732 A KR 1019940027732A KR 19940027732 A KR19940027732 A KR 19940027732A KR 0151182 B1 KR0151182 B1 KR 0151182B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H01L21/02686—Pulsed laser beam
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Abstract
본 발명은 폴리실리콘의 재결정화에 의한 실리콘막 패턴의 형성방법에 관한 것으로, 그레인 경계가 존재하지 않는 폴리실리콘 아일랜드를 형성하기 위한 것이다.The present invention relates to a method of forming a silicon film pattern by recrystallization of polysilicon, to form a polysilicon island having no grain boundary.
본 발명은 재결정화시키고자 하는 폴리실리콘층상부에 소정의 산화막패턴을 형성하는 단계와, 폴리실리콘에 흡수가 잘되는 레이저로 상기 상부에 산화막패턴이 형성된 폴리실리콘층을 어닐링하는 단계, 상기 산화막패턴을 마스크로 하여 상기 폴리실리콘층을 식각하는 단계로 이루어지는 것을 특징으로 하는 폴리실리콘의 재결정에 의한 실리콘막 패턴 형성방법을 제공함으로써 적절한 온도분포의 조절에 의해 그레인 경계가 거의 없는 폴리실리콘 아일랜드로 이루어진 소자형성영역을 형성하여 양질의 능동소자를 구현할 수 있도록 한다.The present invention comprises the steps of forming a predetermined oxide film pattern on the polysilicon layer to be recrystallized, annealing the polysilicon layer having the oxide film pattern formed thereon with a laser that absorbs well in the polysilicon, the oxide film pattern Forming a silicon film pattern by recrystallization of polysilicon, wherein the polysilicon layer is etched using a mask, thereby forming a device made of a polysilicon island having almost no grain boundaries by controlling an appropriate temperature distribution. By forming the area, it is possible to realize a high quality active device.
Description
제1도는 종래의 레이저 어닐링을 통한 폴리실리콘의 재결정화에 의한 실리콘 아일랜드 형성방법을 도시한 공정순서도.1 is a process flowchart showing a method of forming a silicon island by recrystallization of polysilicon through a conventional laser annealing.
제2도는 본 발명의 레이저 어닐링을 통한 폴리실리콘의 재결정화에 의한 실리콘 아일랜드 형성방법을 도시한 공정순서도.2 is a process flow chart showing a method for forming a silicon island by recrystallization of polysilicon through laser annealing of the present invention.
제3도는 본 발명의 레이저 어닐링시 폴리실리콘층의 각 부분에 있어서의 온도분포곡선.3 is a temperature distribution curve in each part of the polysilicon layer during laser annealing of the present invention.
제4도는 본 발명의 레이저 어닐링에 의해 폴리실리콘층에 형성된 그레인 경계를 도시한 도면.4 shows grain boundaries formed in a polysilicon layer by laser annealing of the present invention.
제5도는 상온에서의 실리콘의 각 파장에 대한 흡수계수 및 반사도를 나타낸 도면.5 is a graph showing absorption coefficients and reflectances of respective wavelengths of silicon at room temperature.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 하지층 2 : 폴리실리콘층1: base layer 2: polysilicon layer
3 : 레이저 주사방향 4 : 레이저빔의 스폿크기3: laser scanning direction 4: spot size of laser beam
5 : 그레인 경계 6 : 산화막패턴5: grain boundary 6: oxide film pattern
본 발명은 폴리실리콘의 재결정화에 의한 실리콘막 패턴의 형성방법에 관한 것으로, 특히 레이저 어닐링(laser annealing)공정에 의해 폴리실리콘을 재결정화하여 반도체소자 형성을 위한 아일랜드(island)를 형성하는 방법에 관한 것이다.The present invention relates to a method of forming a silicon film pattern by recrystallization of polysilicon, and more particularly to a method of forming an island for forming a semiconductor device by recrystallizing polysilicon by a laser annealing process. It is about.
종래의 레이저 어닐링을 통한 폴리실리콘의 재결정화에 의해 반도체소자 형성을 위한 아일랜드를 형성하는 방법을 제1도를 참조하여 설명하면 다음과 같다.A method of forming an island for forming a semiconductor device by recrystallization of polysilicon through a conventional laser annealing will be described with reference to FIG.
먼저, 제1도(a)에 도시된 바와 같이 하지층(1)상에 폴리실리콘층(2)을 형성한 후, 폴리실리콘층에 레이저빔을 일방향(3)으로 주사하고, 이와 중첩시키거나 평행하게 폴리실리콘층 전체에 걸쳐 레이저빔을 주사하면, 레이저빔의 스폿크기(spot size)(4)안에 있는 영역의 폴리실리콘이 녹는 점가지 온도가 상승하였다가 냉각되면서 온도분포상 먼저 냉각되는 점부터 재결정화가 이루어져 폴리실리콘의 그레인(grain)이 커지면서 그레인 경계가 재배열되며, 결과적으로 제1도(b)에 도시된 바와 같이 레이저빔의 주사방향과 평행하게 그레이 경계(5)의 밀집된 형태가 나타나게 된다.First, as shown in FIG. 1 (a), the polysilicon layer 2 is formed on the base layer 1, and then the laser beam is scanned in one direction 3 on the polysilicon layer and superimposed thereon. When the laser beam is scanned in parallel across the polysilicon layer, the temperature at which the polysilicon melts in the area within the spot size (4) of the laser beam is increased and then cooled and cooled first. Recrystallization takes place and the grain boundaries of the polysilicon become larger, resulting in rearrangement of the grain boundaries. As a result, as shown in FIG. do.
이와 같이 그레인 경계(5)가 재배열된 폴리실리콘층(2)을 패터닝하여 제1도(c)에 도시된 바와 같이 소자형성영역인 아일랜드를 형성한다.The polysilicon layer 2 with the grain boundaries 5 rearranged is patterned to form an island, which is an element formation region, as shown in FIG.
상기 종래기술에 있어서, 레이저빔은 한 방향의 축에 따라 주사되는데, 소자형성영역이 2차원적인 구조를 가지게 되면 제1도(c)에 도시된 바와 같이 소자형성영역내에 그레인 경계(5)가 존재하게 되어 구현하고자 하는 소자의 특성을 열화시키고 특성의 편차를 크게 만드는 문제가 발생한다.In the prior art, the laser beam is scanned along an axis in one direction. When the device formation region has a two-dimensional structure, the grain boundary 5 is formed in the device formation region as shown in FIG. There exists a problem of deteriorating the characteristics of the device to be implemented to increase the variation of the characteristics.
본 발명은 상술한 문제를 해결하기 위한 것으로, 그레인 경계가 존재하지 않는 폴리실리콘 아일랜드를 형성할 수 있는 레이저 어닐링을 통한 폴리실리콘의 재결정화에 의한 실리콘막 패턴 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object thereof is to provide a method of forming a silicon film pattern by recrystallization of polysilicon through laser annealing, which can form a polysilicon island having no grain boundaries.
상기 목적을 달성하기 위한 본 발명의 폴리실리콘의 재결정화에 의한 실리콘막 패턴 형성방법은 재결정화시키고자 하는 폴리실리콘층상부에 소정의 산화막패턴을 형성하는 단계와, 폴리실리콘에 흡수가 잘되는 레이저로 상기 상부에 산화막패턴이 형성된 폴리실리콘층을 어닐링하는 단계, 상기 산화막패턴을 마스크로 하여 상기 폴리실리콘층을 식각하는 단계로 이루어진다.In order to achieve the above object, a method of forming a silicon film pattern by recrystallization of polysilicon of the present invention includes forming a predetermined oxide film pattern on an upper part of a polysilicon layer to be recrystallized; Annealing the polysilicon layer having the oxide film pattern formed thereon, and etching the polysilicon layer using the oxide film pattern as a mask.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2도에 본 발명에 의한 폴리실리콘의 재결정화에 의한 실리콘막 패턴 형성방법을 도시하였다.2 shows a method of forming a silicon film pattern by recrystallization of polysilicon according to the present invention.
먼저, 제2도(a)에 도시된 바와 같이 하지층(1)상부에 재결정화시키고자 하는 폴리실리콘층(2)을 형성하고, 이위에 산화막패턴(6)을 형성한 후, 이 산화막을 소자형성 영역인 아일랜드 형태로 패터닝한다.First, as shown in FIG. 2A, a polysilicon layer 2 to be recrystallized is formed on the base layer 1, an oxide film pattern 6 is formed thereon, and then the oxide film is formed. Patterning is performed in an island form, which is an element formation region.
다음에 제2도(b)에 도시된 바와 같이 비교적 폴리실리콘에 흡수가 잘되는 레이저인 XeCl레이저를 펄스로 조사시키면서 소정의 방향(3)에 따라 주사하여 레이저어닐을 실시한다. 이때, 해당 파장에서 폴리실리콘의 흡수계수가 산화막이 흡수계수에 비해 높고, 또한 산화막의 높이를 조절하면 반사도를 조절할 수 있으므로 제3도에 도시된 바와 같이 산화막패턴내에 해당하는 폴리실리콘부분의 온도가 더 낮은 분포를 가지도록 할 수 있다. 제5도는 상온에서의 실리콘의 각 파장에 대한 흡수계수 및 반사도를 나타낸 것으로, 참조부호 A부분은 XeCl레이저의 경우를 나타낸다.Next, as shown in FIG. 2 (b), laser annealing is performed by scanning along a predetermined direction (3) while irradiating with pulses an XeCl laser, which is a laser that absorbs relatively well to polysilicon. At this time, the absorption coefficient of the polysilicon is higher than the absorption coefficient of the polysilicon at the corresponding wavelength, and the reflectivity can be adjusted by adjusting the height of the oxide film. Thus, as shown in FIG. Can have a lower distribution. FIG. 5 shows absorption coefficients and reflectances of the respective wavelengths of silicon at room temperature, and part A of FIG. 5 shows a case of an XeCl laser.
레이저빔은 단일파장을 가지고 있으므로 조사되는 매질의 두께를 변화시켜면 간섭 및 보간효과를 일으킨다. 이런 점을 이용하여 상기와 같이 비교적 폴리실리콘에 흡수가 잘되는 XeCl레이저를 사용하여 레이저 어닐을 하게 되면 산화막패턴 하부의 폴리실리콘층의 온도가 그 주변보다 낮게 되므로 제3도에 도시된 바와 같이 산화막패턴 하부에 해당하는 폴리실리콘층의 중심부분부터 먼저 녹는점 아래로 냉각되면서 이 부분이 시드(seed)가 되어 재결정화가 이루어지게 된다.Since the laser beam has a single wavelength, changing the thickness of the irradiated medium causes interference and interpolation effects. When the laser annealing is performed using the XeCl laser, which is relatively well absorbed by polysilicon as described above, the temperature of the polysilicon layer under the oxide layer pattern is lower than that of the surroundings. From the center of the polysilicon layer corresponding to the lower portion of the first cooling point below the melting point as the seed (seed) is recrystallization is made.
결국 그레인경계는 재결정화에 의해 시드를 중심으로 확장되는 그레인영역이 다른 그레인영역과 만나는 경계면이므로 본 발명의 경우, 레이저 어닐링시 가장 늦게 냉각되는 지점에 형성되는 그레인 경계는 제4도에 도시된 바와 같이 산화막 패턴의 바깥쪽에 위치하게 된다.As a result, the grain boundary is a boundary surface where the grain region extending around the seed by recrystallization meets another grain region, and thus, in the present invention, the grain boundary formed at the point where it is cooled most recently during laser annealing is shown in FIG. Likewise, it is located outside of the oxide film pattern.
이후에 제2도(c)에 도시된 바와 같이 상기 산화막패턴(6)을 마스크로 하여 폴리실리콘층(2)을 식각하면 그레인 경계가 밀집된 영역은 식각에 의해 제거되고 거의 단결정에 가까울 폴리실리콘 아일랜드가 얻어진다.Subsequently, as shown in FIG. 2C, when the polysilicon layer 2 is etched using the oxide layer pattern 6 as a mask, a region in which grain boundaries are densified is removed by etching, and a polysilicon island is almost close to a single crystal. Is obtained.
레이저 어닐링시 양호한 결과를 얻기 위해서는 레이저빔을 한 방향으로 주사해야 하는데 이때, 그 주사축과 평행하게 형성되는 그레인 경계의 밀집영역을 피하여 소자를 형성하려면 회로의 설계에 큰 제약을 받게 된다.In order to obtain a good result in laser annealing, the laser beam must be scanned in one direction. However, in order to form the device to avoid the dense area of the grain boundary formed in parallel with the scanning axis, the design of the circuit is severely limited.
그리고 본 발명에 의하면, 상술한 바와 같이 이러한 제약없이 재결정화하고자 하는 폴리실리콘층위에 산화막을 형성하고 어떠한 형태로든지 이 산화막에 소자형성영역을 정의한 후에 레이저 어닐에 의해 폴리실리콘층을 재결정화할 수 있으며, 적절한 온도분포의 조절에 의해 그레인 경계가 거의 없는 폴리실리콘 아일랜드를 형성할 수 있으므로 양질의 능동소자구현이 가능하게 된다.According to the present invention, the polysilicon layer can be recrystallized by laser annealing after forming an oxide film on the polysilicon layer to be recrystallized without such a restriction as described above and defining an element formation region in the oxide film in any form. By controlling the appropriate temperature distribution, it is possible to form polysilicon islands with almost no grain boundaries, thereby enabling high quality active devices.
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| KR1019940027732A KR0151182B1 (en) | 1994-10-27 | 1994-10-27 | Silicon film patterning method by recrystalization of polysilicon |
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| KR1019940027732A KR0151182B1 (en) | 1994-10-27 | 1994-10-27 | Silicon film patterning method by recrystalization of polysilicon |
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| KR0151182B1 true KR0151182B1 (en) | 1998-12-01 |
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| KR100761867B1 (en) * | 2006-06-08 | 2007-09-28 | 재단법인서울대학교산학협력재단 | Gan semiconductor device and method for fabricating thereof |
| KR102463185B1 (en) * | 2016-12-13 | 2022-11-03 | 현대자동차 주식회사 | Front frame structure for a very low type bus |
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