KR0151121B1 - Dram transistor manufacturing device - Google Patents

Dram transistor manufacturing device

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Publication number
KR0151121B1
KR0151121B1 KR1019890018833A KR890018833A KR0151121B1 KR 0151121 B1 KR0151121 B1 KR 0151121B1 KR 1019890018833 A KR1019890018833 A KR 1019890018833A KR 890018833 A KR890018833 A KR 890018833A KR 0151121 B1 KR0151121 B1 KR 0151121B1
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South Korea
Prior art keywords
oxide film
gate
polysilicon
film
junction
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KR1019890018833A
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Korean (ko)
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KR910013260A (en
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김성철
노재성
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문정환
엘지반도체주식회사
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Priority to KR1019890018833A priority Critical patent/KR0151121B1/en
Publication of KR910013260A publication Critical patent/KR910013260A/en
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Publication of KR0151121B1 publication Critical patent/KR0151121B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

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  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음.No content.

Description

디램의 트랜지스터 제조방법DRAM manufacturing method

제1도는 종래의 제조순서를 나타낸 단면도.1 is a cross-sectional view showing a conventional manufacturing procedure.

제2도는 본 발명의 제조순서를 나타낸 단면도.2 is a cross-sectional view showing the manufacturing procedure of the present invention.

제3도와 제4도는 본 고안을 설명하기 위한 디바이스의평면도.3 and 4 are plan views of devices for explaining the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2 : 기본산화막1 substrate 2 basic oxide film

3 : 질화막 4,7,10 : P/R3: nitride film 4,7,10: P / R

5 : 산화막 6 : n- 정선5: oxide film 6: n-selection

8 : 게이트 산화막 9,12,14 : 폴리실리콘8 gate oxide film 9,12,14 polysilicon

11 : 저온 산화막 13: 유전체11: low temperature oxide film 13: dielectric

본 발명의 디렘(DRAM)의 트랜지스터 제조방법에 관한 것으로 특히 서브-하프 마이크론 모스트랜지스터(sub-half micron mosfet) 소자에 적당하도록 게이트를 라운드하게 형성하여 소오스/드레인 셀로우 정션(Shallow Junction)문제를 해결함은 물론 체널길이(Channel Length)를 효과적으로 증가시켜 쇼트(Short)채널 효과를 방지할 수 있도록 한 것이다.The present invention relates to a method for manufacturing a transistor of a DRAM, and in particular, to form a gate round to be suitable for a sub-half micron mosfet device, so as to solve a source / drain shallow junction problem. In addition, the channel length is effectively increased to prevent short channel effects.

종래의 디렘 트랜지스터 제조방법은 제1도의 (a)에 도시된 바와 같이 기판(1에 트랜지스터의 격리를 위해 필드산화막(5)을 형성하고 (b)와 같이 게이트 형성을 위한 게이트 산화막(8) 및 폴리 실리콘(9)을 형성하였다. 다음에 (c)와 같이 상기 게이트 산화막(8)과 폴리실리콘(9)을 식각(etch)하고 (d)와 같이 저온산화막(LTO)을 디포지션한 후 식각하여 측벽(side wall)(15)을 형성하므로 폴리실리콘 식각시 단차(step height difference)에 의해 게이트를 따라 리본(Ribon)이 형성되는 것을 방지하도록 하였다. 이후, (e)와 같이 이온을 주입하고 어닐(anneal)을 통해 소오스와 드레인을 형성하며 (f)와 같이 저온산화막(11) 디포지션 후 액티 영역과 스토리지 노드를 연결하기 위한 콘택트를 식각하고 마지막 공정으로(g)와 같이 폴리실리콘(12), 유전체(13), 폴리실리콘(14)을 차례로 형성하여 커페시터를 형성하였다.In the conventional method of manufacturing a DRAM transistor, a field oxide film 5 is formed on a substrate 1 for isolation of a transistor as shown in FIG. The polysilicon was formed 9. Next, as shown in (c), the gate oxide film 8 and the polysilicon 9 were etched and the low temperature oxide film LTO was deposited as shown in (d), followed by etching. By forming side walls 15, a ribbon is prevented from forming along the gate due to a step height difference during polysilicon etching. The source and drain are formed through annealing, and after the low temperature oxide film 11 deposition as shown in (f), the contact for connecting the active region and the storage node is etched, and as a final step (g), the polysilicon (12) is formed. ), Dielectric 13 and polysilicon 14 are formed in this order. To form a capacitor.

그러나, 상기와 같은 종래의 제조방법에 있어서는 디바이스 디자인룰(rule)의 감소로 인한 펀치 스로우(punch through)형상을 방지하기 위해 셀로우 소오스 및 드레인 정션이 필요하게 되는데 이런 셀로우 정션을 형성하기가 어려우며 또한 디바이스 디자인룰의 감소에 따른 이펙티브(effective) 채널길이의 감소때문에 디바이스의 집ㅂ적도를 증가시키는데 문제점이 있었다.However, in the conventional manufacturing method as described above, in order to prevent the punch through shape due to the reduction of device design rules, a shallow source and a drain junction are required. It is difficult and also has a problem in increasing the integration density of the device due to the reduction of the effective channel length due to the reduction of device design rules.

본 발명은 이와 같은 종래의 문제점을 해결하기 위하여 안출한 것으로 이를 첨부된 도면 제2도에 의하여 상세히 설명하면 다음과 같다.The present invention has been made in order to solve such a conventional problem and will be described in detail with reference to FIG.

본 발명은 먼저 (a)와 같이 기판(1)에 기본 산화막(2)와 질화막(3)을 디포지션하고 (b)(제3도의 A-A선 단면도)와 같이 P/R(4)에 의해 필드 형성을 위한 질화막(3)을 식각하는데 이때 기본공정과는 다르게 제3도와 같은 액티브 영역(AR)의 게이트 부분을 같이 식각한다.The present invention first deposits the basic oxide film 2 and the nitride film 3 on the substrate 1 as shown in (a), and the field is formed by the P / R (4) as shown in FIG. The nitride film 3 is formed to be etched. The gate portion of the active region AR as shown in FIG. 3 is etched differently from the basic process.

다음에 (c)와 같이 필드 산화를 통해 산화막(5)을 형성하며 이 공정을 거치면 게이트 부분에도 산화막이 자라게 된다.Next, as shown in (c), the oxide film 5 is formed through field oxidation. After this step, the oxide film also grows in the gate portion.

그리고 (d)와 같이 기본산화막(2)과 질화막(3)을 제거한 후 (e)와 같이 LDD 구조를 우한 n-정션(6)을 형성하기 위한 이온주임을 하며 이때 게이트 부분은 산화로 인해 정션이 형성되지 않는다.And after removing the basic oxide film (2) and the nitride film (3) as shown in (d) is an ion column for forming the n-junction (6) having a LDD structure as shown in (e), the gate portion is a junction due to oxidation It is not formed.

이후, (f)(제4도의 B-B선 단면도)와 같이 게이트 부분에 자란 산화막(5)을 제거하기 위해 이 산화막(5) 주위의 제거될 부분을 제외하고 P/R(7)을 도포하고 (g)와 같이 습식식각을 사용해 게이트 부분의 산화막(5)을 제거시킨다.Thereafter, in order to remove the oxide film 5 grown on the gate portion as shown in (f) (cross section BB in FIG. 4), the P / R 7 is applied except for the portion to be removed around the oxide film 5 ( As in g), the oxide film 5 in the gate portion is removed by wet etching.

따라서, 이와 같이 산화막을 제거시키면서 게이트가 형성될 부분이 오목한 모양이 된다.Therefore, the portion where the gate is to be formed becomes concave while removing the oxide film in this way.

이후, (h)와 같이 P/R(7)을 제거한 후 게이트 형성을 위해 게이트 산화막(8)을 성장시키고 (i)와 같이 폴리실리콘(9)을 디포지션 및 도핑한다.Thereafter, after removing the P / R 7 as shown in (h), the gate oxide film 8 is grown to form a gate, and the polysilicon 9 is deposited and doped as shown in (i).

그리고, (j)와 같이 P/R(10)을 사용하여 폴리시리콘(9)과 게이트 산화막(8)부분중 게이트가 형성될 부분을 제외하고 식각한다.Then, as shown in (j), the P / R 10 is used to etch the portions of the polysilicon 9 and the gate oxide film 8 except for the portion where the gate is to be formed.

또, (k)와 같이 게이트를 마스크로 이용해 n+정션을 형성하기 위한 이온주입을 실시하고 (l)와 같이 저온산화막(11) 디포지션후 액티브 영역과 스토리지 노드를 연결하기 위한 콘택트를 식각한다.In addition, as shown in (k), ion implantation is performed to form n + junction using a gate as a mask, and as shown in (l), the contact for connecting the active region and the storage node is etched after deposition of the low temperature oxide film 11.

이후, 마지막 공정으로 (m)와 같이 폴리시리콘(12)과 유전제(13) 및 폴리시리콘(14)을 차례로 형성하여 커페시터를 형성한다.Thereafter, as a final process, as shown in (m), the polysilicon 12, the dielectric agent 13, and the polysilicon 14 are sequentially formed to form a capacitor.

이와같은 본 발명은 디렘 디바이스 트랜지스터의 게이트가 될 폴리 실리콘(9)을 라운드하게 형성하므로 펀치 스로우 방지와 핫 캐이어 효과 감소를 위해 셀로우 정션을 만들어야 하는 어려운 공정이 필요 없어질 뿐만 아니라 디프(deep) 서브-마이크론 모스 트랜지스터에서 요구되는 이펙티브 채널길이를 효과적으로 증가시킬 수 있는 특징을 갖는다.The present invention rounds the polysilicon 9 that will be the gate of the DRAM device transistor, thus eliminating the need for a difficult process of creating a shallow junction for preventing punch throw and reducing the hot-carrier effect. ) Can effectively increase the effective channel length required in the sub-micron MOS transistor.

Claims (1)

기판(1)에 기본산화막(2)과 질환막(3)을 디포지션하고 P/R(4)에 의해 질화막(3)과 기본산화막(2)을 식각하고 필드산화를 통해 산화막(5)을 형성하여 게이트 부분에 산화막이 자라게 하며 기본 산화막(2)과 질환막(3) 제거후 이온주입하여 n-정션(6)을 형성하고 산화막(5) 주위를 제외한 P/R(7) 도포후 습식식각하므로 산화막(5)을 제거하며 이후 게이트 산화막(8)과 폴리실리콘(9)을 디포지션한후 P/R(10)을 사용하여 게이트가 형성될 부분을 제외하고 식각하며 n+정션을 형성하기 위한 이온 주입후 저온산화막(11), 폴리실리콘(12)(14) 그리고 유전체(13)를 디포지션하여 라운드한 게이트를 형성함을 특징으로 하는 디렘의 트랜지스터 제조방법.The base oxide film 2 and the diseased film 3 are deposited on the substrate 1, the nitride film 3 and the base oxide film 2 are etched by the P / R 4, and the oxide film 5 is removed through field oxidation. To form an oxide film on the gate, remove the basic oxide film (2) and the disease film (3), and ion implantation to form n-junction (6) Since the oxide film 5 is removed, the gate oxide film 8 and the polysilicon 9 are subsequently deposited, and then the P / R 10 is used to etch except for the portion where the gate is to be formed to form n + junction. The method of manufacturing a transistor of the DRAM, characterized by forming a rounded gate by depositing a low temperature oxide film (11), a polysilicon (12), and a dielectric (13) after ion implantation.
KR1019890018833A 1989-12-18 1989-12-18 Dram transistor manufacturing device KR0151121B1 (en)

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KR1019890018833A KR0151121B1 (en) 1989-12-18 1989-12-18 Dram transistor manufacturing device

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KR1019890018833A KR0151121B1 (en) 1989-12-18 1989-12-18 Dram transistor manufacturing device

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KR910013260A KR910013260A (en) 1991-08-08
KR0151121B1 true KR0151121B1 (en) 1998-10-01

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