KR0150498B1 - A semiconductor memory device - Google Patents

Abstract

The present invention eliminates the need to always activate the sense amplifier in the page access mode of the semiconductor memory, and suppresses the current consumption in the sense amplifier.

A semiconductor memory having a page access mode, comprising: a plurality of sense amplifiers 13 for detecting data read out from a plurality of memory cells 10 selected based on row addresses A2 to An, and a plurality of sense amplifiers. A plurality of latch circuits 15 for latching data, means for reading latch data based on page addresses A0 to A1 corresponding to the plurality of latch circuits 16 and 17, and when the row address input is changed. The address transition detection circuit 20 which generates the pulse signals S1 and S3 and generates the pulse signals S2 and S3 when the page address input is changed, controls the activation / deactivation of the sense amplifier using the pulse signals. It characterized in that it comprises a means 30 to.

Description

Semiconductor memory

1 is a block diagram showing a portion of an SRAM according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing one specific example by taking out one set of the sense amplifier, latch circuit, and page selection circuit in FIG.

3 is a circuit diagram showing one specific example by extracting the address transition detection circuit and the sense amplifier control circuit in FIG.

4 is a timing waveform diagram showing an operation example of the address transition detection circuit and the sense amplifier control circuit in FIG.

5 is a block diagram showing a part of an SRAM.

* Explanation of symbols for main parts of the drawings

10: memory cell 11: memory cell array

12: hang decoder 13: sense amplifier

15: latch circuit 16: page selection circuit

17: page decoder 18: output buffer

20: address transition detection circuit 21: first address transition detection circuit

22: second address transition detection circuit 23: third address transition detection circuit

30: sense amplifier control circuit 31 to 34: NAND circuit

BLi, / BLi: Bit line pair I / Oi, / (I / Oi): I / O line pair

BUS: data bus line A2 to An: hang address

A0 to A1: Page mode address PD: Page decode signal

S1: first pulse signal S2: second pulse signal

S3: third pulse signal SE: sense amplifier control signal

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a page mode read control / sense amplifier control circuit in a semiconductor memory device having a page access mode in an SRAM (Static Random Access Memory), a ROM (Read Only Memory), or the like. It is about.

[Traditional Technology and Problems]

Some semiconductor memory devices have a page access mode that enables high-speed access of a specific address. In the read operation of the page access mode, the plurality of rows of data are switched at high speed and outputted by changing the open mode for the page mode in a state in which a plurality of pieces of data of the memory cell array are read in parallel to the sense amplifier. Therefore, the page access mode has a limitation on random access, but can realize a high speed read operation, and is very effective when using a method such as reading data serially.

5 shows a conventional read circuit as an example of an SRAM having a page access mode, for example, in the case of having a 4-bit page mode.

In this SRAM, 10 is a memory cell, 11 is a memory cell array, 12 is a row for selecting memory cells to read data of a plurality of memory cells from the memory cell array 11 according to the row addresses A2 to An. The decoder 13 reads data read from the plurality of selected memory cells to the input / output line pairs I / Oi and / (I / Oi) through each of the bit line pairs BLi and / BLi and the respective column selection circuits 14. A sense amplifier 16 for sensing, 16 is a page selection circuit for selecting data output from the sense amplifier 13 to an output line pair, and 17 is the page selection circuit 16 selected according to the page mode addresses A0 to A1. The page decoder 18 is an output buffer for outputting the data output from the page selection circuit 16 to the data bus line BUS to the output terminal 19.

Next, the read operation in the SRAM will be described.

When reading in the normal access mode, the address signals A0 to An are set, and the 4-bit data selected by the row addresses (normal addresses A2 to An) are read in parallel to the sense amplifier 13, and a double One bit of data is selected and output in accordance with A0 to A1 in the address signal.

When reading in the page access mode, first, address signals A0 to An are set, and in response to the transition of the address signals, four bits of data (page data) are selected in parallel in accordance with the row addresses A2 to An. The sense amplifier 13 is read out, and the data of these bits is selected and output in accordance with the page mode addresses A0 to A1.

Next, the page mode addresses A0 to A1 are changed (transitioned) so that the remaining three bits of data are sequentially selected and sequentially output to the output terminal 19 via the output buffer 18, thereby enabling high-speed readout. .

Further, in the case of continuously reading the page data, the contents of the row addresses A2 to An are changed to select new 4-bit data and read out to the sense amplifier 13 in parallel, and the 1-bit data is read out. The output is selected in accordance with the mode addresses A0 to A1. The page mode addresses A0 to A1 are changed to sequentially select the remaining three bits of data, and are sequentially output to the output terminal 19 via the output buffer 18.

In the conventional read circuit as described above, in the page access mode, it is necessary to keep the sense amplifier 13 always active so that the read data must be in the output state, so that the current consumption of the sense amplifier is large.

The conventional semiconductor memory device as described above has a problem that the sense amplifier must always be activated in the page access mode, so that the current consumption of the sense amplifier is large.

[Purpose of invention]

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor memory device obtained by eliminating the need to always activate a sense amplifier in a page access mode.

[Configuration of Invention]

A semiconductor memory device of the present invention for achieving the above object is based on a memory cell, a memory cell array in which the memory cells are arranged in a matrix, and a first address input for selecting a plurality of memory cells in the memory cell array. A plurality of sense amplifiers for respectively detecting data read from the plurality of selected memory cells, a plurality of latch circuits for respectively latching data from the plurality of sense amplifiers, and a second address input corresponding to the plurality of latch circuits Decoding means for reading latch data from the plurality of latch circuits based on the first data, a first address detection circuit for generating a first pulse signal when the first address input is changed, and the second address input is changed. Second address transition detection circuit for generating a second pulse signal when the signal is generated and the first address transition detection circuit And control means (30) for controlling the activation / deactivation of the sense amplifier by using the first pulse signal generated from the furnace and the second pulse signal generated from the second address transition detection circuit.

[Action]

The control means activates the sense amplifier when only the first address input of the address input is changed or when both the first address input and the second address input are changed, and the sense amplifier is inactive when only the second address input is changed. It is to be controlled to be.

As a result, when the read operation is performed in the page access mode, the sense amplifier is activated to detect data of a plurality of selected memory cells, and after the detected data is latched to the latch circuit, the sense amplifier is inactivated to perform the read operation. The current consumption can be suppressed (disappears from the conventional example).

EXAMPLE

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 shows a read circuit in the case of having a 4-bit page mode as part of an SRAM having a page access mode according to an embodiment of the present invention.

In this SRAM, 10 is a memory cell array, 11 is a memory cell array arranged in a matrix shape, 12 is a plurality of row addresses A2 to An for selecting a plurality of memory cells in the memory cell array. The row decoder 13 for selecting a memory cell is selected from each of the plurality of input / output line pairs (Bi, / BLi) and the column select circuit 14, respectively, from the plurality of memory cells 10 selected by the row decoder. A plurality of sense amplifiers for detecting data read into I / Oi and / (I / Oi)), respectively.

15 is a plurality of latch circuits for respectively latching data output from the sense amplifier 13 to an output line pair, and 16 is data selected from the latch circuit 15 and output to the data bus line BUS. Is a page selection circuit.

17 is page data for reading latch data from the plurality of latch circuits 15, and the page selection circuit 16 is controlled in accordance with the page mode addresses A0 to A1 according to the plurality of latch circuits 15. FIG. A page decode signal PD is outputted. 18 is an output buffer for outputting the data output from the page selection circuit 16 to the data bus line BUS to the output terminal 19.

Furthermore, the sense amplifier 13 is activated by using the address transition detection circuit 20 for generating a pulse signal when the addresses A0 to An are changed and the pulse signal generated from the address transition detection circuit 20. A sense amplifier control circuit 30 for outputting a sense amplifier control signal SE for controlling the deactivation / deactivation to the sense amplifier control signal line is provided.

FIG. 2 is a circuit diagram showing one specific example by taking out one set of the sense amplifier 13, latch circuit 15, and page selection circuit 16 shown in FIG.

In FIG. 2, the sense amplifier 13 includes two CMOS type sense amplifiers 131 and 132 for complementarily detecting data of input / output line pairs I / Oi and / (I / Oi). MOS transistors T1 for activation / deactivation control, which are commonly connected to the two sense amplifiers 13 and controlled by the sense amplifier control signal SE, and respective outputs of the two sense amplifiers 131 and 132 are input. CMOS type sense amplifier 133, and two MOS transistors T2 and T3 for activation / deactivation control connected to the sense amplifier 133.

The latch circuit 15 has two inverter circuits 151 and 152 connected in opposite directions between the pair of output lines connected to the pair of output nodes of the sense amplifier 13.

The page select circuit 16 has MOS transistors T4 and T5 inserted and connected in series to each of the output line pairs and controlled by the page decode signal PD from the page decoder 17.

Further, in this example, two sense bits A0 to A1 of the address signals A0 to An are used as page mode addresses. Is provided, but when the address for the page mode is (A0 to Ai), it is necessary to prepare 2 ⁱ for each of the sense amplifier 13, the latch circuit 15, and the page select circuit 16.

3 is a circuit diagram showing one specific example by taking out the address transition detection circuit 20 and the sense amplifier control circuit 30 in FIG.

In FIG. 3, the address transition detection circuit 20 includes a first address transition detection circuit 21 for generating the first pulse signal S1 when the row addresses A2 to An are changed, and the page. Second address transition detecting circuit 22, the row addresses A2 to An or the page mode address A0 to to generate a second pulse signal S2 when the mode addresses A0 to A1 are changed. One of A1) has a third address transition detecting circuit 23 for generating the third pulse signal S3.

In addition, the third address transition detecting circuit 23 may be configured to logicalize the first pulse signal S1 and the second pulse signal S2.

The sense amplifier control circuit 30 switches the sense amplifier 13 when only the first address input S1 of the address input is changed and when both the first address input S1 and the second address input S2 are changed. It activates and controls so that the sense amplifier 13 may become inactive when only the second address input S2 is changed, and has four NAND circuits 31 to 34, for example.

That is, the first NAND circuit 31 receives the first pulse signal S1 and the third pulse signal S3. The second NAND circuit 32 receives the output signal S4 of the first NAND circuit 31 and the output signal S6 of the fourth second input NAND circuit 34. The third NAND circuit 33 receives the output signal S4 of the first NAND circuit 31, the second pulse signal S2, and the third pulse signal S3. The fourth NAND circuit 34 receives the output signal S5 of the third NAND circuit 33 and the output signal of the second NAND circuit 32 (sense amplifier control signal output SE).

Here, the operation of the address transition detection circuit 20 and the sense amplifier control circuit 30 in FIG. 3 will be described with reference to the timing waveform diagram shown in FIG.

Now, when the row addresses A2 to An and the page mode addresses A0 to A1 are simultaneously transitioned, the second address signal S2 and the second address transition detection circuit 22 are transmitted from the first address transition detection circuit 21. From the second pulse signal S2 and the third address transition detection circuit 23, the third pulse signal S3 is generated. As a result, the control signal output SE of the sense amplifier control circuit 30 becomes H level, thereby activating the sense amplifier 13.

Further, when only the page mode address signals A0 to A1 are transitioned, the second pulse signal S2 from the second address transition detection circuit 22 and the second pulse signal (from the third address transition detection circuit 23) are used. S2) occurs. As a result, the control signal output SE of the sense amplifier control circuit 30 becomes L level, and the sense amplifier 13 is made inactive.

When only the row addresses A2 to An are transitioned, the first pulse signal S2 is generated from the first address transition detection circuit 21 and the third pulse signal S3 is generated from the third address transition detection circuit 23. do. As a result, the control signal output SE of the sense amplifier control circuit 30 becomes H level again, and activates the sense amplifier 13.

Next, the read operation in the SRAM will be described.

When reading in the normal access mode, the address signals A0 to An are set, and the four bits of data selected by the row addresses (normal addresses A2 to An) are read out to the sense amplifier 13 simultaneously. In this case, since only the row addresses A2 to An are transitioned, only the pulse signal S1 is generated or the row addresses A2 to An and the page mode addresses A0 to A1 are simultaneously transitioned. S3) occurs and the sense amplifier control circuit 30 controls to activate the sense amplifier 13.

As a result, four bits of data are detected by the sense amplifier 13, and the detected data is latched by the latch circuit 15... Select and output according to A0 to A1 in An).

When reading in the page access mode, first, the address signals A0 to An are set, and the 4-bit data (page data) is selected in accordance with the row addresses A2 to An in response to the transition of the address signals. Read until (13). In this case, since only the row addresses A2 to An transition, the pulse signals S1 and S3 are generated and the sense amplifier control circuit 30 controls the sense amplifier 13 to be activated.

As a result, the page data is detected by the sense amplifier 13, and the detected page data is latched by the latch circuit 15, and double 1-bit data is stored in accordance with the page mode addresses A0 to A1. It is selected and output.

Subsequently, when only the page mode addresses A0 to A1 are changed, the pulse signals S2 and S3 are generated so that the sense amplifier control circuit 30 deactivates the sense amplifiers 13... It is possible to control and sequentially select and output the page data latched by the latch circuit 15 in accordance with the page mode addresses A0 to A1.

This enables high-speed readout at the time of page address selection and suppresses the current consumption of the sense amplifier 13 (disappears from the conventional example). Further, in the case of continuously reading the page data, the sense amplifier control circuit 30 causes the sense amplifier 13 to shift only the row addresses A2 to An or the row addresses A2 to An and the page addresses A0 to A1. ) To activate. As a result, the data of the input / output line pairs I / Oi and / (I / Oi) are detected by the sense amplifier 13, and the detected page data is latched by the latch circuit 15 so that the data is stored in the page address. Data can be read.

Further, the present invention is not limited to the SRAM of the above embodiment, but can also be applied to other semiconductor memories having a page access mode in ROM. On the other hand, the reference numerals in the drawings which are changed in each component requirement of the claims of the present application to facilitate the understanding of the present invention, not intended to limit the technical scope of the present invention to the embodiments shown in the drawings. .

[Effects of the Invention]

As described above, according to the present invention, it is not necessary to always activate the sense amplifier in the page access mode, and the current consumption in the sense amplifier can be suppressed.

Claims (2)

Selected based on a memory cell 10, a memory cell array 11 in which the memory cells 10 are arranged in a matrix, and a first address input for selecting a plurality of memory cells in the memory cell array 11; A plurality of sense amplifiers 13 for respectively detecting data read out from the plurality of memory cells, a plurality of latch circuits 15 for latching data from the plurality of sense amplifiers 13, and a plurality of latch circuits ( Decoding means 16 and 17 for reading latch data from the plurality of latch circuits based on the second address input corresponding to 15), and a first pulse signal for generating a first pulse signal when the first address input is changed. A first address transition detection circuit 21, a second address transition detection circuit 22 for generating a second pulse signal when the second address input is changed, and a first address generated from the first address transition detection circuit; Scan signal and a second address transition by using the second pulse signal generated from the detecting circuit, characterized in that the semiconductor memory device is configured with a control means 30 for controlling the activation / deactivation of the sense amplifier. The method of claim 1, wherein the control means 30 is a sense amplifier when both the first address input and the second address input is changed when only the first address input of the first address input and the second address input is changed. (13) is activated and the sense amplifier 13 is controlled to be inactive when only the second address input is changed.