KR0150106B1 - Monitoring circuit and method of wafer - Google Patents

Abstract

The present invention relates to a wafer verification circuit and a verification method. Since the array mode and the random mode used in the wafer verification equipment can be executed at the same time, it becomes possible to measure a Peri region, which is a problem when only the array mode is used. The present invention also relates to a wafer verification circuit and a method for verifying the same, wherein the measurable scanning area, which is a problem when using only the random mode, is solved to improve cell sensitivity.

Description

Wafer Verification Circuit and Its Verification Method

The accompanying drawings are a wafer verification circuit diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

1: Array Program Setup Mode 2: Array Image Computer

3: random image computer 4: random program setup mode

5: coprocessor enable terminal 6: coprocessor

7: verification unit 8: read signal unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer inspection circuit and an inspection method, in particular, a wafer verification circuit capable of simultaneously executing an array mode and a random mode used in a wafer verification apparatus. And a verification method thereof.

In general, the scanning method of the wafer verification equipment KAL is divided into an array mode and a random mode. The array mode is a mode that can be used only when there are repeated patterns of the same size in the scanning area. The random mode refers to a mode in which one scanning area is caught and measured in a die. However, in the conventional wafer verification method, the two modes (array mode and random mode) may be used independently of each other. When only the array mode is used, it is impossible to measure a peri area in addition to the cell. When only the random mode is used, there is a burden because the scanning area that can be measured is limited, and if the scanning area is wider, the sensitivity of the cell is relatively lowered, which lowers the verification efficiency.

Accordingly, an object of the present invention is to provide a wafer verification circuit and a verification method that can solve the above-mentioned disadvantages by enabling simultaneous execution of the array mode and the random mode used in the wafer verification equipment.

The present invention for achieving the above object is an array program setup mode and a random program setup mode for performing programming, and the output signal of the coprocessor enable terminal as input, respectively, the array program setup mode and random program setup mode An array image computer and a random image computer for storing respective information on the wafer surface according to the programming of the readout signal, a read signal unit connected between the output terminals of the array image computer and the random image computer, the array image computer and the random image computer And a coprocessor operated according to an output signal of the coprocessor enable terminal, and a verification unit configured to input output data of the coprocessor.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

The accompanying drawings are a wafer verification circuit diagram according to the present invention, an array program setup mode (1) and a random program setup mode (4) and a coprocessor An array image for storing the respective information on the wafer surface according to the programming of the array program setup mode (1) and the random program setup mode (4) as inputs to the output signals of the coprocessor enable terminal (5). A read signal unit connected between an array image computer 2 and a random image computer 3 and output terminals of the array image computer 2 and the random image computer 3; 8) and data of the array image computer 2 and the random image computer 3 as inputs, respectively, in accordance with the output signal of the coprocessor enable terminal 5. Small co-processor which (Coprocessor; 6) and the nose verify that the output data as input to the processor 6 unit; when describing the operation of the verification circuit wafer consisting of (Inspection station 7) as follows.

Array mode and random mode can be used as each individual mode. For example, when the array mode is operated, when programming is performed in the array program setup mode 1, respective information about the wafer surface is stored in the array image computer 2. At this time, when reading is performed, each information is input to the coprocessor 6. At this time, the data of the random image computer 3 on the random mode side is inverted by the inverter G2 of the read signal section 8. Therefore, the data of the random image computer 3 is blocked. Eventually, the coprocessor 6 is operated by the data of the array image computer 2. On the contrary, when the random mode is operated, the data of the array image computer 2 on the side of the array mode is inverted by the inverter G1 of the read signal unit 8. Therefore, the data of the array image computer 2 is blocked. The output signal of the read signal section 8 is output as flip-flop signals opposite to each other. Meanwhile, when the array mode and the random mode are used at the same time, the coprocessor enable terminal 5 is enabled to directly control the coprocessor 6. When the enable signal is generated from the coprocessor enable terminal 5, the read signal unit 8 is disabled. The programmed data in each of these modes is stored in respective image computers 2 and 3, and then the coprocessor enable terminal 5 is enabled and simultaneously input into the coprocessor 6. In the coprocessor 6, the two data are combined and output to the verification unit 7. The verification unit 7 sets and verifies hardware. That is, the array mode and the random mode can be used simultaneously according to the output signal of the coprocessor enable terminal 5.

As described above, according to the present invention, it is possible to simultaneously execute the array mode and the random mode used in the wafer verification equipment, thereby making it possible to measure a Peri region, which is a problem when only the array mode is used, and the random mode. The measurable scanning area, which is a problem when using only, is solved, and the sensitivity of the cell is improved, which is excellent in improving the verification efficiency.

Claims (3)

In the wafer verification circuit, an array program setup mode and a random program setup mode for performing programming and an output signal of the coprocessor enable terminal are input as inputs, and according to the programming of the array program setup mode and the random program setup mode. An array image computer and a random image computer for storing respective information on the wafer surface, a read signal unit connected between output terminals of the array image computer and the random image computer, and data of the array image computer and the random image computer, respectively. And a verification unit configured as an input and operating according to an output signal of the coprocessor enable terminal, and a verification unit configured to input output data of the coprocessor. 2. The wafer verification circuit according to claim 1, wherein the read signal section comprises a pair of inverters connected alternately. In the wafer verification method, the coprocessor enable terminal is enabled to directly control the coprocessor, and when the enable signal is generated from the coprocessor enable terminal, the read signal unit is disabled, respectively The programmed data is stored in each image computer so that the coprocessor enable terminal is enabled and input to the coprocessor. In the coprocessor, the two data are combined and output to the verification unit. Wafer verification method characterized in that the verification unit to set the hardware to verify using the array mode and the random mode at the same time.