KR0147642B1 - Method for forming fine pattern of semiconductor device - Google Patents

Abstract

In the method of forming a micropattern using a multilayer resist in the stepped portion, a thick layer of a resist without a sensitizer is formed in the stepped portion to be flattened, and the bottom layer resist is baked, and then the upper layer resist is thinned ( thin). After exposing on the upper resist, the upper resist and the lower resist are simultaneously developed at the time of development to develop the lower resist in the upper resist pattern. Finally, the pattern of the exposed semiconductor substrate is formed using the developed resist as a mask. Accordingly, the present invention can form a fine pattern even when the underlying medium has severe reflection of light, and further simplify the process, and can form a fine pattern by maintaining a constant depth of focus during exposure in a stepped area. .

Description

Method of forming fine pattern of semiconductor device

1A and 1B are cross-sectional views for explaining a method of forming a pattern of a stepped portion by a conventional multilayer resistor method.

2A to 2C are cross-sectional views showing a method of forming a fine pattern of a stepped portion according to the present invention.

3 is a photograph of a state in which the lower layer resist formed thick according to the present invention is developed simultaneously with the upper layer resist pattern.

(a) is a flat picture,

(b) shows a vertical cross section

(c) shows the cross section photograph tilted at 45 degree angle, respectively.

The present invention relates to a method for forming a micropattern, and more particularly, to a method for forming a micropattern using a multilayer resist in a stepped portion.

As is well known, as the degree of integration of semiconductor devices increases rapidly, it becomes more important to accurately form patterns having extremely fine sizes. Therefore, it becomes very important to use photolithography more precisely to form a fine pattern.

However, if the substrates under the conductive and insulating layers are uneven, stepped or uneven, the accuracy of pattern formation is reduced and it is very difficult to form fine patterns accurately. The reason for this is that, first, when light is incident on the resist, the light is exposed to a portion that is not originally incident due to the reflection of the incident light due to the inclined slope from the stepped portion of the substrate, thereby degrading the resolution. Second, due to the interference effect, because the interference phenomenon cannot be easily adjusted due to the large difference in the thickness of the photoresist film in the stepped portion, the accuracy of pattern formation is reduced due to the interference between the incident light and the reflected light.

On the other hand, the depth of focus becomes a problem when trying to form a pattern at the stepped portion of the semiconductor manufacturing process at the same time. As the numerical aperture (NA) of the exposure equipment increases, the depth of focus

By getting smaller.

Therefore, as the pattern becomes finer, it becomes more difficult to form the pattern in the stepped portion. In order to solve this problem, the planarization process is preceded by a thin resist thereon.

As a method for solving the problem when the substrate surface is uneven or stepped as described above, it is common to use the 'Multi Layer Resist Method' disclosed in Japanese Patent Application Laid-Open Nos. 107,775 and 107,776. According to this method, when there is a bumpy part or a stepped part on the semiconductor substrate, a thick organic film (lowest layer) is first applied evenly on the film to be processed. Next, a thin film (intermediate layer) using spin on glass (SOG), phospho-silicate glass (PSG), or SiO 2 is formed thereon. And a thin photoresist film (top layer) is formed into a thin film thereon. Therefore, the top layer is exposed to light using a conventional photolithography technique and then developed to form the desired shape by etching the intermediate layer. Thereafter, the exposed portions of the thickest lowermost layer are removed by dry etching using the pattern of the intermediate layer as a mask. The exposed portion of the semiconductor substrate to be patterned is removed by etching to form a desired pattern.

The reason for applying the resistor in multiple layers is to prevent the interference effect in the above-mentioned resist film, and to prevent the light reflected from the stepped portion from absorbing in the lowermost layer or the middle layer and not reaching the uppermost photoresist layer so that the fine pattern can be accurately To form.

FIG. 1A and FIG. 1B are process cross-sectional views showing a step process with a step by the conventional method.

Specifically, the aluminum (A1) film quality 3 is formed on the semiconductor substrate 1 having the stepped surface. A thick organic layer (lowermost layer 5) is applied on the semiconductor substrate to be patterned so that a process, ie, an etching process, may be performed on the film quality. Next, a thin layer (middle layer: 7) using SOG (Spin On Glass), PSG (Phospho Silicate Glass), SiO 2, etc. is formed thereon. Then, a thin photoresist (top layer 9) is formed into a thin film thereon. Therefore, the top layer 9 is exposed and developed by a conventional photolithography technique, and the intermediate layer 7 is etched to form a desired shape 7a. Thereafter, the exposed portion of the thick lowermost layer 5 is removed by dry etching using the pattern of the intermediate layer as a mask. The exposed portion of the semiconductor substrate to be patterned is removed by etching to form a desired pattern.

As described above, the reason for applying the resist in multiple layers is to prevent the interference effect of the resist as mentioned above, and to prevent the light reflected from the stepped portion from absorbing in the lowermost layer or the middle layer to prevent reaching the uppermost photoresist, thereby precisely forming a fine pattern. To do that.

However, in the multilayer resist method, the characteristics and interactions of each of the lowermost layer, the middle layer, and the uppermost layer of the resist were not sufficiently investigated, and above all, the complexity of the process due to the three-layer structure was a major obstacle.

Accordingly, the present invention has been made to solve the above-described problems, and an object thereof is to provide a method of forming a fine pattern of a semiconductor device in which a process can be simplified and a pattern can be formed more accurately at a stepped portion.

In order to achieve the above object, the present invention provides a flat layer by forming a resist without a sensitizer in a stepped portion in the semiconductor manufacturing process, and baking the resist, and then thinning the upper layer resist. After the exposure, the two resists are developed simultaneously.

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.

In order to simplify the process, the present invention is flattened by applying a thick resist-free resist. In photoresist, polymers and resins receive energy and polymers in the state where the solvent and the monomers that determine the viscosity of the resist are combined in the thousands. There is a sensitizer called Photo Active Compound (PAC) to deliver. However, in the present invention, a resist that is dissolved in a developer even without a sensitizer is used as a lower layer planarization film and an upper layer resist is formed thereon. At this time, since poor formation occurs due to a mutual reaction between the lower layer and the upper layer resist, it uses a method of baking and treating the lower layer resist at 130 to 145 ° C.

FIG. 2A is a cross-sectional view of a resist-free resist formed on the stepped portion and planarized according to the procedure of the present invention. Specifically, the aluminum (A1) film quality 13 is formed on the semiconductor substrate 11 having the stepped surface. A thick organic layer (lowest layer 15) is formed flat on the film so that a process, that is, an etching process, may be performed on the film.

2B is a cross-sectional view of the upper layer resist 19 applied after baking the lower layer resist 15a. Therefore, the photoresist layer 19 is exposed to light using a conventional photolithography technique and then developed to form a desired shape.

FIG. 2C is a cross-sectional view of a state in which a resist pattern is developed at a stepped portion in a state in which the upper resist 19a and the lower resist 15b are formed simultaneously after exposure. In this state, the exposed portion of the semiconductor substrate to be patterned is removed by etching to form a desired pattern.

On the other hand, during the post-exposure development of the thinly formed upper layer resist, the state in which the thickly formed lower layer resist is simultaneously developed in the upper layer resist pattern may be supported by the attached photograph 3rd. That is, FIG. 3A shows a planar photograph, FIG. 3B shows a vertical section photograph, and FIG. 3C shows a tilted section photograph at a 45 ° angle.

As described above, according to the present invention, a reproducible pattern is formed even when light is severely reflected in a sub-material when forming a fine pattern in a stepped portion, and in particular, a selectivity ratio between the semiconductor substrate to be patterned and the resist is small. Even the correct pattern is formed. In addition, the process is simplified, and the depth of focus is constant at the time of exposure in the stepped area to form a fine pattern, and as a thick mask, the sub-film quality is more accurately patterned. Can be formed.

Claims (3)

Forming a fine pattern on a stepped portion of the semiconductor device, the step of forming a lower layer resist-free resist on the semiconductor substrate to be patterned to planarize the stepped portion; Forming an upper resist containing a photoresist on the lower resist; And exposing and developing the resultant to form a fine pattern. The method of claim 1, further comprising baking the lower layer resist at 130 to 145 ° C. after the knitting process. The method of claim 1, wherein in the forming of the pattern, upper and lower resists are simultaneously developed.