KR0147617B1 - Decoder for inverse scan and run length code using memory address of dct - Google Patents

Abstract

The present invention discloses an inverse scan and run-length decoding apparatus using memory addressing of an inverse quantization unit. In the inverse quantization unit which inputs a run signal, a code signal and a coefficient value and outputs a discrete cosine transform (hereinafter, referred to as DCT) coefficient in the moving picture encoding apparatus, the device accumulates and stores the run signal and increases the address by the accumulated number. Address control means for generating a first control signal, scan table means for storing the addresses in the reverse order of the DCT coefficients being scanned in the video encoding apparatus, and outputting the addresses in the order controlled and stored in the first control signal, and scanning A quantization table means for controlling the output of the table means to output quantization matrix values, coefficient decoding means for inputting a code signal, a coefficient value and a quantization matrix value to decode DCT coefficients, outputting coefficients of the DCT block, and In order to perform length decoding, padding is carried out by a predetermined number before input and control of the output of the scan table means. And an output buffer means for storing the output of the coefficient coefficient decoding means. Since the address is stored in the scan table portion inversely, the reverse scanning process is automatically performed by reading the address and outputting the address to the quantization table portion. In addition, there is an effect of performing run-length decoding by adjusting the input of the output buffer in the address controller without the need for a separate circuit for run-length decoding.

Description

Reverse scan and run-length decoder using memory addressing of inverse quantizer

FIG. 1A is a table showing a reverse scan table in one reverse scan method. FIG.

1B is a table showing a reverse scan table in another reverse scan scheme.

2 is a block diagram illustrating an inverse scan and run-length decoding apparatus using memory addressing of an inverse quantization unit according to the present invention.

3 is a block diagram of inverse scan and run-length decoding using memory addressing according to the present invention for explaining the decoding apparatus shown in FIG. 2 in detail.

FIG. 4A is a table showing a scan table stored in the first scan table unit shown in FIG.

FIG. 4B is a table showing a scan table stored in the second scan table portion shown in FIG.

5 is a circuit diagram for explaining a preferred embodiment of the inverse scan and run-length decoding apparatus using the memory addressing of the inverse quantization unit according to the present invention.

The present invention relates to a video decoding apparatus, and more particularly, to an apparatus for performing inverse scan and run-length-decoding (RLD) using memory addressing of an inverse quantization unit in the apparatus. .

Moving Picture Expert Group (MPEG) 2, the international standard for video compression, was released in April 1994. It is a specification for moving picture compression and decompression, and several companies are working to make it possible. Digital video signal compression is increasing in many applications such as digital image data transmission and digital image storage.

When encoding image information, the image information is 8 × 8 Discrete Cosine Tranform (DCT: DCT), compressed by the quantization unit, and then read in a Zig-Zag method (scan). Are converted to dimensions. As a result of being read in a zigzag manner, the image information is arranged by frequency size, so that the high frequency component is almost '0', and thus the run signal and the value encoded by the run value indicating the number of consecutive '0's are encoded. This increases the compression effect of the length encoder.

It is an object of the present invention to perform inverse scan and run-length using memory addressing of an inverse quantizer to perform inverse scan and run-length-decoding functions by addressing quantization matrix values stored in a memory using a run signal input to a decoder. It is to provide a decoding device.

In order to achieve the above object, an inverse scan and run-length decoder using memory addressing of an inverse quantizer according to the present invention inputs a run signal, a code signal, and a coefficient value in a moving picture encoding apparatus to output a discrete cosine transform coefficient. And address control means for generating a first control signal for accumulating and storing the run signal after inputting the run signal, and in the reverse order of scanning the discrete cosine transform coefficients in the video encoding apparatus. Scan table means for storing addresses and outputting addresses in an order stored and controlled by a first control signal, quantization table means controlled at the output of the scan table means for outputting quantization metrics values, the code signal and the coefficients Discrete cosine transform coefficients by inputting a value and the quantization matrix Coefficient decoding means for outputting the coefficients of the discrete cosine transform block and outputting the coefficients of the discrete cosine transform block and padding with a predetermined number before input and controlling the coefficient decoding by controlling the output of the scan table means. And output buffer means for storing the output of the means.

FIG. 1A is a table showing a reverse scan table in one reverse scan method. FIG.

1B is a table showing a reverse scan table in another reverse scan scheme.

2 is a block diagram illustrating an inverse scan and run-length decoding apparatus using memory addressing of the inverse quantization unit according to the present invention, and includes a coefficient decoding unit 200, an address control unit 202, a scan table unit 204, It consists of a quantization table section 206 and an output buffer 208.

3 is a block diagram of an inverse scan and run-length decoding apparatus using memory addressing according to the present invention for explaining the decoding apparatus shown in FIG. 2 in detail, and includes a coefficient decoding unit 200 and an address control unit 202. The first scan table 400, the second scan table 402, the first selector 404, and the quantization table 206 constituting the output buffer 208, the scan table 204. The first quantization table unit 406, the second quantization table unit 408, and the second selection unit 410 are configured.

4A is a table illustrating a scan table stored in the first scan table 400 shown in FIG. 3.

FIG. 4B is a table showing a scan table stored in the second scan table portion 402 shown in FIG.

Hereinafter, operations of the inverse scan and run-length decoding apparatus using the memory addressing of the inverse quantization unit according to the present invention will be described in detail with reference to FIGS. 1A-1B, 2, 3, and 4A-4B. do.

The scan table unit 204 shown in FIG. 2 includes a first scan table unit 400 for storing an address corresponding to a first scan method controlled and output by a first control signal generated by the address controller 202. Similarly, the second scan table unit 402 for storing an address corresponding to the second scan method controlled and output to the first control signal and the second control signal input through the input terminal IN3 are controlled to be the first or the second. The first selection unit 404 selects and outputs values of addresses stored in the two scan table units 400 and 402, and the quantization table unit 206 controls the third control signal input through the input terminal IN5. The first quantization table unit 406 for inputting the quantization matrix from the moving picture encoding apparatus through the input terminal IN4, and storing and controlling the output of the first selection unit 404 to output the quantization matrix to the second selection unit 410. ) And the first selector 404 A second quantization table unit 408 which is controlled by an output and outputs a quantization matrix internally stored in advance to the second selection unit 410, and is controlled by a fourth control signal input through the input terminal IN6, thereby controlling the first or second The second selector 410 selects and outputs the quantization matrices stored in the quantization table units 406 and 408 to the coefficient decoding unit 200.

The signals read in the video encoding apparatus in a zigzag manner are read in the same order as those in FIGS. 1a and 1b by the decoder (inverse scan), so that the zigzag matrix can be replaced with the original 8 × 8 signal array.

The coefficient decoding unit 200 shown in FIG. 2 decodes the AC (hereinafter referred to as AC) and DC (hereinafter referred to as DC) coefficient values of the DCT block by using the 12-bit encoded value input through the input terminal IN1. Output the count value.

The address control unit 202 shown in FIGS. 2 and 3 accumulates as many run lengths as the number of consecutive '0' input through the input terminal IN2 and generates the first control signal. In this case, the address values stored in the first and second scan table units 400 and 402 are stored in the reverse order of the addresses corresponding to the coefficients scanned by the code unit, and the stored addresses are controlled by the first control signal. The reverse scan is automatically performed by outputting to the quantization table unit 206. The first and second scan table portions 400 and 402 shown in FIG. 3 constituting the scan table portion 204 to perform the functions of the reverse scan and the run-length decoder are implemented in ROM. The first scan table 400 stores the values corresponding to each address of the scan table in one scan method in the order as shown in FIG. 4a, and the second scan table 402 in FIG. 4b. A value corresponding to each address of the scan table in another scan method is stored in the order as shown in the figure, and is controlled by a second control signal input to the input terminal IN3 and outputted from the first selector 404. One is selected and input to the first and second quantization table units 406 and 408.

In the International Standard (IS) 13618-2, the address transmitted to the first quantization table section 406 is always the scan method shown in FIG. 4A.

The signal output from the first selector 404 controls the first and second quantization table units 406 and 408 to output the quantization matrix stored therein.

On the other hand, the output buffer 208, which may be implemented as RAM, pads the memory to a value of '0' before accepting an input, and firstly selects the first selection unit 404 in the scan table unit 204. In response to the output of n), the output of the coefficient decoding unit 200 is input to perform run-length decoding. After performing run-length decoding, the output buffer 208 outputs the coefficients of the DCT block.

The process of performing run-length decoding will be described in detail as follows.

'0' should be input to the output buffer 208 for as many runs as the number of consecutive '0's, but since' 0 'is padded in advance, it is not necessary to input' 0 'and the coefficient decoding unit 200 When the AC and DC coefficient values are inputted, the signal output from the first selector 404 for controlling the output of the first and second quantization table parts 406 and 408 is increased by the address accumulated in the run signal. By using the input control signal of the output buffer 208, which is designed to fill it with '0', and temporarily storing the coefficient values in the output buffer 208, it can be seen that run-length decoding is automatically performed using memory addressing. Can be.

5 is a circuit diagram illustrating a preferred embodiment of an inverse scan and run-length decoding apparatus using memory addressing of the inverse quantization unit according to the present invention, and includes a decoder 600, an address selector 602, and a first ROM ( ROM) 604, a first RAM 606, a second ROM 608, a third ROM 610, a multiplexer 612, and a second RAM 614.

Hereinafter, an operation of a preferred embodiment of the inverse scan and run-length decoding apparatus using the memory addressing of the inverse quantization unit according to the present invention will be described with reference to FIG.

In the inverse quantizer which inputs the coefficient value, the run signal, and the code signal from the moving picture encoding apparatus, respectively, and outputs a discrete cosine transform coefficient, the run signal is input and accumulated through the input terminal IN2 shown in FIG. An address selector 602 for generating a first control signal for increasing the number of addresses by a predetermined number; and storing the address in an order opposite to the order of scanning the discrete cosine transform coefficients in a moving picture encoding apparatus, The first ROM 604 outputs an address in response to the control signal, and the quantization matrix is input from the video encoding apparatus through the input terminal IN4 in response to the second control signal input through the input terminal IN5. The first RAM 606 outputs in response to the output of the 604, the second ROM 608 internally stores the quantization matrix and outputs in response to the output of the first ROM 604, and the constant quantization. The input shown in FIG. 5 after inputting the quantization metrics stored in the third ROM 610 and the third ROM 610, the second ROM 608, or the first RAM 606, respectively, storing the 16 value. A multiplexer 612 which selects and outputs in response to the third control signal input through the terminal IN6, and inputs a coefficient value, a code signal, and an output of the multiplexer 612, which are input to the input terminal IN1 shown in FIG. Decoder 600 for decoding the discrete cosine transform coefficients, and padding with a predetermined number internally to perform run-length decoding and outputting the decoder 600 in response to the output of the first ROM 604. And a second RAM 614 for outputting the discrete cosine transform coefficients.

The first ROM 604 includes a first scan ROM storing scan tables in an order opposite to the first scan method of scanning a discrete cosine transform coefficient in a moving picture encoding apparatus, and a first scan ROM storing a discrete cosine transform coefficient in a moving picture encoding apparatus. Selection means for controlling and selecting and outputting the second scan ROM storing the scan table in the reverse order of the two scan method, and the fourth control signal inputted to the input terminal IN3 by inputting the outputs of the first and second scan ROMs; It consists of.

On the other hand, the address selector 602 shown in FIG. 5 terminates the input of the run signal when the E.O.B.:End Of Block signal is input through the input terminal IN2.

A third control signal input through the input terminal IN6 shown in FIG. 5 controls the multiplexer 612 as follows.

The third control signal includes a first signal that is an intra-quantization matrix load signal, a second signal that is a non-intra-quantization matrix load signal, and a third signal that is a macro block intra load signal. have.

When the first, second and third signals of the third control signal are at a low level, the quantization matrix of the third ROM 610 in which the constant quantization matrix value 16 is stored is decoded by the multiplexer 612. When the first and second signals of the third control signal is low level and the third signal is high level, the quantization matrix stored in the second ROM 608 as a default is decoded through the multiplexer 612. Is outputted at 600.

The third control signal is generated in the order according to the combination of the run signal and the output signal of the first ROM 604, and the quantization matrixes sent from the moving picture encoding apparatus are transmitted to the decoder 600 through the multiplexer 612.

As described above, since the address is stored in the scan table 204 in reverse, the reverse scan process is automatically performed by reading the address and outputting the address to the quantization table, and a separate circuit for run-length decoding is provided. There is an effect of performing run-length decoding by simply inputting the decoded coefficients input from the coefficient decoding unit 208 by adjusting the input of the output buffer 208 in the address control unit 202 without the need.

Claims (5)

The inverse quantizer which inputs a run signal, a code signal, and a coefficient value to output a discrete cosine transform coefficient in a moving picture encoding apparatus, generates a first control signal for increasing the address by the accumulated number after inputting the run signal. An address control means for storing the address in reverse order of scanning of the discrete cosine transform coefficients in the moving picture encoding apparatus, and scan table means for outputting the addresses in an order stored and controlled by a first control signal; Quantization table means for controlling the output of the table means and outputting quantization matrix values, coefficient decoding means for inputting the code signal, the coefficient value and the quantization matrix value to decode discrete cosine transform coefficients, and the discrete cosine transform block Before input to output coefficients of and perform run-length decoding. And an output buffer means padded by a predetermined number at a predetermined number and controlled by an output of the scan table means to store an output of the coefficient decoding means. Length decoder. 2. The apparatus of claim 1, wherein the scan table means comprises: first scan table means for storing an address corresponding to a first scan method controlled and output to the first control signal; Second scan table means for storing an address corresponding to a second scan method controlled and output by the first control signal; And a first selecting means controlled by a second control signal to select and output values of addresses stored in the first or second scan table means. The reverse scan and the run-length using the memory addressing of the inverse quantization unit. Decryptor. 3. The apparatus according to claim 1 or 2, wherein the quantization table means is controlled by a third control signal to input quantization metrics from the video encoding apparatus, and is stored and controlled by an output of the first selection means to output the quantization metrics. First quantization table means; Second quantization table means which is controlled by an output of the first selection means and outputs internally stored quantization metrics; And a second selection means controlled by a fourth control signal to select and output quantization matrices stored in the first or second quantization table means. Inverse scan and run-length decoding using memory addressing of the inverse quantization unit Device. A dequantizer for inputting a coefficient value, a run signal, and a code signal from a moving picture encoding apparatus, respectively, and outputting a discrete cosine transform coefficient, wherein the first control signal accumulates after the run signal and increases an address by the accumulated number. Generating address selection means; A first ROM storing the address in an order opposite to the order of scanning the discrete cosine transform coefficients in the moving picture encoding apparatus, and outputting the address in response to the first control signal; A first RAM configured to input a quantization matrix from the video encoding apparatus in response to a second control signal and output the quantization matrix in response to an output of the first ROM; A second ROM internally storing the quantization matrix and outputting the quantization matrix in response to an output of the first ROM; A third ROM storing a constant quantization matrix value; A multiplexer configured to select and output the quantization metrics stored in the third ROM, the second ROM, or the first RAM, respectively, in response to a third control signal; A decoder which decodes the discrete cosine transform coefficient by inputting the coefficient value, the code signal and the output of the multiplexer; In order to perform run-length decoding, a second RAM which is padded internally by a predetermined number and inputs the output of the decoder in response to the output of the first ROM to output the discrete cosine transform coefficients. An inverse scan and run-length decoder using memory addressing of the inverse quantization unit. 5. The apparatus of claim 4, wherein the first ROM comprises: a first scan ROM storing scan tables in a reverse order to a first method of scanning a discrete cosine transform coefficient in the video encoding apparatus; A second scan ROM storing a scan table opposite to a second method of scanning the discrete cosine transform coefficients in the video encoding apparatus; And a selection means for inputting the outputs of the first and second scan ROMs to control and select and output the fourth control signal. The reverse scan and run-length decoding apparatuses using the memory addressing of the inverse quantization unit are provided.