KR0146111B1 - Aspect ratio converter - Google Patents

Abstract

The present invention relates to a screen aspect ratio converting apparatus, which is configured to record / read a single clock into two line memories when a 4: 3 video signal or a 2: 1 cinema video signal is received by a 16: 9 wide television receiver. To simplify the hardware as a whole.

The present invention as described above comprises clock generation means for generating a clock each time the horizontal synchronization signal is input; Clock counting means for counting a clock of the clock generating means to generate a first write enable signal; Coefficient control means for generating a first read enable signal, a second write enable signal, and a coefficient control signal of a predetermined bit with a clock of the clock generation means according to horizontal compression and horizontal extension; First line memory means for recording / reading every line in synchronization with a clock of a clock generating means in accordance with the first write enable signal and the first read enable signal; Sample interpolation means for interpolating between 4: 3 or 7: 8 image data of said first line memory means and previous image data; And a second line memory means for recording and outputting image data of the sample interpolation means every line according to the second write enable signal and the set second read enable signal.

Description

Screen aspect ratio inverter

1 is a block diagram of a horizontal compression / expansion device of a conventional TV screen

FIG. 2 is a screen state diagram of compressed / extended video signals according to FIG.

(a) is a horizontal compressed screen state diagram of a 4: 3 signal.

(b) is a horizontal state diagram of a cinema signal

3 is a block diagram of the present invention TV screen horizontal compression / expansion device

4 is a configuration diagram showing in more detail the coefficient control unit of FIG.

FIG. 5 is a diagram illustrating the sample interpolator of FIG. 3 in more detail.

6 is a table showing coefficient control signals and write / read enable signals by the output of the counter of FIG.

7 shows an example of 4: 3 sample interpolation according to FIG.

8 is an illustration of a 7: 8 sample interpolation process according to FIG.

9 is a configuration diagram of another embodiment of the sample interpolator of FIG.

10 is another embodiment of the present invention TV screen horizontal compression / expansion device

11 is another embodiment configuration of the TV screen horizontal compression / expansion device by the sampling or duplication of the present invention

* Explanation of symbols for main parts of the drawings

200: first video input terminal 201: first synchronous input terminal

202: first clock generator 203: first clock counter

204: coefficient control unit 205: first line memory unit

206: first sample interpolator 207: second line interpolator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to screen aspect ratio conversion in television receivers, and more particularly to 4: 3 video signals or 2: 1 cinema (HD) screens in wide screen television receivers having an aspect ratio of 16: 9. A screen aspect ratio converting apparatus for changing a scanning player on a screen when a signal is received so that a 4: 3 video signal is horizontally compressed and a 2: 1 cinema signal is horizontally stretched and displayed.

In general, in the NTSC broadcasting system and the PAL broadcasting system, the letter box form blacks the upper, lower, left, and right sides of the screen by using 3/4 of the original active video section (effective video section) as a low-pass video. That is, the image is transmitted in the form of letterbox.

This is to transmit a 16: 9 aspect ratio picture such as a movie without distortion of the screen in a television receiver having an aspect ratio of 4: 3.

However, the development of a wide television receiver having an aspect ratio of 16: 9 has led to the necessity of displaying a 4: 3 video signal on the full screen of a wide television receiver.

Therefore, in response to the spread of wide television receivers, 4: 3 programs, 16: 9 programs, and 2: are used to revolve between television stations with 4: 3 aspect ratio and wide television receivers with 16: 9 aspect ratio in each broadcasting station. Increasingly, one cinema program is mixed and transmitted.

The receiving side detects a wide screen signal (WSS) indicating whether the program transmitted from the broadcasting station is a 4: 3 program, a 16: 9 program, or a 2: 1 cinema program, and automatically displays a screen of the wide television receiver. There is a need to expand or extend the system.

However, in order to receive and watch 4: 3 programs transmitted from the broadcasting station by using a 16: 9 wide TV receiver, only when the scanning player on the screen is horizontally compressed to watch and also when a 2: 1 cinema signal is received, It is possible to watch only when the injection player on the screen is heightened.

As described above, the horizontal compression / expansion apparatus for a conventional TV screen for displaying a 4: 3 video signal or a 2: 1 cinema video signal on a wide television receiver having an aspect ratio of 16: 9 is provided in the accompanying drawings. As shown in FIG. 1, the clock generator 104 generates a first clock CLK1 whenever the horizontal synchronization signal Hsy is input through the synchronization input terminal 101 for horizontal compression and horizontal expansion; A clock counter 106 for counting and outputting a first clock CLK1 generated by the clock generator 104; A first multiplier 107 which multiplies the first clock CLK1 generated by the clock generator 104 by 4/3 to generate a second clock CLK2; A second multiplier 108 for multiplying the first clock CLK1 generated by the clock generator 104 to 8/9 to generate a third clock CLK3; When the horizontal expansion is performed by the cinema image signal having the aspect ratio of 2: 1, the clock coefficient value of the clock counter unit 106 is compared with the set value, and the removed image section is determined on the monitor screen having an aspect ratio of 16: 9. Generates the first clock selection control signal S1 and the write enable signal WE, and removes 1/18 of the left and right screens from the 16: 9 monitor screen to display a cinema video signal with a 2: 1 aspect ratio. A removal image section discriminating unit 11 for performing the processing; By comparing the clock coefficient value and the set value of the clock counter unit 106, the effective video section and the horizontal retrace section are discriminated, and the second clock selection control signal S2 and the side panel selection control signal SPC are output accordingly. An effective image section discriminating unit 109 for horizontally compressing the screen; An edge detector 105 which detects the rising edge of the horizontal synchronization signal Hsy input through the synchronization input terminal 101 and generates a reset signal RST each time the rising edge is detected; The first clock CLK1 of the clock generator 104 and the third multiplier 108 of the clock generator 104 are switched according to the first clock selection control signal S1 generated by the removal image section determination unit 110. A first clock selector 111 which selects and outputs one of the clocks CLK3; The second clock CLK2 and the first multiplied by 4/3 in the first multiplier 107 are switched by switching according to the second clock selection control signal S2 generated by the valid video section determination unit 109. A second clock selector 112 which selects and outputs one clock selected by the clock selector 111; The first clock CLK1 generated by the clock generator 104 is input as a recording clock according to the recording enable signal WE generated by the removal image section determination unit 110, and the first clock selection unit 111 is input. Receives a clock selected as a read clock and stores and outputs 8-bit digital image data inputted through the image input terminal 100 for each horizontal line and outputs the reset signal to the reset signal RST generated by the edge detector 105. A first line memory section 102, reset by the first line memory section 102, for recording / reading the next line of image data; The clock selected by the first clock selector 111 is input to the write clock and the clock selected by the second clock selector 112 is read as the read clock to store the image data obtained from the first line memory 102. A second line memory section (103) for storing and outputting each horizontal line and being reset by the reset signal (RST) generated by the edge detection section (105) to record / read the image data of the next line; The brightness level of an arbitrary side panel is inserted into the image data input for each line by the second line memory unit 103 in accordance with the side panel selection control signal SPC of the effective image section discriminating unit 109 and horizontally changed. The side panel inserting unit 113 outputs the digital image data through the output terminal 114.

Two first and second line memory units 102 are converted into digital signals in the horizontal compression / extension apparatus of the conventional TV screen configured as described above to compress or expand the image signals input through the image input terminal 100. 103 is connected in series, and only the second line memory unit 103 is required for horizontal compression of the video signal, and two first and second line memory units 102 (for horizontal extension) are used. 103).

In the horizontal compression / extension apparatus of such a TV screen, first, a process of horizontal compression processing will be described with reference to FIG.

When the horizontal synchronization signal Hsy is input through the synchronization input terminal 101, the clock generator 104 compresses the synchronization input terminal 101 to horizontally compress the digital image data input through the image input terminal 100. When the horizontal synchronization signal Hsy is input through the first clock CLK1, the first and second multipliers 107 and 108, the clock counter 106, the first clock selector 111 and The first line memory unit 102 is provided.

The first multiplier 107 multiplies the first clock CLK1 input from the clock generator 104 by 4/3, and converts the first clock CLK1 into a second clock CLK2 to be described later. 112).

The second multiplier 108 multiplies the first clock CLK1 input from the clock generator 104 to 8/9 to provide the third clock CLK3 to the first clock selector 111. Done.

In addition, the clock counter unit 106 counts the start of the first clock CLK1 input from the clock generator 104 every line, and removes the count value from the image segment determination unit 110 and the effective image. The section discriminating unit 109 is provided.

The removal image section determination unit 110 compares the value counted by the clock counter unit 106 with the setting value, and when the aspect ratio is 4: 3, in order not to remove the left and right sides of the screen, the first clock selection control signal ( S2) is provided to the first clock selector 111 and a write enable signal WE is provided to the first line memory 102. FIG.

The valid video section discriminating unit 109 distinguishes the horizontal recursive ear section from the valid video section by comparing the result value and the set value of the coefficient input from the clock counter unit 106.

This is because, when reading the image signal stored in the second line memory unit 103, which will be described later, the clock speed should be differently divided into sections to be compressed and sections not to be compressed during one horizontal scanning period.

In other words, the section that should not be compressed is the horizontal retrace section and should not be compressed because this section has horizontal synchronization.

As described above, the effective video section determining unit 109 compares the count result value and the set value of the first clock CLK1 obtained by counting by the clock counter unit 106 with the horizontal retrace section and the effective video as described above. The second clock select control signal S2 is provided to the second clock selector 112 in order to change the read clock speed of the second line memory unit 103 according to the divided result, and the side panel. The selection control signal SPC is generated and provided to the side panel insertion unit 113.

The first clock selection unit 111 is switched by the first clock selection control signal S1 input from the removal image section determination unit 110 so that the first clock pulse is transmitted from the second multiplication unit 108. The third clock CLK3 multiplied by 8/9 with respect to the CLK1 is blocked, and the first clock CLK1 generated by the clock generator 104 is selected to select the first and second line memory units 102 ( 103 and the second clock selector 112.

In addition, the second clock selection unit 112 is switched by the second clock selection control signal S2 input from the effective video section determination unit 109, so that the first clock in the first multiplication unit 107 ( The second clock CLK2 multiplied by 4/3 with respect to the CLK1 and the first clock CLK1 selected by the first clock selecting unit 111 are alternately selected to be provided to the second line memory unit 103. do.

At this time, when the digital image data is input through the image input terminal 100, the first line memory unit 102 is enabled by the write enable signal WE input from the removal image section determination unit 110. Enabled and receives the first clock (CLK1) input from the clock generator 104 as a recording clock to store the 8-bit digital image data input through the image input terminal 100 for each horizontal line and the first The first clock CLK1 selected by the clock selector 111, that is, the write clock of the first line memory 102 is input as a read clock, and the stored image data is output for each horizontal line to output the second line. The memory unit 103 is provided.

As a result, the first line memory section 102 writes and reads to the first clock CLK1 generated by the clock generation section 104, thereby delaying a simple 1H (horizontal scanning period), and the change of the signal none.

The reset signal RST of the edge detector 105 detects a rising edge of the horizontal synchronization signal Hsy input through the synchronization input terminal 101 and generates a reset signal RST at each time. The first line memory section 102 is initialized to record and read the image data of the next line in the same manner as described above.

Meanwhile, the second line memory unit 103 receives a read clock of the first line memory unit 102 selected from the first clock selector 111, that is, the first clock CLK1 as a write clock. The image data input from the first line memory unit 102 is recorded every line, and the first clock CLK1 and the first clock CLK1 that are alternately selected by the second clock selection unit 112 are input. The second clock CLK2 multiplied by 4/3 is input to the readout clock and the stored image data is first-in-first-out for each horizontal scan line and provided to the side panel insertion unit 113.

In other words, in order to horizontally compress the image data to 4: 3, the second clock selector 112 first discriminates the effective video section in order to read the image data of the second line memory unit 103, unlike at the time of recording. When the second clock selection control signal S2 of the unit 109 indicates the horizontal retracement, as described above, the first clock CLK1 selected by the first clock selection unit 111, that is, the second line memory unit ( By selecting a clock to be used as the recording clock of 103, the image data stored in the second line memory section 103 is read out as it is and there is no change of the image data.

When the second clock selection control signal S2 of the effective video section determination unit 109 indicates the valid video section, the second clock obtained by multiplying the first clock CLK1 by 4/3 through the first multiplier 107 is performed. By selecting (CLK2) and reading the image data stored in the second line memory section 103, the aspect ratio becomes 4: 3 on the screen in which the effective image section has an aspect ratio of 16: 9 as shown in Fig. 2A. Will be maintained.

As shown in (a) of FIG. 2, the side panel (on the left and right portions of the video signal having a 16: 9 aspect ratio except for an effective video section of 4: 3, i.e., the left and right portions of the video signal compressed to 3/4) In order to insert the LSP (RSP), it is required to pass through the side panel inserting unit 113. In this case, the left and right side panel LSPs ( The luminance level value 0 may be inserted at the RSP) position.

In other words, the side panel inserting unit 113 is the image of the second line memory unit 103 when the side panel selection control signal SPC obtained by dividing by the effective image section determining unit 109 indicates the effective video section. When data is selected and output through the output terminal 114, and the side panel selection control signal (SPC) does not indicate the effective video section, the luminance level value of the ground potential is selected and inserted into both sides of the valid video section, and the output terminal ( 114), a screen having an aspect ratio of 4: 3 can be obtained horizontally on a screen having an aspect ratio of 16: 9 as shown in FIG.

In addition, in order to horizontally extend a cinema video signal having an aspect ratio of 2: 1 in a wide television receiver having an aspect ratio of 16: 9, first, the clock generation is performed using the digital image data input through the image input terminal 100. The first clock CLK1 generated by the unit 104 and the first clock CLK1 and the second body generated by the clock generator 104 are written to the first line memory unit 102 every horizontal line and then read. The allocation unit 108 reads the selected clock through the first clock selector 111 from among the third clock CLK3 multiplying the first clock CLK1 by 8/9.

The control signal for selecting the first clock CLK1 of the clock generator 104 and the third clock CLK3 of the second multiplier 108 by the first clock selector 111 is as described above. The first clock selection control signal S1 generated by the removal image section determination unit 110.

That is, in order to display an image such as a cinema signal having an aspect ratio of about 2: 1 on a monitor having an aspect ratio of 16: 9, the left and right screens should be removed by 1/18 as shown in (b) of FIG. 2. As described above, the determination unit 110 compares the output count value and the set value of the clock counter unit 106 with the side panel sections LSP1 (RSP1) to be removed to the left and right corresponding to (b) of FIG. 2. In this case, the image data is not written to the first line memory unit 102 by disabling the write enable signal WE of the first line memory unit 102.

Similarly to the case of horizontal compression, in the effective video section, the first clock selector 111 generates a second clock at the second multiplication unit 108 by the first clock selection control signal S1 of the removed video section determination unit 110. The third clock CLK3 multiplied by 8/9 with respect to one clock CLK1 is selected to read image data stored in the first line memory unit 102.

Therefore, the video data read in the effective video section becomes 16/18 of the original video signal, but is slowly read by 8/9 times, that is, the third clock CLK3, so that the left and right sides of the 16: 9 monitor are temporally separated. Displayed correctly.

The left and right 1/18 signals recorded in the first line memory unit 102 are not automatically read, but the rising edge of the horizontal synchronization signal Hsy input from the synchronization input terminal 101, that is, the edge detection unit ( It is reset by the reset signal RST generated at 105 and is passed to the next line.

In the second line memory unit 103, the second clock selector 112 may transmit the first clock selector 111 by the second clock select control signal S2 of the valid video section determination unit 109. The selected third clock CLK3, that is, the recording clock of the second line memory unit 103 is selected, and image data stored in the second line memory unit 103 is read and provided to the side panel inserting unit 113.

That is, as a result, the read line and the write clock of the second line memory section 103 are put together so that the horizontally stretched scan line can be read.

The side panel inserting unit 113 selects and outputs only the image data read from the second line memory unit 103 by the side panel selection control signal SPC provided from the effective image section determining unit 109. By outputting through the terminal 114, as shown in (b) of FIG. 2, the monitor having a 16: 9 aspect ratio can watch a cinema video signal having a 2: 1 aspect ratio.

However, the conventional TV screen horizontal compression / expansion technology is a method of horizontally compressing and expanding in time, which is a memory, that is, a first and second line memory by using a clock circuit without using a digital filter. The compression ratio and decompression ratio of the clock used for the negative will be different.

Therefore, whenever the compression ratio and the expansion ratio of the clock are different, a clock having a speed corresponding thereto is required. Thus, a clock circuit for generating a clock corresponding thereto, namely, a first multiplier, a clock counter, and a clock generator The hardware is very complicated and the clock is difficult to control, as well as the system has an unstable operation.

Accordingly, an object of the present invention is to provide a single clock in two line memories when a 4: 3 video signal or a 2: 1 cinema video signal is received by a 16: 9 wide television receiver. The present invention provides a screen aspect ratio converting apparatus that simplifies hardware as a whole by recording / reading and performing horizontal compression and stretching of two video signals.

It is another object of the present invention to simplify the hardware and to perform horizontal compression and horizontal stretching of an image with a single clock to operate the system more stably.

It is still another object of the present invention to expand the compression and decompression ratios of video signals in a variety of simple hardware configurations.

Another object of the present invention is to compress and expand in a horizontal as well as a vertical direction by using a line memory instead of a sample memory and a field memory instead of a line memory.

Another object of the present invention is to freely change the screen aspect ratio of a video signal even with a single clock speed.

The aspect aspect converter according to the present invention for achieving the above object comprises a clock generating means for generating a first clock corresponding to each horizontal synchronization signal input; Clock counting means for counting a first clock obtained by said clock generating means to a set value and generating a first write enable signal; Counting the first clock obtained by the clock generating means for every sample according to horizontal compression and horizontal extension, and selecting each count value according to the coefficient selection signal included in the horizontal synchronous signal according to horizontal compression and stretching. Coefficient control means for generating a first read enable signal and a second write enable signal by logically generating the respective coefficient values and the coefficient selection signal; In response to the first write enable signal obtained by the clock counting means and the first read enable signal obtained by the coefficient control means, the first clock obtained by the clock generating means is inputted as a recording / reading clock, and the input digital image data is input every line. First line memory means for recording and outputting; Combining the coefficient values set differently to the current image data and the previous image data inputted from the first line memory means, and selecting them for each line according to the coefficient control signal generated by the coefficient control means, each different value. Sample interpolation means for outputting; The first clock obtained by the clock generating means is input to the recording / reading clock according to the second write enable signal and the fixed second read enable signal obtained by the coefficient control means. Second line memory means for recording and outputting each time; Characterized in that made.

In the above, the coefficient control means includes counter means for sequentially counting the first clock obtained by the clock generation means to generate a 3-bit coefficient control signal; An exclusive-OR device for outputting an exclusive-OR inversion of any two-bit value among the three-bit values obtained by the counter means; First multiplexing means for multiplexing a 2-bit value or 3-bit value obtained by the counter means and a 1-bit value from an exclusive logical sum element to generate different 4-bit coefficient control signals for interpolation of image data; Enable generation means for receiving a two-bit value of the three bits obtained by the counter means and the coefficient selection signal, respectively, and logicizing them to generate a first read enable signal and a second write enable signal; Characterized in that made.

The sample interpolation means may include: a sample memory for storing image data input from the first line memory means every line; Second multiplexing means for multiplexing and outputting previous image data obtained from the sample memory and current image data obtained from the first line memory according to the coefficient control signal obtained by the first multiplexing means; Line interpolation means for multiplying coefficient values set differently from each current or previous image data for two lines obtained by the second multiplexing means; Each image data obtained by interpolation in the line interpolation means and previous image data directly inputted in the second multiplexing means are sequentially selected for each line according to the 3-bit coefficient control signal input from the coefficient control means. Third multiplexing means for outputting different values; And data summing means for summing two different image data obtained by multiplexing by the third multiplexing means and providing the second line memory means to the second line memory means.

Hereinafter, described in detail with reference to the accompanying drawings of the present invention.

FIG. 3 is a block diagram of the present invention of a TV screen horizontal compression / new apparatus. As shown in FIG. 3, a first clock corresponding to a horizontal synchronous signal Hsy is input through the first synchronous input terminal 201. A first clock generator 202 for generating CLK1; A first clock counter unit 203 for generating a first write enable signal WE1 by counting the first clock CLK1 generated by the first clock generator 202 to a predetermined value; The first clock CLK1 generated by the first clock generator 202 is counted to generate a random bit value, and the random bit value is converted into a horizontal compression mode (normal mode) and a horizontal extension mode (cinema zoom mode). a first read enable signal RE1 included in the horizontal synchronous signal Hsy and selected by a coefficient selection signal N / CS inputted through a control terminal 208 according to a cinema zoom mode. A coefficient control unit 204 for generating a second write enable signal WE2 and a coefficient control signal S of a predetermined bit; According to the first write enable signal WE1 generated by the first clock counter unit 203 and the first read enable signal RE1 generated by the coefficient control unit 204, the first clock generator 202 may be used. First line memory that receives the first clock CLK1 as a write / read clock WR / RD, that is, a single clock, and records and outputs digital image data input through the first image input terminal 200 every line. Section 205; 4: 3 or 7 according to the coefficient control signal S of a predetermined bit generated by the coefficient control unit 204 with the current image data and previous image data inputted from the first line memory unit 205 every line. A first sample interpolator 206 that outputs sample interpolated by: 8; It is enabled and disabled according to the second write enable signal WE2 and the fixed second read enable signal RE2 generated by the coefficient control unit 204, and the horizontal synchronous signal is generated by the first clock generator 202. The first clock CLK1 generated whenever (Hsy) is input to the recording / reading clock (WR / RD), and the image data interpolated by the sample is interpolated by the first sample interpolation unit 206 and recorded every line. A second line memory unit 207 for outputting the horizontally converted digital image data to the output terminal 210; The edge generating the reset signal RST in the first and second line memory units 205 and 207 whenever a rising edge of the horizontal synchronization signal Hsy is detected through the first synchronization input terminal 201. It consists of the detection part 209.

In the above, the coefficient controller 204 sequentially counts the first clock CLK1 generated by the first clock generator 202 through the first to third flip-flops 20 to 22 to obtain a 3-bit value. An outputting first counter portion 204a; An exclusive logical sum element 204b for exclusively ORing the two bit values input from the first flip flop 20 and the second flip flop 21 of the first counter portion 204a; In order to interpolate the image data, two or three bit values counted by the first counter unit 204a and one bit value of the exclusive logical sum element 204b are multiplexed, respectively. A first multiplexer 204d for generating S3); A first read enable signal RE1 by logicalizing a 2 bit value among the 3 bits counted by the first counter unit 204a and a coefficient selection signal N / CS inputted through the control terminal 208; And an enable generation unit 204c for generating the second write enable signal WE2.

The first multiplexer 204d may combine one bit that is exclusively ORed in the exclusive logical sum element 204b and three bits that are counted in the first to third flip-flops 20 to 22 of the first counter unit 888. A first selector 288 which receives all six bits and selects only three of the three bits by the coefficient selection signal N / CS to generate three-bit coefficient control signals S1-S3; The 1-bit value counted by the first flip-flop 20 of the first counter unit 204a and the 1-bit value counted by the third flip-flop 22 are selected according to the coefficient selection signal N / CS. It consists of the 2nd selection part 27 which generate | occur | produces with the control signal SO.

The enable generator 204c includes: a first inverting element 23 for inverting the 1-bit value counted by the second flip-flop 21 of the first counter 204a; The first bit value counted by the first flip flop 20 of the first counter unit 204a and the first bit value of the first inverting element 23 and the coefficient selection signal N / CS are logically inverted to form a first logical value. A first logical inversion element 25 for generating a read enable signal RE1; Coefficient selection signal (N /) inverted through each of the 1-bit value counted by the first and second flip-flops 20 and 21 of the first counter unit 204a and the second inverting element 24. The second logical product inversion element 26 which generates the second write enable signal WE2 by performing logical AND inversion on CS is configured.

In addition, as shown in FIG. 5, the second sample interpolator 206 outputs the current image data output from the first line memory unit 205 and input through the second image input terminal 200a. A first sample memory 206a for storing every line; Previous image data and first line memory unit input from the first sample memory 206a according to the 1-bit coefficient control signal S0 selected and selected by the first multiplexer 204d of the coefficient control unit 204. A second multiplexer which selects and outputs current image data output from 205 and input through the second image input terminal 200a every line through the third and fourth selectors 29 and 30; 206b); A first line multiplier 206c for combining and outputting coefficient values differently set to respective current or previous image data of two lines obtained through the second multiplexer 206b; The first multiplexer 204d of the coefficient control unit 204 displays the respective image data obtained by the first line multiplier 206c and the previous or current image data directly input from the second multiplexer 206b. A third multiplexer 206d for sequentially selecting every line according to the 3-bit coefficient control signal S1-S3 and outputting different values; A first data summing unit 206e is added to the second line memory unit 207 by adding two different 8-bit image data obtained by multiplexing by the third multiplexer 206d.

The first line multiplier 206c is a 1/8, 2/8, 3/8 to the current or previous image data selected and input by the third selector 29 of the second multiplexer 206b. A first to fourth multipliers 31 to 34 multiplying 4/8 respectively; A multiplier for outputting 4/8, 5/8, 6/8, and 7/8 to the current or previous image data selected and input by the fourth selector 30 of the second multiplexer 206b, respectively. It consists of 5-8th multipliers 35-38.

The third multiplexer 206d may include current or previous image data directly input from the third selector 206b and first to fourth multipliers 31 to 34 of the first line multiplier 206c. And multiplying the image data inputted by the values set by the sixth to eighth multipliers 36 to 38 in accordance with the 3-bit coefficient control signal S1-S3 input by the first multiplexer 204d. A fifth selection unit 39 which selects and outputs the first data summing unit 206e; The image data obtained by multiplying the set ground potential by one bit and a value set by the first to third multipliers 31 to 33 and the fifth to eighth multipliers 35 to 38 of the first line multiplier 206c is obtained. The sixth selector 40 selects every line according to the three-bit coefficient control signals S1-S3 obtained by the first multiplexer 204d and outputs them to the first data summing unit 206e.

As described above, the operation and effects of the present invention constructed as described in detail with reference to FIGS. 3 to 7 are as follows.

The first and second line memory units 205 and 207 generate the first and second line memory units 205 and 207 in order to compress or decompress an image signal converted into a digital signal and input through the first image input terminal 200. The image signal is horizontally compressed and decompressed by recording and reading with a single clock.

In the horizontal compression / extension apparatus of such a TV screen, first, the horizontal compression processing will be described first.

When the horizontal synchronous signal Hsy is input through the first synchronous input terminal 201, the first clock generator 202 is configured to horizontally compress the digital image data input through the first image input terminal 200. Whenever the horizontal synchronous signal Hsy is input through the first synchronous input terminal 201, a first clock CLK1 corresponding thereto is generated so that the coefficient control unit 204, the first and second line memory units 205 ( 207 and the first clock counter unit 203.

The first clock counter unit 203 receives the first clock CLK1 generated whenever the horizontal synchronization signal Hsy is input from the first clock generator 202, counts up to a set value, and records the first clock. The enable signal WE1 is provided to the first line memory unit 205.

The coefficient controller 204 counts the first clock CLK1 generated by the first clock generator 202 to generate a 3-bit value, and converts the 3-bit value into a horizontal compression mode (normal mode) or a horizontal extension. The first read enable signal RE1 is multiplexed and logicalized by the coefficient selection signal N / CS included in the horizontal synchronous signal Hsy according to a mode (cinema zoom mode) and input through the control terminal 208. ), The second write enable signal WE2 and the 4-bit coefficient control signal S are generated.

That is, the coefficient control unit 204, as shown in Figure 4, the first counter unit 204a consisting of the first to third flip-flop (20 to 22), the exclusive logical sum element 204b, First and second multiplexing units 204d comprising first and second selection units 28 and 27, first and second inverting elements 23 and 24, and first and second logical inverting elements 25 ( And an enable generation unit 204c.

The first to third flip-flops 20-22 of the first counter unit 204a sequentially count the first clock CLK1 generated by the first clock generator 202 to generate three bits C 0 -C 2. A three-bit counter that generates?), Which counts the samples on the horizontal scan line by 4 samples for 4: 3 interpolation and 8 samples for 7: 8 interpolation, thereby enabling the enable generator 204c. This is to provide the exclusive logical sum element 204b and the first multiplexer 204d.

Here, the reason for 7: 8 interpolation without 8: 9 interpolation in the horizontal extension is to simplify the hardware by sharing the first counter unit 204a and the first sample interpolator 206 to be described later. To do this.

Of course, 8: 9 interpolation may be performed by using a 4-bit counter, and the first sample interpolation unit 206 at this time will be described separately in another embodiment of the present invention.

Subsequently, during horizontal compression, the exclusive logical sum element 204b decodes the bit values C0 and C1 counted by the first flip-flop 20 and the second flip-flop 21 of the first counter part 204b. The exclusive OR is input to the first selector 28 of the first multiplexer 204b.

In addition, the first selector 28 of the first multiplexer 204b may include the exclusive OR value of the exclusive OR element 204b and the first and second flip flops 20 (of the first counter unit 204a). The first to third flip-flops 20 to 22 of the first counter unit 204a are received by receiving the bit values C0 and C1 counted in 21 as the upper three bit values N0 and N1 and N2. After receiving the bit value (C0) (C1) (C2) of the () as the lower 3 bit value and included in the horizontal synchronization signal (Hsy) by the coefficient selection signal (N / CS) input through the control terminal 208 The upper 3 bits (N0-N2) or the lower 3 bits (C0-C2) are selected and generated as 3-bit coefficient control signals (S1-S3), and the second selector (1) of the first multiplexer (204d) 27 is one of the bit value C0 of the first flip flop 20 and the bit value C2 of the third flip flop 22 of the first counter unit 204a. Selects and generates a one-bit coefficient control signal S0.

In other words, in the case of horizontal compression, the coefficient selection signal N / CS input through the control terminal 208 is logically low potential in the horizontal compression mode, so that the first, It is input to the second selectors 28 and 27, and is provided to the first and second selectors 28 and 27 at the logically high potential in the horizontal extension mode.

The first selector 28 is the exclusive logical element 204b, the first and the second when the coefficient selection signal N / CS input through the control terminal 208 is logically low potential, that is, in the horizontal compression mode. The 3-bit value (N0-N2) input from the flip-flop (20) (21) is selected as the high-potential, that is, the 3-bit value (C0-C2) in the horizontal extension mode, and is converted into the coefficient control signal (S1-S3). And the second selector 27 supplies the bit value C0 of the first flip-flop 20 when the coefficient selection signal N / CS is low potential. In the above case, the bit value C2 of the third flip-flop 22 is selected and provided as the coefficient control signal S0 to the first sample interpolator 206 to be described later.

Meanwhile, the first inversion element 23 of the enable generation unit 204c of the coefficient control unit 204 inverts the one bit value C1 counted by the second flip-flop 21 to thereby invert the first logical inversion element. The second inverting element 24 inverts the low potential or the high potential according to the horizontal compression and horizontal extension mode input through the control terminal 208 to the second logical inversion element 26. To be provided.

The first logical sum inversion element 25 has a low potential or high potential due to a horizontal compression / horizontal extension mode, a value inverted by the first inversion element 23, and a one-bit value C0 of the first flip-flop 20. Is the logical AND inversion to generate a first read enable signal RE1, the second logical inversion element 26 is a coefficient selection signal (N) inverted to a high potential or a low potential through the second inversion element (24) / CS) and the logical OR of the bit values C0 and C1 counted by the first and second flip-flops 20 and 21 to generate a second write enable signal WE2, wherein the second write enable signal WE2 is generated. The two- logical inversion element 26 is a four-sample interval that is input in every sample block counted by the first counter unit 204a in the horizontal compression mode (4: 3 interpolation, and 7 samples that are input in the case of 7: 8 interpolation). The second write enable signal (only when the bit C0 (C1) output from the fourth section, i.e., the first and second flip-flop 20, 21 is 1, 1 for each section, i. To low potential WE2) The open second line memory unit 207 thereby disabling.

As shown in FIG. 7, each sample block, that is, the first section (A1, B1), the second section (B1, C1), the third section (C1, D1), and the fourth section (D1, A2) This is because it is not necessary to record data in the fourth section (D1, A2) of each sample block in.

In addition to the fourth and eighth sections, the second write enable signal WE2 is supplied to the second line memory unit 207 at a high potential, and a high potential is provided every sample section in the horizontal extension mode. Will be provided.

In addition, in the horizontal extension mode (cinema zoom mode), since the coefficient selection signal N / CS input through the control terminal 208 is logically high potential, the first logical product inverting element 25 causes every sample to be used. The first read enable signal RE1 is low when the bit intervals C0 and C1 of the first and second flip-flop 20 and 21 are C0 = 1 and C1 = 0. As it goes up, the first line memory unit 205 is disabled.

That is, as shown in FIG. 8, each sample block, that is, the first and second sections A1 and B1, the third sections B1 and C1, the fourth sections C1 and D1, and the fifth section ( In the second section (A1, B1) of the D1, E1, 6th section (E1, F1), 7th section (F1, G1), 8th section (G1, H1), there is no need to read new data. This is because the second sample b1 is generated while keeping the data as it is.

In other sample sections, the first reader enable signal RE1 is provided at high potential to the first line memory unit 205. In addition, in the horizontal compression mode, the first reader enable signal RE1 is supplied. It is provided at high potential for every sample interval.

At this time, when digital image data is input through the first image input terminal 200, the first line memory unit 205 generates a reset signal RST whenever a rising edge of the horizontal synchronization signal Hsy is detected. The first write enable signal WE1 generated from the first clock counter 203 and the first read enable signal RE1 generated from the coefficient control unit 204 are initialized by the edge detector 209. The first clock CLK1 controlled by the first clock generator 202 is input to the recording and reading clock WR / RD, and the input digital image data is synchronously recorded every line, and the horizontal compression and stretching are performed. In accordance with the synchronous output is provided to the first sample interpolator 206.

In the side panel (LSP) (RSP), which is removed from the left and right of the cinema signal as shown in FIG. 2 (b), the first write enable signal WE1 generated by the first clock counter unit 203 is used. The one-line memory unit 205 is disabled so that video data is not recorded.

When the image data is to be read from the first line memory unit 205 during 4: 3 horizontal compression, the first logical product of the enable generation unit 204c configured in the coefficient control unit 204 is described as described above. The inverter 25 reads the first read enable signal RE1 generated at every sample interval and provides the readout signal to the first sample interpolator 206 and the first generator 204c at the time of horizontal extension. Except for the second sample interval, the logical product inversion element 25 is read out with the first read enable signal RE1 generated in every sample interval and is provided to the first sample interpolator 206.

The first sample interpolator 206 controls the 4-bit coefficient generated by the coefficient controller 204 with the current image data and the previous image data inputted from the first line memory unit 205 every sample period. Sample interpolation is performed at 4: 3 or 7: 8 according to the signals S0-S3 and the interpolated image data is provided to the second line memory unit 207.

In other words, in the case of 4: 3 interpolation, four sample combinations (sample blocks) of image data input from the first line memory unit 205 are generated and output in three sample combinations. Seven sample combinations (sample blocks) input from the line memory unit 205 are generated as eight sample combinations and provided to the second line memory unit 207.

That is, the first sample interpolator 206 includes a first sample memory 206a, a third and fourth selectors 29 and 30, as shown in FIG. 206b), a first line multiplier 206c composed of first to eighth multipliers 31-38, a third multiplexer 206d composed of fifth and sixth selectors 39 and 40, and And a first data summing unit 206e.

In this case, the first sample memory 206a records image data output from the first line memory unit 205 and input through the second image input terminal 200a at every sample interval, and records the recorded image data. The data is provided to the input terminal Io of the third selector 29 and the input terminal I1 of the fourth selector 30 configured as the second multiplexer 206b, and the second image input terminal ( The current image data through 200a is directly input to the input terminal I1 of the third selector 29 and the input terminal Io of the fourth selector 30.

The third selector 29 is stored in the first sample memory 206a by a one-bit coefficient control signal So selected from the second selector 27 of the first multiplexer 204d of FIG. Selects the image data or the current image data and provides them to the input terminal Io of the fifth selector 39 configured in the fourth multiplexer 206d and the first to the first line multipliers 206c. 4 multipliers 31 to 34, and the fourth selector 40 selects the current image data or the previous image data in the same manner as the third selector 29 so as to select the first line multiplier 206c. ) To the fifth to eighth multipliers 35 to 38.

In this case, in the case of 4: 3 interpolation, three samples (a1, b1.c1) are generated by interpolating four input samples by the same method as in FIG.

That is, it will be described in more detail as follows.

First, the 1-bit coefficient control signal S0 output from the second selector 27 of the coefficient control unit 204, as shown in FIG. 4, is the first and the first counter of the first counter unit 204a. One of the values counted by the three flip-flops 20 and 22 is selected and outputted. In this case, the second selecting unit 27 is the first flip-flop 20 as shown in FIG. 6 by the horizontal compression mode. 1-bit value counted in < RTI ID = 0.0 >) is selected as the count control signal S0.

However, in the above, the coefficient control signal S0 becomes low potential (0) in the first sample section, the third sample section, the fifth sample section, and the seventh sample section, whereby the third selector 29 of FIG. As described above, the previous image data stored in the first sample memory 206a is selected, and the first to fourth multipliers of the input terminal Io of the fifth selector 206d and the first line multiplier 206c are used. (31 to 34), and in the other sample section is provided by selecting the image data input through the second image input terminal (200a).

The fourth selector 30 selects the current image data input through the second image input terminal 200a when the coefficient control signal S0 has a low potential, thereby selecting the first line multiplier 206c. When the fifth to eighth multipliers 35 to 38 are provided and the coefficient control signal S0 has a high potential, that is, as shown in FIG. 6, the first, second, fourth, sixth, and eighth sample intervals. The previous image data stored in the sample memory 206a is selected and provided to the fifth to eighth multipliers 35 to 38.

The first to fourth multipliers 31 to 34 of the first line multiplier 206c are respectively 1/8, 2/8, and 3 to the pixels of the previous or current image data selected by the third selector 29. And multiply by / 8 and 4/8 to provide to the input terminals I1-I4 of the fifth selector 39, respectively. The pixel of the image data multiplied by 3/8 is provided to the input terminals I7-I5 of the sixth selector 40.

In addition, the fifth to eighth multipliers 35 to 38 of the first line multiplier 206c may correspond to the pixels of the current or previous image data selected by the fourth selector 30, respectively. The fifth selector multiplies 6/8 and 7/8 to provide the input terminals I4-I1 of the sixth selector 40 and multiplies the pixels of image data multiplied by 5/8, 6/8 and 7/8. To the input terminals I5-I7 of 206d.

The fifth and sixth selectors 39 and 40 of the third multiplexer 206d may provide image data input through its input terminals Io-I7 to the first selector 28 of FIG. The three-bit coefficient control signals S1-S3 are selected for each sample section and provided to the first data summing unit 206e.

That is, the 3-bit coefficient control signal S1-S3 provided by the first selector 28 is 0, 110, 101, and 11 from the first sample section to the fourth sample section as shown in FIG. Then, 0, 101, 101, and 11 are repeatedly provided to the fifth and sixth selectors 39 and 40 from the fifth sample section to the eighth sample section in the same manner.

Accordingly, the fifth and sixth selectors 39 and 40 have the previous image data 1 and the ground potential (0) input to their input terminal Io in the first sample interval as shown in FIG. ) Are selected and provided to the first data summing unit 206e, whereby the data summing unit 206e adds these two input data to generate one sample a1.

In the second sample section, the input terminal I3 is selected by the 3-bit coefficient control signal S1-S3, that is, 3/8 and 5/8 in the third and sixth multipliers 33 and 36. The multiplied pixels are selected and provided to the first data summing unit 206e, and the data summing unit 206e adds these two pixel values to generate one sample b1 as shown in FIG.

In the third sample section, the input terminal I5 is selected by the 3-bit coefficient control signal S1-S3, that is, the pixel value multiplied by 5/8 and 3/8 is selected and the data summation unit ( 206e), one sample c1 is generated as shown in FIG.

Then, in the fourth sample section, the input terminal I6 is selected by the 3-bit coefficient control signal S1-S3, that is, the pixel value multiplied by 6/8, 2/8 is selected, and the first data is summed. The addition is made in the section 206e, which is meaningless since it is not written to the second line memory section 888 to be described later.

As such, the image data interpolated at 4: 3 by the first sample interpolator 206 is provided to the second line memory unit 207.

In the case of 7: 8 interpolation, 7 samples (a1, b1, c1, d1, e1, f1, g1, h1, i1) are generated by interpolating 8 samples by the same method as in FIG. a1) selects the input terminal Io of the fifth selector 39 and the input terminal Io of the sixth selector 40 in the same manner as described above to select the 8-bit first data summing unit 206e. The sample b1 may be generated by selecting the input terminal I1 of the fifth and sixth selectors 39 and 40, that is, by selecting a pixel value multiplied by 1/8 and 7/8. The data may be added through the data summing unit 206e, and the sample c1 selects the input terminal I2 of the fifth and sixth selection units 39 and 40, that is, 2/8 and 6/8 are multiplied. The pixel value may be selected and added through the data summing unit 206e, and the sample d1 may select the input terminal I3 of the fifth and sixth selection units 39 and 40.

When the sample i1 is also selected in the same manner as described above, eight samples a1 to i1 are generated in the first data summing unit 206e and provided to the second line memory unit 207.

Here, the 1-bit coefficient control signal S0 provided to the third and fourth selectors 39 and 40 of the second multiplexer 206b is the first sample memory 206a until the samples a1-d1. ) Through the first to fourth multipliers (31 to 34) to be input to the fifth selector (39), and the fifth to eighth multipliers (35 to 38) to the samples (e1-i1). By inputting the multiplier to the sixth selector 40 through the use of a multiplier, the two fifth and sixth selectors 39 and 40 share the hardware, thereby simplifying the hardware.

Therefore, the 1-bit coefficient control signal S0 output from the second selector 27 of the first multiplexer 204d of FIG. 4 uses the output of the first flip-flop 20 whose state changes every four clocks. Just do it.

Meanwhile, the second line memory unit 207 receives the first clock CLK1 generated by the first clock generator 202 as a single clock of a write / read clock and receives the first clock interpolation unit 206 from the first sample interpolator 206. The generated image data is recorded and output. In this case, the output bit values Co (C1) of the fourth and eighth sections, that is, the first and second trim-flops 20 and 21 during horizontal compression are 11 days. When the second write enable signal WE2 output from the second logical inversion element 26 becomes low potential, the second line memory unit 207 has a fourth section input from the first sample interpolation unit 206. The video data of the eighth section is not recorded, but in other sections, the video data of the first sample interpolator 206 is recorded.

This is because, as in FIG. 7, data need not be recorded in the fourth and eighth sections of each sample block.

In addition, in the case of the horizontal extension, the second write enable signal WE2 output from the second logical product inversion element 26 is input at high potential for every sample period, so that the second line memory unit 207 has a first sample beam. Image data input from the executive unit 206 is recorded every line.

In addition, since the second read enable signal RE2 provided to the second line memory unit 207 is connected to the power supply terminal Vcc, the stored data is outputted through the output terminal 210 for every line. You can get the image data horizontally converted to 3 or 7: 8.

9 is another exemplary configuration diagram of the sample interpolator of FIG. 3. Here, the 1-bit coefficient control signal S0 outputted from the second selector 27 of FIG. The multipliers are connected to the sample delayed video data.

That is, the second and third sample memories 300 and 301 which receive the image data of the first line memory unit 205 through the second image input terminal 200a and delay and output the two samples; The current image data and the third sample memory 301 which are switched by the luminance signal Y and the color signal C input from the external input terminal 302 and input from the second image input terminal 200a The sample delayed image data is selected and output through the seventh selector 41 or the current image data and the sample delayed image data in the second sample memory 300 are selected and output through the eighth selector 42. A fourth multiplexer 303; A second line multiplier for multiplying and outputting coefficient values different from one sample delayed image data selected by the fourth multiplexer 303 and current image data or two sample delayed image data and current image data. Section 304; Each of the image data obtained by interpolation in the second line multiplier 304 and the image data and ground potential directly input from the seventh selector 41 of the fourth multiplexer 303 may be used. The first data summing unit 206e is multiplexed through the ninth and tenth selecting units 57 and 58 by the 3-bit coefficient control signal S1-S3 selected by the first selecting unit 28 of 204d). The fifth multiplexer 305 is provided.

In this case, the second line multiplier 304 is 1/8, 2/8, 3 to the two-sampled delayed image data or the current image data selected by the seventh selector 41 of the fourth multiplexer 303, respectively. 9th to 15th multipliers (43 to 49) provided to the input terminals (I1 to I7) of the ninth selector (57) by multiplying / 8, 4/8, 5/8, 6/8, and 7/8; 7/8, 6/8, 5/8, 4/8, 3/8, 2/8, and 1/8 are added to the one-sample delayed image data or the current image data selected by the eighth selector 42, respectively. 16 to 22 multipliers 50 to 56 which are multiplied and provided to the input terminals I1 to I7 of the tenth selector 58, and the same reference numerals are assigned to the same parts as those in FIGS. Will be explained.

First, the image data read from the first line memory unit 205 is stored in the second and third sample memory units 300 and 301 through the second image input terminal 200a and the third sample memory 301. The two sample delayed image data and the current image data are provided to the seventh selector 41 of the fourth multiplexer 303, and the image data and the current image which are delayed by one sample in the second sample memory 300. The data is provided to the eighth selector 42 of the fourth multiplexer 303.

At this time, when the 1-bit luminance signal Y from the external input terminal 302 is input, the seventh selector 41 of the fourth multiplexer 303 has its input terminal I0, that is, the second signal. The ninth selector of the ninth to fifteen multipliers 43 to 49 and the fifth multiplexer 305 of the second line multiplier 304 by selecting current image data input through the image input terminal 200a. The input terminal I0 of 57 is provided.

The eighth selector 42 selects image data delayed by one sample from the second sample memory 300 and provides the image data to the sixteenth to twenty-second multipliers 50 to 56.

Accordingly, the ninth to fifteenth multipliers 43 to 49 respectively calculate the current image data selected and input from the seventh selector 41 and have coefficient values of 1/8, 2/8, 3/8, and 4 /. 8, 5/8, 6/8, and 7/8 to be provided to the input terminals I1 to I7 of the ninth selector 57, and the sixteenth to twenty-second multipliers 50 to 56 are provided in the eighth. The second sample delayed image data selected and input by the selecting unit 42 is multiplied by the count values 7/8, 6/8, 5/8, 4/8, 3/8, 2/8, and 1/8, respectively, to obtain a tenth result. The input terminals I1 to I7 of the selector 58 are provided.

The ninth selector 57 selects the image data selected by the seventh selector 41 and the image data multiplied by the ninth to fifteen multipliers 43 to 49, that is, the input terminals I0 to I7. The first selector 28 shown in FIG. 4 selects each sample period by three-bit coefficient control signals S1-S3 and provides them to the eight-bit first data summing unit 206e. The selector 58 provides the image data multiplied by the ground potential 0 and the sixteenth to twenty-second multipliers 50 to 56, that is, the input terminals I0 to I7 thereof, which are provided by the first selector 28. The three-bit coefficient control signals S1-S3 are selected for each sample section and provided to the first data summing unit 206e.

When the color signal C obtained by multiplexing the in-phase component I and the quadrature component Q from the external input terminal 302 is input, the seventh selector 41 of the fourth multiplexer 303 is input. Selects two-sample delayed image data from the third sample memory 301 and provides them to the input terminals I0 of the ninth to fifteen multipliers 43 to 49 and the ninth selector 57, and the eighth selector. 42 selects the current image data input through the second image input terminal 200a and provides it to the 16th to 22nd multipliers 50 to 56.

Accordingly, the ninth to fifteenth multipliers 43 to 49 multiply two-sample delayed image data by differently set coefficient values and provide them to the ninth selector 57 in the manner described above. The 22 multipliers 50 to 56 multiply the current image data by different coefficient values and provide them to the tenth selector 58.

Accordingly, the ninth and tenth selectors 57 and 58 are three-bit coefficient control signals S1 provided from the first selector 28 of the first multiplexer 204d in the same manner as described above. -S3) selects the current and two sample delayed image data interpolated through each multiplier for each sample section and provides the 8-bit first data summing unit 206e.

Therefore, the first data summing unit 206e adds the interpolated current image data and one sample delayed image data or the current image data and two sample delayed image data to output through the output terminal 210. 3 or 7: 8 Interpolated image data can be obtained.

FIG. 10 shows the present invention in which the two line memories are used in parallel so that one line memory section can select an uninterpolated portion and the other memory section selects an effective image section for interpolation. Another embodiment of the expansion device, as shown in FIG. 2, generates a second clock CLK11 whenever the horizontal synchronization signal Hsy is input through the second synchronization input terminal 401. A generator 402; A second clock counter unit 403 for generating a first selection signal S11 by counting the second clock CLK11 generated by the second clock generator 402 to a set value; The second clock is generated by receiving the first selection signal S11 generated by the second clock counter unit 403 as a write enable signal WE and generating digital image data input through the third image input terminal 400. A third line memory unit 404 which is first-in first-out in synchronization with the second clock CLK11 of the unit 402; A second counter unit 406 which is a T-flip-flop that receives the second clock CLK11 from the second clock generator 402 and generates a one-bit second selection signal S12 every clock; ; A first switching unit 407 for alternately switching digital image data input through the third image input terminal 400 by the second selection signal S12 of the second counter unit 406; The image data input from the first switching unit 407 is alternately synchronized with the fourth and fifth flip flops 408a and 408b in synchronization with the second clock CLK11 generated by the second clock generator 402. A data storage unit 408 for storing and outputting the data in order; A second sample that interpolates the image data input from the data storage unit 408 to differently set coefficient values, and switches them for every sample period according to the 3-bit coefficient control signals S1 to S3 inputted from the outside. An interpolation section 409; A fourth line memory unit 410 which first-in-first-out is synchronized with the image data interpolated by the second sample interpolator 409 in synchronization with the second clock CLK11 generated by the second clock generator 402; The first selection signal S11 provided from the second clock counter unit 403 to each of the 8-bit image data and the set ground potential of the two lines provided from the third and fourth line memory units 404 and 410. The second switching unit 405 is sequentially selected by the output unit 412 to be output to the output terminal 412.

In the above, the second sample interpolator 409 has coefficient values of 1/8, 2/8, 3/8, 4 / to image data input from the fourth flip-flop 408a of the data storage unit 408, respectively. 23rd to 29th multipliers 59 to 65 multiplying by 8, 5/8, 6/8, and 7/8 to output the multiplication results; Count values 7/8, 6/8, 5/8, 4/8, 3/8, 2/8, and 1 / of image data input from the fifth flip-flop 408b of the data storage unit 408, respectively. A thirty-th thirty-sixth multiplier (66-72) for multiplying and outputting eight; 3-bit coefficient control signal (S1-S3) input from the outside of the 7-bit image data obtained from the 23rd to 29th multipliers (59 to 65) and the 1-bit image data input from the fourth flip-flop (408a) An eleventh selector 73 for sequentially selecting and outputting every sample by the " The 7-bit image data and the 1-bit ground potential obtained from the 30 th to 36 th multipliers 66 to 72 are sequentially selected for each sample by the 3-bit coefficient control signals S1-S3 input from the outside. A twelfth selector 74 for outputting; A second data summing unit 410 which adds two image data of 8 bits selected by the eleventh and twelfth selecting units 73 and 74 to provide to the fourth line memory unit 411.

Thus, the operational effects of the present invention configured as follows.

First, when the horizontal synchronous signal Hsy is input through the second synchronous input terminal 401, the second clock generator 402 generates the second clock CLK11 whenever the horizontal synchronous signal Hsy is input. The fourth and fifth flip-flops 408a of the second clock counter unit 403, the third and fourth line memory units 404 and 411, the second counter unit 406, and the data storage unit 408. 408b).

The second clock counter unit 403 counts the second clock CLK11 input from the second clock generator 402 to a set value, and in the compression mode, the horizontal retrace section, the side panel section, and the effective video section section. As shown in (a) of FIG. 2, the first select signal S11 is divided and provided to the third line memory unit 404 and the second switching unit 405, which will be described later. The horizontal regression section, the image removal section and the effective image section are provided as shown in (b) of FIG. 2.

The second counter unit 406 changes the second selection signal S12 into high potential and low potential whenever the second clock CLK11 is input from the second clock generator 402. The switching unit 407 is provided.

At this time, when the digital image data is input through the third image input terminal 400, the third line memory unit 404 records the first selection signal S11 generated by the second clock counter unit 403. The input digital image data, which is received as the enable signal WE and not interpolated, is provided to the second switching unit 405 in synchronization with the second clock CLK11 of the second clock generator 402.

In addition, the first switching unit 407 is switched every line by the second selection signal S12 provided from the second counter unit 406 to receive the image data input through the third image input terminal 400. The fourth flip-flop 408a and the fifth flip-flop 408b of the data storage unit 408, which is a D-flip flop, are alternately input.

The fourth and fifth flip-flops 408a and 408b of the data storage unit 408 may output image data inputted alternately from the first switching unit 407 to the second clock generator 402. It is stored in synchronization with the clock CLK11.

That is, as shown in (a) of FIG. 2, since the image data should be compressed by 3/4 in the actual image section, the samples are alternately recorded in the fourth and fifth flip flops 408a and 408b during the image section. do.

Samples of the image data recorded in the fourth and fifth flip-flops 408a and 408b of the data storage unit 408 are alternately provided to the second sample interpolator 408.

When the second sample interpolator 409 receives samples (pixels) of image data in alternating order from the fourth and fifth flip-flops 408a and 408b of the data storage unit 408, the second sample interpolator 409 uses different coefficient values. Multiply by and select a sample of each image data obtained in this way to synthesize each line.

That is, the one-sample delayed image data from the fourth flip-flop 408a of the data storage unit 408 is counted by 1/8, 2/8, 3 in the 23rd through 29th multipliers 59 through 65, respectively. / 8, 4/8, 5/8, 6/8, 7/8 are multiplied and provided to the input terminals I1-I7 of the eleventh selector 73 and directly provided to the input terminal I0, The image data delayed by one sample from the fifth flip-flop 408b has coefficient values of 7/8, 6/8, 5/8, 4/8, 3/8, and 2 in the 30th to 36th multipliers 66 to 72, respectively. / 8, 1/8 are multiplied and provided to the twelfth selector 74.

The eleventh selector 73 includes image data delayed by one sample in the fourth flip-flop 408a by a 3-bit coefficient control signal S1-S3 inputted in the same manner as in FIG. The image data obtained by the multiplier 23 to 29 multiplier 59 to 65 are selected and output for each line, and the twelfth selector 74 also has the image data obtained by the thirty to 36 multiplier 66 to 72 and its own ground. The potential is selected for each line and provided to the second data summing unit 410.

Accordingly, the second data summing unit 410 adds 8-bit image data selected and input for each line from the eleventh and twelfth selecting units 73 and 74 to add the fourth line memory unit 411. To be provided.

The fourth line memory unit 411 first-in first-in first-out the image data interpolated by the second data summing unit 410 by the second clock CLK11 of the second clock generator 402. 405.

In this case, as described above, the second switching unit 405 selects the first selection signal S11 of the second clock counter unit 403 according to the horizontal retrace section, the side panel section, and the effective video section in the compression mode. Selects the image data of the third line memory unit 404, the ground potential, the image data of the second line memory unit 411, and the ground potential, and outputs them through the output terminal 412. 3, only image data of the fourth line memory units 404 and 411 are sequentially selected and output through the output terminal 412, thereby obtaining horizontally converted image data.

11 is a block diagram of a TV screen horizontal compression / extension device according to sampling or overlapping according to the present invention. As shown therein, a horizontal synchronous signal Hsy from the third synchronous input terminal 410 is illustrated. A third clock generator 502 generating a third clock CLK21 each time) is inputted; A third clock counter unit 505 for generating a one-bit selection signal S13 by counting the third clock CLK21 generated by the third clock generator 502 to a set value; A third counter unit 506 for counting the third clock CLK21 generated by the third clock generator 502 and outputting four bits Q0-Q3; The third read unit 506 generates a third read enable signal RE3 and a fourth write enable signal WE4 by logicalizing the 4-bit value counted by the third counter unit 506 and is input from an external control terminal 509. A logic control unit 507 for generating a reset signal REST in accordance with the coefficient selection signal N / CS to reset the third counter unit 506; The third read enable signal RE3 generated from the logic control unit 507 is received by receiving the one-bit selection signal S13 generated by the third clock counter unit 505 as the third write enable signal WE3. A fifth line memory unit 503 configured to receive and store and output the image data input through the fourth image input terminal 500 in synchronization with the third clock CLK21 of the third clock generator 502; A sixth line memory unit 504 for storing and outputting image data sequentially input from the fifth line memory unit 503 according to the fourth write enable signal WE4 generated by the logic controller 507; ; A digital image that is switched according to the selection signal S13 generated by the third clock counter 505 and interpolated through the output terminal 510 by selecting image data or ground potential of the sixth line memory unit 504. The third switching unit 508 outputs data.

The logic controller 507 includes: a third logical product inversion element 507a for performing logical AND inversion on the outputs Q0 and Q1 of the third counter unit 506; A third inverting element (507c) for inverting the output (Q3) of the third counter portion (506); A logic sum element 507b for generating a third read enable signal RE3 by logically combining the outputs Q0-Q2 of the third counter portion 888 and the output of the third inverting element 507c; Providing or blocking the third read enable signal RE3 of the logic sum element 507b to the fifth line memory unit 503 according to the coefficient selection signal N / C input from an external control terminal 509. A fourth switching unit 507d; The output Q3 of the third counter unit 506 is supplied to and disconnected from the reset terminal of the third counter unit 506 according to the coefficient selection signal N / C input from the external control terminal 509. It consists of a 5th switching part 507e.

In this way, in the present invention configured, horizontal compression and stretching are performed by deducting a sample in the case of compression and overlapping the sample in the case of stretching.

In case of compression, the 4-bit third counter unit 506 outputs coefficients from 0 to 3 through its outputs Q0 and Q1, and from 0 to 8 through outputs Q0-Q3 when it is decompressed. Get the coefficient output of

At this time, when the output (Q3) of the 4-bit third counter unit 506 is high potential, if the reset through the fifth switching unit (507e) is a module-9 counter.

In the case of compression, the low potential is applied to the reset terminal of the third counter portion 506, so that it is not necessary to reset it.

In the case of compression, when the output Q0 (Q1) of the third counter unit 506 is 11, that is, the fourth section, the input image data is not written to the sixth line memory unit 504. The fourth write enable signal WE4 is placed at low potential through the third logical inversion element 507a to perform 4: 3 rounding.

In the case of the decompression, when the output (Q3, Q2, Q1, Q0) of the third counter unit 506 is 1000, that is, in the ninth section, the data is not read from the fifth line memory unit 503 and the previous data is not read. The third readout enable signal RE3 is placed at low potential through the third inverting element 507c, the logic sum element 507b, and the fourth switching unit 507d so as to be transferred to the sixth line memory unit 504 as it is. Each time we do the 8: 9 redundancy by having the last sample duplicated once more.

Here, performing 8: 9 redundancy instead of 7: 8 causes the cinema signal having an aspect ratio of 2: 1 to be displayed more accurately on a 16: 9 monitor, regardless of hardware characteristics.

Therefore, the rounding or overlapping ratio can be arbitrarily adjusted according to the input image data.

The selection signal S13 and the third switching unit 508 output from the third clock counter unit 505 are the same as in FIG. 10.

In the expanded embodiment of the present invention, when the sample memory is a line memory and the line memory is a field memory, the video signal can be vertically compressed and decompressed.

As described in detail above, according to the present invention, when a 4: 3 video signal or a 2: 1 cinema video signal is received by a 16: 9 wide television receiver, two lines are written and read out as a single clock. By performing horizontal compression and decompression of the video signal, not only the hardware is simplified as a whole, but also the compression and decompression ratio can be expanded in various ways, and the system can be operated more stably. By using field memory instead of line memory, it is possible to compress and expand in the horizontal as well as the vertical direction, so that the aspect ratio of the video signal can be freely changed with a single clock.

Claims (15)

Clock generation means for generating a clock each time a horizontal synchronization signal is input; Clock counting means for counting a clock of the clock generating means to a set value and generating a first write enable signal; The clock obtained by the clock generating means is counted every sample according to the coefficient selection signal input according to horizontal compression and horizontal extension to generate a predetermined bit coefficient control signal, and the respective coefficient values and the coefficient selection signal are logically generated. Coefficient control means for generating a first read enable signal and a second write enable signal; Receiving the first write enable signal of the clock counting means and the first read enable signal of the coefficient control means, and receiving the clock of the clock generating means as a write / read clock to record / read the input image data every line First line memory means; 4: 3 or 7: 8 interpolation between the current image data and the previous image data inputted from the first line memory means and selects every line according to the coefficient control signal of a predetermined bit generated by the coefficient control means. Sample interpolation means for outputting; The second write enable signal of the coefficient control means and the set second read enable signal are input, the clock of the clock generating means is input to the recording / reading clock, and the interpolated image data by the sample interpolation means is recorded every line. Second line memory means for outputting; A screen aspect ratio converter, characterized in that consisting of. 2. The apparatus of claim 1, wherein the coefficient control means comprises: a counter for generating a 3-bit coefficient control signal by sequentially counting a clock obtained by the clock generating means into first to third flip-flops; An exclusive-OR device for performing an exclusive OR on the lower two bit values of the three bits obtained by the counter; First multiplexing means for receiving a 3-bit value obtained from the counter and a 1-bit value obtained from an exclusive logical sum element as predetermined bits, respectively, and multiplexing the same; Enable generation means for generating a first read enable signal and a second write enable signal by logicalizing a lower two-bit value of the three bits obtained by the counter and the coefficient selection signal; Screen aspect ratio converter, characterized in that consisting of. 3. The apparatus of claim 2, wherein the first multiplexing means receives the 1 bit value of the exclusive logical sum element and the 1 bit value of the first and second flip flops as the lower 3 bit values, and each 1 of the first to third flip flops. A first selector which receives a bit value as an upper 3 bit value and selects the lower 3 bits or the upper 3 bits according to the coefficient selection signal and outputs the result as a coefficient control signal; And a second selector which selects each 1-bit value counted by the first and third flip-flops according to a coefficient selection signal and outputs it as a coefficient control signal. 3. The apparatus of claim 2, wherein the enable generating means comprises: a first inverting element for inverting the output of the second flip flop; A first logical inverse device for generating a first read enable signal by performing an AND operation on the output of the first flip-flop, the output of the first inverting device, and a coefficient selection signal; A second inverting element for inverting the coefficient selection signal; And a second logical inverting device for generating a second write enable signal by performing an AND operation on the output of the second inverting device and the outputs of the first and second flip-flops. The screen aspect ratio converting apparatus according to claim 1, wherein the second read enable signal of the second line memory means is always enabled. 2. The apparatus of claim 1, wherein the sample interpolation means comprises: a sample memory for storing image data input from the first line memory means every line; Second multiplexing means for multiplexing and outputting previous image data obtained from said sample memory and current image data obtained from said first line memory means according to the coefficient control signal obtained by said coefficient control means; Line multiplication means for multiplying each of the current or previous video data obtained by the second multiplexing means with coefficient values set differently from each other; Each image data obtained from the line multiplication means and previous image data directly input from the second multiplexing means and their own set values are sequentially selected for each line according to the coefficient control signal input from the coefficient control means. Third multiplexing means for outputting different values; And a data summing means for summing two different image data obtained by multiplexing by said third multiplexing means and providing it to the second line memory means. 7. The apparatus according to claim 6, wherein the second multiplexing means comprises third and fourth selectors for selecting the current image data or the previous image data stored in the sample memory by the one-bit coefficient control signal provided from the coefficient control means. Screen aspect ratio converter characterized in that. The apparatus of claim 7, wherein the third and fourth selectors select different image data by the same 1-bit coefficient control signal. 7. The apparatus according to claim 6, wherein the line multiplication means multiplies the image data input from any one of the second multiplexing means by the coefficient values 1/8, 2/8, 3/8, 4/8, respectively. To fourth multiplier; And fifth to eighth multipliers for multiplying the coefficient values 4/8, 5/8, 6/8, and 7/8 by the image data input from the other selector of the second multiplexing means. One screen aspect ratio inverter. 7. The image input apparatus according to claim 6, wherein the third multiplexing means multiplies the current or previous image data directly input from the third selector with a coefficient value set in the first to fourth multipliers and the sixth to eighth multipliers. A fifth selector which selects data every line according to a 3-bit coefficient control signal inputted from the coefficient control means and provides the data to the data summing means; And a sixth selector which selects the ground potentials of the first to third multipliers, the fifth to eighth multipliers, and its own ground potential in each line according to the three-bit coefficient control signal obtained from the coefficient control means and provides them to the data summing means. Screen aspect ratio converter characterized in that. 2. The apparatus of claim 1, wherein the sample interpolation means comprises: a sample memory for delaying two sample delays of image data provided from the first line memory means; The image data that is switched by the luminance signal and the color signal input from the outside and is input from the first line memory means is selected from the image data delayed by two samples in the sample memory, or one sample delayed in the current image data and the sample memory. First multiplexing means for selecting and outputting image data; Line multiplication means for multiplying and outputting coefficient values different from one sample delayed image data selected by said first multiplexing means and current image data or two sample delayed image data and current image data; The image data obtained by interpolation in the line multiplication means, the image data directly input from the first multiplexing means, and its ground potential are multiplexed to the 3-bit coefficient control signal obtained by the coefficient control means and provided to the data summing means. A screen aspect ratio converting apparatus, characterized by comprising multiplexing means. 12. The apparatus of claim 11, wherein the line multiplying means comprises a coefficient value of 1/8, 2/8, 3/8, 4/8, 5/8, First to seventh multipliers for multiplying 6/8 and 7/8; Multiplying coefficient values 7/8, 6/8, 5/8, 4/8, 3/8, 2/8, 1/8 by one sample delayed image data or current image data selected by the first multiplexing means; And an aspect ratio conversion device as set forth in an eighth to fourteenth multiplier. The apparatus of claim 11, wherein the external luminance signal and the color signal are input as a 1-bit value. 12. The apparatus according to claim 11, wherein the second multiplexing means is sequentially executed every line by the three-bit coefficient control signal in the order of current or previous image data obtained from the first multiplexing means and image data obtained from the first to seventh multipliers. A first selection unit for selecting; And a second selector which sequentially selects each line by the three-bit coefficient control signal according to the set ground potential and the current or previous image data sequence obtained from the eighth to fourteenth multipliers. . 12. The method of claim 11, wherein the sample interpolation means interpolates the image data delayed by one sample and the current image data when the external signal is a luminance signal, and interpolates the image data delayed by two samples and the current image data when the external signal is a color signal. Screen aspect ratio converter, characterized in that.