KR0146069B1 - Method of fabricating self-aligned bipolar transistors by using nitride films - Google Patents
Method of fabricating self-aligned bipolar transistors by using nitride filmsInfo
- Publication number
- KR0146069B1 KR0146069B1 KR1019890007490A KR890007490A KR0146069B1 KR 0146069 B1 KR0146069 B1 KR 0146069B1 KR 1019890007490 A KR1019890007490 A KR 1019890007490A KR 890007490 A KR890007490 A KR 890007490A KR 0146069 B1 KR0146069 B1 KR 0146069B1
- Authority
- KR
- South Korea
- Prior art keywords
- base
- layer
- emitter
- forming
- polysilicon layer
- Prior art date
Links
- 150000004767 nitrides Chemical class 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
Abstract
내용없음No content
Description
제 1 도 및 제 2 도는 종래의 자기정렬 바이폴라 트랜지스터의 제조 공정도.1 and 2 are manufacturing process diagrams of a conventional self-aligned bipolar transistor.
제 3 도의 (a) 내지 (f)는 본 발명의 질화막을 이용한 자기정렬 바이폴라 트랜지스터의 제조공정도.3A to 3F are manufacturing process diagrams of a self-aligned bipolar transistor using the nitride film of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 기판 22 : 질화막층21 substrate 22 nitride layer
23 : 필드산화막 24 : 외부확장베이스23: field oxide film 24: external extension base
25 : 산화막층 26 : 진성베이스25 oxide layer 26 intrinsic base
27 : 폴리실리콘층 28 : 측벽27 polysilicon layer 28 sidewalls
29 : 에미터정션29 emitter junction
본 발명은 자기정렬(self-align)바이폴라 트랜지스터에 관한 것으로, 특히 질화막(Nitride film)을 이용하여 고속의 집적소자 제조에 적용할 수 있게한 질화막을 이용한 자기정렬 바이폴라 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-aligned bipolar transistor, and more particularly, to a method of manufacturing a self-aligned bipolar transistor using a nitride film that can be applied to a high speed integrated device fabrication using a nitride film.
제 1 도는 종래의 자기정렬 바이폴라 트랜지스터의 제조 공정도로서, 제 1 도의 (a)에 도시된 바와같이 기판(1)상에 붕소(Boron)가 도핑된 폴리실리콘을 증착하여 폴리실리콘층(2)을 형성하고, 그 폴리실리콘층(2)위에 SiO₂의 산화막(3)을 증착 형성한다.FIG. 1 is a manufacturing process diagram of a conventional self-aligned bipolar transistor. As shown in FIG. 1A, boron-doped polysilicon is deposited on a substrate 1 to form a polysilicon layer 2. And an oxide film 3 of SiO2 is deposited on the polysilicon layer 2.
이후, 제 1 도의 (b)와 같이 에미터 마스크를 이용하여 상기 산화막(3)과 폴리실리콘층(2)을 에칭한후 제 1 도의 (c)와 같이 상기 SiO₂의 산화막(3)을 약 200Å 정도의 열산화시키고, 그 위에 화학증착방법으로 SiO₂를 증착하여 2000Å정도의 산화막(3)을 형성한다.Thereafter, the oxide film 3 and the polysilicon layer 2 are etched using an emitter mask as shown in FIG. 1 (b), and then the oxide film 3 of SiO 2 as shown in FIG. It is thermally oxidized to a degree, and SiO 2 is deposited on it by a chemical vapor deposition method to form an oxide film 3 of about 2000Å.
이때, 불순물(dopant)베이스가 P+(5)로 도핑된다.At this time, the dopant base is doped with P + (5).
이후, 제 1 도의 (d)와 같이 리액티브 이온 에칭(RIE)에 의하여 상기 폴리실리콘층(2)의 측벽을 제외한 에미터영역의 산화막(4)을 제거한 후 이온주입(Implantation)공정과 드라이브-인 공정에 의해 에미터(6)와 진성(intrinsic)베이스(7)을 형성하였다.Subsequently, as shown in FIG. 1D, the oxide film 4 of the emitter region except for the sidewall of the polysilicon layer 2 is removed by reactive ion etching (RIE), followed by an implantation process and a drive- The emitter 6 and the intrinsic base 7 were formed by the phosphorus process.
제 2 도의 (a) 내지 (c)는 제 1 도의 제조공정을 변형한 종래의 자기정렬 바이폴라 트랜지스터의 제조공정을 나타낸 것으로, 우선 제 2 도의 (a)와 같이 기판(11)상에 폴리실리콘(12)을 증착에 의해 형성한 후 붕소를 주입하고, 그 폴리실리콘층(12)위에 SiO₂를 증착하여 산화막(13)을 형성한 다음 에미터영역을 정의한 후 정의된 에미터영역을 에칭한다.2 (a) to 2 (c) show a manufacturing process of a conventional self-aligned bipolar transistor modified from the manufacturing process of FIG. 1, first, as shown in FIG. 2 (a). 12) is formed by evaporation, boron is implanted, SiO2 is deposited on the polysilicon layer 12 to form an oxide film 13, and then the emitter region is etched after defining the emitter region.
이후, 제 2 도의 (b)와 같이 상기에서 에칭된 부위에 SiO₂의 측벽(14)을 형성한 다음 폴리실리콘층(15)을 증착에 의해 형성한다.Subsequently, as shown in FIG. 2 (b), a sidewall 14 of SiO 2 is formed on the etched portion, and then a polysilicon layer 15 is formed by vapor deposition.
그런 다음 제 2 도의 (c)와 같이 베이스 주입을 하여 어닐링(annealing)하고, 에미터 이온주입후에 어닐링하여 에미터를 형성하였다.Then, as shown in (c) of FIG. 2, the base was implanted and annealed, followed by annealing after emitter ion implantation to form an emitter.
그러나, 이러한 종래의 제조방법에 있어서는 폴리실리콘층 에칭시에 베이스로 형성된 실리콘층이 오버에칭되고, 베이스연결폴리와 에미터연결폴리의 절연을 의하여 산화막의 측벽이 필요하게 되므로 공정이 복잡하게 되고, 트랜지스터의 신뢰성이 떨어지며, 또한 베이스접촉을 폴리로 하므로 베이스저항이 증가되는 단점이 있었다.However, in this conventional manufacturing method, the silicon layer formed as a base is overetched during the polysilicon layer etching, and the sidewall of the oxide film is required by the insulation of the base connection poly and the emitter connection poly, which makes the process complicated. The reliability of the transistor is low, and the base resistance is increased because the base contact is made of poly.
본 발명은 이러한 종래의 단점을 해결하기 위하여, 외부확장(Extrinsic)베이스를 이온주입으로 형성하고, 베이스-에미터간에 두꺼운 열산화막을 형성하므로써 공정제어가 용이하고 베이스-에미터간의 절연층 신뢰성이 향상되며, 베이스층이 형성될 실리콘층이 오버에칭되지 않고, 에미터의 면적을 쉽게 조절할 수 있도록 하는 질화막을 이용한 자기정렬 바이폴라 트랜지스터 제조방법을 창안한 것으로, 이를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.In order to solve the above disadvantages, the present invention forms an extrinsic base by ion implantation, and forms a thick thermal oxide film between the base and the emitter, thereby facilitating process control and increasing the reliability of the insulating layer between the base and the emitter. The invention provides a method for fabricating a self-aligned bipolar transistor using a nitride film to improve the area of the emitter without over-etching the silicon layer on which the base layer is to be formed, which will be described in detail with reference to the accompanying drawings. As follows.
제 3 도의 (a) 내지 (f)는 본 발명의 질화막을 이용한 자기정렬 바이폴라 트랜지스터의 제조공정도로서, 제 3 도의 (a)에 도시한 바와같이 기판(21)상에 질화막층(22)을 이용하여 액티브(Active)영역을 정의한 후 열산화에 의해 필드산화막(23)을 형성한다.3A to 3F are manufacturing process diagrams of a self-aligned bipolar transistor using the nitride film of the present invention, and the nitride film layer 22 is used on the substrate 21 as shown in FIG. After defining an active region, the field oxide layer 23 is formed by thermal oxidation.
이후, 제 3 도의 (b)와같이 베이스마스크를 이용하여 상기 질화막층(22)을 에칭한 다음 그 질화막층(22)패턴을 마스크로 사용하여 P+이온을 주입하여 외부확장베이스(24)를 형성한 후 제 3 도의 (c)와 같이 열산화에 의하여 상기 외부확장베이스(24)위에 산화막층(25)을 형성한다.Thereafter, as shown in FIG. 3 (b), the nitride layer 22 is etched using a base mask, and then P + ions are implanted using the nitride layer 22 pattern as a mask, thereby forming the external extension base 24. After forming, the oxide layer 25 is formed on the external extension base 24 by thermal oxidation as shown in FIG.
다음으로 제 3 도의 (d)와 같이 상기 질화막(22)을 제거한 후 진성베이스(26)를 형성한다.Next, the intrinsic base 26 is formed after removing the nitride film 22 as shown in FIG.
이후, 제 3 도의 (e)와 같이 상기 진성베이스(26)위에 폴리실리콘을 증착한 후 패터닝하여 폴리실리콘층(27)을 형성한 다음 그 폴리실리콘층(27)의 옆에 측벽(28)을 형성하여 에미터영역을 정의하고, 이후 제 3 도의 (f)와같이 상기 폴리실리콘층(27)의 하부에 에미터정션(29)을 형성하여 본 발명에 따른 바이폴라 트랜지스터를 제조한다.Thereafter, as shown in FIG. 3E, polysilicon is deposited on the intrinsic base 26, and then patterned to form a polysilicon layer 27, and then sidewalls 28 are formed next to the polysilicon layer 27. To form an emitter region, and then, as shown in FIG. 3 (f), an emitter junction 29 is formed below the polysilicon layer 27 to manufacture a bipolar transistor according to the present invention.
이와같이 제조되는 바이폴라 트랜지스터에 있어 외부확장베이스(24)영역은 베이스 접촉을 의하여 사용되고, 외부확장베이스(24)영역 위의 산화막층(25)은 폴리실리콘층(27)과 외부확장베이스(24)사이를 절연 시켜주게 된다.In the bipolar transistor manufactured as described above, the region of the external extension base 24 is used by the base contact, and the oxide layer 25 on the region of the external extension base 24 is formed between the polysilicon layer 27 and the external extension base 24. It insulates.
이때, 상기 산화막층(25)에 의한 기생(Parasitic)캐패시턴스를 감소시키기 위해서는 그의 두께가 두꺼워야 한다.At this time, in order to reduce the parasitic capacitance caused by the oxide layer 25, its thickness should be thick.
한편, 상기 폴리실리콘층(27)은 에미터의 접촉으로 사용되고 전류이득(hfe)를 증가시키게 된다.On the other hand, the polysilicon layer 27 is used as the contact of the emitter to increase the current gain (h fe ).
그리고, 상기 측벽(28)은 실제로 베이스와 에미터영역의 절연기능을 하지 않고, 그 측벽(28)이 존재하지 않아도 본 발명의 구성에 영향을 주지 않게 된다.The side wall 28 does not actually insulate the base and emitter regions, and does not affect the configuration of the present invention even if the side wall 28 does not exist.
이상에서 상세히 설명한 바와같이 본 발명은 외부확장베이스를 이온주입으로 형성할 수 있고, 베이스-에미터간에 두꺼운 열산화막을 형성할 수 있으므로 공정의 제조가 용이하고, 베이스-에미터간의 절연층의 신뢰성이 향상되며, 베이스층이 형성될 실리콘층에 오버에칭이 발생되지 않고, 에미터의 면적을 질화막의 영역정의에 의해 쉽게 조절할 수 있는 효과가 있다.As described in detail above, the present invention can form the external extension base by ion implantation, and can form a thick thermal oxide film between the base and the emitter, thereby facilitating the manufacture of the process and the reliability of the insulating layer between the base and the emitter. This is improved, and overetching is not generated in the silicon layer on which the base layer is to be formed, and the area of the emitter can be easily adjusted by the area definition of the nitride film.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890007490A KR0146069B1 (en) | 1989-05-31 | 1989-05-31 | Method of fabricating self-aligned bipolar transistors by using nitride films |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890007490A KR0146069B1 (en) | 1989-05-31 | 1989-05-31 | Method of fabricating self-aligned bipolar transistors by using nitride films |
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| Publication Number | Publication Date |
|---|---|
| KR900019255A KR900019255A (en) | 1990-12-24 |
| KR0146069B1 true KR0146069B1 (en) | 1998-08-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019890007490A KR0146069B1 (en) | 1989-05-31 | 1989-05-31 | Method of fabricating self-aligned bipolar transistors by using nitride films |
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| Country | Link |
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| KR (1) | KR0146069B1 (en) |
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1989
- 1989-05-31 KR KR1019890007490A patent/KR0146069B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR900019255A (en) | 1990-12-24 |
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