KR0145046B1 - Digital signal reproducing apparatus - Google Patents

Abstract

The present invention relates to a digital signal reproducing apparatus, and more particularly to a detector. The detector comprises: a phase-locked loop for extracting a clock signal, a 1-bit analog / digital converter for converting the clock signal as a sampling clock signal, and a correlation signal for determining and outputting the correlation signal by correlation coefficients; An in-phase three detector for detecting in-phase, a comparator for comparing the in-phase value with a predetermined threshold, outputting a comparison value, a delay delaying at least one clock, and decoding means for decoding in response to the comparison value. Characterized in that it has the effect that the accurate recovery of the synchronization signal is possible.

Description

Digital signal reproducing device

1 is a block diagram for explaining a general digital signal reproducing apparatus;

2 is a block diagram for explaining the detector of FIG. 1;

3 is a block diagram for explaining a synchronization signal recovery circuit of FIG. 2;

4 is a block diagram for explaining another detector of FIG. 1;

5 is a block diagram for explaining a synchronization signal recovery circuit of FIG. 4;

6 is a block diagram for explaining a synchronization signal recovery circuit of FIG. 4 according to the present invention;

7 is an input / output relationship table for explaining the input / output relationship of the N-bit detector of FIG. 6;

8 is a circuit which can replace the comparator of the synchronization signal recovery circuit of FIG. 6 according to the present invention;

9 is another circuit that can replace the comparator of the synchronization signal recovery circuit of FIG. 6 according to the present invention;

FIG. 10 shows a block diagram for explaining another synchronization signal recovery circuit of FIG. 4 according to the present invention.

11 is an input / output relationship table for explaining the input / output relationship of another (N-x) bit detector of FIG. 10 according to the present invention;

12 is a block diagram for explaining a detector according to the present invention;

FIG. 13 is a block diagram for explaining a synchronization signal recovery circuit of FIG. 12 according to the present invention; FIG.

14 is a circuit that can replace the in-phase detector and the comparator of FIG. 13;

FIG. 15 is an input / output relationship table for explaining the input / output relationship of the (M-x) block detector of FIG. 14;

FIG. 16 is another circuit that can replace the in-phase detector and comparator of FIG. 13;

17 is a block diagram for explaining another detector according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital transmission / reception or recording / reproducing apparatus, and more particularly to a detector for detecting a synchronization signal recorded or transmitted.

Digital transmission / reception or recording / playback devices, in particular digital videotape (D-VCR), digital audiotape (DAT), compact disc (CD), minidisc (MD) and digital video recorder (D-VDR) In order to restore the digital transmission or recorded data, first, the synchronization signal, which is a reference signal, is first restored. At this time, even if no error occurs during digital transmission or recording, accurate digital data cannot be detected unless the accurate synchronization signal is restored. In addition, even when an error occurs in a synchronization signal during digital transmission or recording, much effort has been made to compensate for such an error and restore an accurate synchronization signal.

1 is a block diagram for explaining a general digital magnetic recording / reproducing apparatus.

A general digital magnetic recording / reproducing apparatus first converts an externally applied video signal into a digital signal through an analog / digital converter 1. At this time, since the signal band of the converted digital signal is so wide that a large number of necessary bands are required for recording, image compression is performed through the image compressor 2 in an amount suitable for recording. Then, the compressed picture signal is encoded by the error encoder 3 to correct an error in reproduction. At this time, since the encoded signal is not suitable for the channel but only a small recording frequency, it is amplified by the recording amplifier 5 through the recording encoder 4 at a predetermined gain ratio in order to encode the channel appropriately, and then, the encoded signal is stored in the storage body 10. Record it. In this case, the digital transmission / reception apparatus may be a transmission line or a transmission medium instead of the storage body 10. Subsequently, the data recorded in the storage body 10 is read and amplified to a predetermined gain through the reproducing amplifier 11, the signal is detected by the detector 12, and error correction is performed by the error corrector 13. . The error corrected signal is then decoded through the image decoder 14 and converted into an analog signal through the digital / analog converter 15 and output.

The detector 12 will be described in detail with reference to FIG. 2.

The conventional detector 12 operating at the multi-value and binary value of FIG. 2 receives the amplified signal from the regenerative amplifier 11 of FIG. 1 and converts the signal into a digital scene through the analog-to-digital converter 21. At this time, the phase-locked loop 24 extracts a clock signal from the amplified signal and transfers the clock signal to the analog / digital converter 22 as a sampling clock. Subsequently, the digitally converted signal is input to the synchronous restoring circuit 22, and the extracted synchronous signal is input to the reference signal of the decoder 23 through the terminal 25, and the digitally converted signal is delayed to the terminal of the decoder 23. Entered through 26. At this time, the decoder 23 decodes the digitally converted signal on the basis of the synchronization signal. Therefore, if the synchronization signal cannot be restored through the synchronization recovery circuit 22, even if no error occurs on the channel, the normal digitally converted signal cannot be decoded.

In order to learn more about the synchronous restoration circuit 22 will be described with reference to FIG.

3 is a conventional synchronous restoring circuit 22 that operates at multiple values and binary values, and includes a correlator 31 and a comparator 32. FIG. At this time, the correlator 31 finds the correlation of the input signal, and when the correlation is large, the output value of the adder 33 is large and conversely, when the correlation is small, the output value of the adder 33 is small. The correlation coefficients b ₀ , b ₁ , b ₂ .......... b _n-1 are already known values for recording, so use them. n-bit input signal is input to a _k a synchronization recovery circuit 22, a delay storage unit _{(A 1 ~ A n-1} ) are delay stored in _{a k-1, a k-} 2, ........ .., a _{k-n + 1} (for example, a _k-2 is k-2nd data). Subsequently, each of the delayed stored values is multiplied by the correlation coefficients b ₀ , b ₁ , b ₂ ... B _n-1 and input to the adder 33. Subsequently, the added value C _k and the threshold C are input to the comparator 32, and the comparison value dk is output after the comparison. Since it takes a long time to receive the digitally converted n-bit signal and process it by the conventional synchronous restoration circuit 22, a high-speed processing, that is, a signal having a high write bit rate, is very difficult in real time and considerably complicated in hardware. There was a problem of increasing.

In addition, to describe another example of the conventional detector 12 will be described with reference to FIG.

4 is a detector 12 according to another conventional example. The detector 12 of FIG. 2 is improved. The signal input to the 1-bit analog-to-digital converter 41 is three-valued, and is sampled at a clock cycle of the phase-locked loop 44. Output by 1 bit. At this time, the output value of the 1-bit digital-to-analog converter 41 has two values. Therefore, the binary operation can be performed by partially changing the synchronous restoring circuit 22 of the detector 12 of FIG. 2 to the synchronous restoring circuit 42 as shown in FIG. Therefore, the 1-bit digital-to-analog converter 41 can be replaced by a comparator. FIG. 5 shows the synchronous restoration circuit 42 of the detector 12 of FIG. 4 in detail. Since the output of the 1-bit analog-to-digital converter 41 of FIG. 4 has a binary value, the adder 33 of FIG. And comparator 32 may be replaced with a logical AND 51. Therefore, since 1-bit operation is possible without performing n-bit operation, the recording bit rate can be increased.

However, FIG. 5 is configured by setting the threshold c of the comparator 32 of FIG. 3 to the maximum. Therefore, if an error occurs in the sync signal, the sync restore circuit 42 of FIG. 5 may fail to detect the sync signal, resulting in overall performance degradation.

Accordingly, an object of the present invention is to provide a digital signal reproducing apparatus that can accurately recover a synchronization signal even when multiple errors occur.

Another object of the present invention is to provide a digital signal reproducing apparatus with a simple circuit implementation.

In order to achieve the object of the present invention, a digital signal reproducing apparatus according to the present invention includes an analog / digital conversion means for receiving a video signal and converting it digitally, an image compression means for receiving and compressing the digitally converted signal, and compressing the compressed signal. Error encoding means for receiving error correction, recording encoding means for receiving an error encoded signal and converting the signal according to recording or transmission, recording amplifying means for receiving the amplified signal at a predetermined gain ratio and being amplified. Recording or transmission means for receiving and recording or transmitting a signal, reproducing amplification means for reading and amplifying a recorded or transmitted signal at a predetermined gain ratio, and detecting for detecting the recorded or transmitted signal upon receiving the reproduced and amplified signal. Means, error correcting means for receiving the detected signal and correcting the error; A digital signal reproducing apparatus having a video decoding means for receiving and decoding a digital signal, and a digital / analog converting means for receiving the decoded signal and converting the decoded signal into an analog signal. Phase-locked loop means for extracting a signal; 1-bit analog / digital conversion means for receiving the output signal of the reproduction amplifier means and converting the clock signal into a sampling clock signal for 1-bit digital conversion; Correlating means for receiving the 1-bit digitally converted signal and delaying the predetermined signal for a predetermined time, and determining and outputting a correlation signal by predetermined correlation coefficients; In-phase detection means for detecting the in-phase by receiving the correlation signal; Comparing means for receiving the detected in-phase signal and comparing a predetermined threshold value to output a comparison value; Delay means for receiving the delayed signal and delaying at least one clock or more; And decoding means for receiving the signal delayed by one or more clocks and decoding the signal in response to the comparison value.

In addition, in order to achieve another object of the present invention, another digital signal reproducing apparatus of the present invention, the analog / digital conversion means for receiving a video signal and digital conversion, the image compression means for receiving and compressing the digital converted signal, the compression Error encoding means for receiving the corrected signal and correcting the error, recording encoding means for receiving an error encoded signal and converting the signal appropriately for recording or transmission, and recording amplification means for receiving the encoded signal and amplifying the signal at a predetermined gain ratio. Recording or transmission means for receiving the recorded signal or transmitting the received signal, reproducing amplification means for reading and amplifying the recorded or transmitted signal at a predetermined gain ratio, and receiving the recorded amplified signal to receive the recorded or transmitted signal. Detection means for detecting, error correction means for error correction receiving the detected signal, and error correction A digital signal reproducing apparatus comprising: an image decoding means for receiving a decoded signal and decoding the decoded signal; and a digital / analog converting means for receiving the decoded signal and converting it into an analog signal. Phase-locked loop means for receiving an input and extracting a clock signal; 1-bit analog / digital conversion means for receiving the output signal of the reproduction amplifier means and converting the clock signal into a sampling clock signal for 1-bit digital conversion;

In-phase detection means for receiving the one-bit digitally converted signal and delaying the signal for a predetermined time and detecting in-phase; Correlation means for receiving the detected in-phase signal and determining a correlation signal by predetermined correlation coefficients and outputting the correlation signal; Comparison means for receiving the correlation signal and comparing the threshold value to output a comparison value; Delay means for receiving the delayed signal and delaying at least one clock or more; And decoding means for receiving the signal delayed by one or more clocks and decoding the signal in response to the comparison value.

Hereinafter, a synchronous restoration circuit according to the present invention will be described with reference to the accompanying drawings.

6 is a block diagram for explaining a synchronous restoration circuit according to the present invention.

The synchronous restoring circuit according to the present invention of FIG. 6 is an improvement of the conventional synchronous restoring circuit of FIG. 5 and replaces the logic AND 51 circuit of FIG. 5 with an N-bit detector 61 and a comparator 62. FIG. In this case, the N-bit detector 61 may be implemented as a logic circuit and a ROM. That is, the input becomes the address of the ROM and the output becomes the output of the ROM. At this time, the maximum number of output lines j is a natural number that is greater than or equal to the natural logarithm of the number of input lines N. The output value C _K of the N-bit detector 61 and the threshold value C are compared by the comparator 62 to output the _1- bit comparison value D _{K -N + 1} . FIG. 7 shows the input / output relationship in the case where N = 6 and threshold c = 5 of the N-bit detector 61 in FIG. The hatched portion indicates the portion where the synchronization signal is detected. At this time, if the values of the output value C _K and the threshold value c of the N-bit detector 61 are slightly lowered, the synchronization signal can be detected accurately even if there is an error in the synchronization signal. At this time, instead of the comparator 62 of FIG. 6, it is possible to substitute the logic AND (81, 82) and logical OR 83 circuits as shown in FIG. At this time, the number of input lines is N and the number of output lines has a natural value greater than or equal to the natural log in (N). In particular, when the threshold c of the comparator is 4, as shown in FIG. 9, one logical AND 91 can be configured. At this time, the maximum number of output lines is three.

FIG. 10 is an embodiment of another synchronous restoring circuit according to the present invention, in which the N-bit detector 61 and the comparator 62 of FIG. 6 are replaced with the (N-x) bit detector 101. FIG. The other synchronous restoring circuit of FIG. 10 is simpler in circuit implementation than in FIG. 6, and in particular, the (Nx) bit detector 101 can be implemented as a logic circuit or a ROM, and since the output is 1 bit, in particular, the larger the N, Much simpler than 6 degrees. FIG. 11 is an input / output table showing the input / output relationship of the (Nx) bit detector 101 of FIG. 10. Like FIG. 7, the number of input lines N is 6 bits and one (x = 1) error occurs in the synchronization signal. The case is shown. Therefore, since (N-x) becomes 5, a logic 'H' is detected when logically '1' of 5 bits or more, and a logic 'L' is detected otherwise. At this time, the number 32, 48, 60, 62, 63 is a case where one error occurs and the number 64 is a complete detection of the synchronization signal. At this time, even though all the synchronization signals have been transmitted without errors, it is determined that an error has occurred during transmission, and this table indicates that the synchronization signals are detected. If you want to judge the synchronization signal even if x errors occur, replace all values greater than (Nx) with H (logical 'HIGH') and replace the rest with L (logically 'LOW'). The input / output table of the (Nx) bit detector 91 when an error occurs can be obtained.

12 shows an embodiment of another detector according to the present invention, and the same parts as those of the conventional detector of FIG. 2 will be omitted.

Another detector according to the present invention of FIG. 12 is composed of a 1-bit analog / digital converter 121, a synchronization signal recovery circuit 122, a delay unit 1 123, a decoder 124, and a phase synchronization loop 125. . At this time, the synchronization signal recovery circuit 122 includes a correlator 126, an in-phase detector 127, and a comparator 128. In particular, the detector 12 of FIG. 2 described above operates normally when an error of one or two bits occurs in the synchronization signal. However, the detector 12 of FIG. 2 is not correctly detected when multiple errors, that is, errors of several bits in the synchronization signal, occur. Do not. Therefore, to improve this, an in-phase detector 127 is placed between the correlator 126 and the comparator 128 as shown in FIG. In this case, the in-phase detector 127 can be implemented by setting all the correlation coefficients to 1 in the correlator 126. That is, a method of detecting the signal when a certain type of signal is repeatedly inputted for a certain period of time It is possible to add the preceding and delayed signals over a period of time. In particular, repeated several times will increase the effect.

13 illustrates the synchronization signal recovery circuit 122 of FIG. 12 in detail. The thirteenth embodiment shows that the input signal, that is, the synchronization signal, is delayed by (M-1) times and added together. In this case, the correlator 126 may also be the correlator of FIGS. 3, 5, 6, and 8 described above. In particular, the correlator of FIG. In addition, although the in-phase detector 127 may use the basic structure of FIG. 13, a circuit is complicated as mentioned above and there exists a problem in high speed processing. Thus, by replacing the in-phase detector 127 and the comparator 128 in FIG. 13 with FIG. 14 according to the present invention, it is possible to process at a much faster and higher recording rate. That is, the adder 131 and the comparator 128 of FIG. 13 can be replaced by the (M-x) block detector 141 of FIG.

FIG. 15 shows an input / output relationship table for explaining the input / output relationship of the (M-x) block detector 141 of FIG. The input / output relationship table of FIG. 15 shows that when M = 4 and x = 1 (three delay lines ((Mx) = 3), that is, when three or more sync signal blocks are detected among four sync signal blocks, a sync signal is generated). In this case, when the inputs are all 1, that is, when all four sync signal blocks are detected, the input is included in having at least one error. Since the delay generated in FIG. 14 is a synchronization signal block unit, a delay 1 (123) is added to the correlator 126 and the decoder 124 on the main path of FIG. 12 so that the same signal is input from the decoder position. In addition, the (Mx) block detector 141 of Fig. 14 can be implemented with a logic circuit and a ROM, in particular, Fig. 15 shows a (Mx) block detector (Mx) when M = 4 and (Mx) = 3. 141) shows an input / output relationship table, and FIG. 16 shows input of FIG. It illustrates an example implementation of the (M-x) block detector 141 according to the relationship table to output logic circuit.

FIG. 17 shows another embodiment of the synchronous restoring circuit according to the present invention in which the correlator 126 and the in-phase detector 127 of FIG. 12 are interchanged.

In another synchronous restoring circuit according to the present invention of FIG. 17, the delay line 1 (123) of FIG. 12 is a significantly large delay line because it is a sync signal block unit, whereas delay 2 (171) of FIG. 17 is a bit delay. Simplification is possible.

In another embodiment of the synchronous restoring circuit, all the coefficients of the in-phase detector are all set to 1, but it is also possible to implement all of the correlators in the coefficients (not shown).

The invention particularly relates to a detector for detecting a reproduced signal. It is also apparent that it can be used to detect the transmitted signal. Therefore, the present invention is not limited to the above-described range, and the present invention is modified within the technical scope of the present invention, including a digital signal reception-only device, a digital signal playback-only device, a digital signal transmission / reception device, or a digital signal recording / reproduction device. Include an example.

As described above, the synchronous restoring circuit according to the present invention can be completely restored even when there is a partial loss of the synchronous signal. That is, when x bits are lost in the N-bit synchronous signal, it is restored using the (Nx) detector, and when x bits or more are lost in the synchronous signal, the next step is compensated again by the (Mx) block detector. There is an effect that the synchronization signal without any synchronization signal can be completely restored.

Claims (8)

A digital signal reproducing apparatus, comprising: detecting means for reproducing and amplifying a recorded digital signal and detecting the recorded digital signal from the reproduced amplified signal, wherein the detecting means receives the reproduced amplified signal and extracts a clock signal. Phase synchronous loop means; 1-bit analog / digital conversion means for receiving the reproduction-amplified signal and converting the clock signal into a sampling clock signal for 1-bit digital conversion; Correlating means for receiving the 1-bit digitally converted signal and delaying the predetermined signal for a predetermined time, and determining and outputting a correlation signal by predetermined correlation coefficients; In-phase detection means for detecting the in-phase by receiving the correlation signal; Comparing means for receiving the detected in-phase signal and comparing a predetermined threshold value to output a comparison value; Delay means for receiving the delayed signal and delaying at least one clock or more; And decoding means for receiving the signal delayed by one or more clocks and decoding the signal in response to the comparison value. 2. The apparatus of claim 1, wherein the correlation means comprises: a plurality of first delay storage means connected in series for receiving and storing the 1-bit digitally converted signal; Multiplication means for receiving the 1-bit digitally converted signal and the output signals of the first delay storage means and multiplying the corresponding correlation coefficients; And (N-x1) bit detection means for receiving the N output signals of the multiplication means and detecting when (N-x1) bit or more is a predetermined logic state according to a predetermined x1 value. Signal regeneration device. 2. The apparatus of claim 1, wherein the in-phase detection means comprises: a plurality of second delay storage means connected in series for receiving and storing the correlation signal; And adding means for receiving the correlation signal and the output signals of the second delay storage means and adding them. 2. The apparatus of claim 1, wherein the in-phase detection means and the comparison means comprise: a plurality of third delay storage means connected in series for receiving and storing the correlation signal; (M-x2) for detecting when the M-x2 bit or more is in a predetermined logic state according to the number M of input signals and the predetermined x2 value, which are received from the correlation signal and the output signals of the third delay storage means. Digital signal reproducing apparatus, characterized in that the bit detection means. 5. The apparatus according to claim 4, wherein the (M-x2) bit detection means comprises: logic AND circuits equal in number and in all cases capable of grouping the M input signals into X2; And a logical OR circuit for receiving the output signals of the logical AND circuits and performing a logical OR operation. A digital signal reproducing apparatus, comprising: detecting means for reproducing and amplifying a recorded digital signal and detecting the recorded digital signal from the reproduced amplified signal, wherein the detecting means receives the reproduced amplified signal and extracts a clock signal. Phase synchronous loop means; 1-bit analog / digital conversion means for receiving the reproduction-amplified signal and converting the clock signal into a sampling clock signal for 1-bit digital conversion; In-phase detection means for receiving the one-bit digitally converted signal and delaying the signal for a predetermined time and detecting in-phase; Correlation means for receiving the detected in-phase signal and determining a correlation signal by predetermined correlation coefficients and outputting the correlation signal; Comparison means for receiving the correlation signal and comparing the threshold value to output a comparison value; Delay means for receiving the delayed signal and delaying at least one clock or more; And decoding means for receiving the signal delayed by one or more clocks and decoding the signal in response to the comparison value. A digital signal reproducing apparatus, comprising: detecting means for reproducing and amplifying a recorded digital signal and detecting the recorded digital signal from the reproduced amplified signal, wherein the detecting means receives the reproduced amplified signal and extracts a clock signal. Phase synchronous loop means; 1-bit analog / digital conversion means for receiving the reproduction-amplified signal and converting the clock signal into a sampling clock signal for 1-bit digital conversion; A plurality of fourth delayed storage means connected in series to receive the 1-bit digitally converted signal and to sequentially store the delayed output; Multiplication means for receiving the one-bit digitally converted signal and the output signals of the fourth delay storage means and multiplying predetermined correlation coefficients; L bit detection means for receiving L output signals of the multiplication means and detecting bits having a predetermined logic state; Comparison means for receiving the output signal of the L-bit detection means and comparing it with a predetermined threshold to output a comparison value; And decoding means for receiving the output signals of the fourth delay storage means and decoding the comparison value as a synchronization signal. A digital signal reproducing apparatus, comprising: detecting means for reproducing and amplifying a recorded digital signal and detecting the recorded digital signal from the reproduced and amplified signal, the digital signal reproducing apparatus comprising: amplifying means for reproducing and amplifying the recorded digital signal at a predetermined gain ratio; A digital signal reproducing apparatus comprising: a phase synchronous loop means for extracting a clock signal by receiving the reproduction-amplified signal; 1-bit analog / digital conversion means for receiving the reproduction-amplified signal and converting the clock signal into a sampling clock signal for 1-bit digital conversion; A plurality of serially connected fifth delay storage means for receiving the 1-bit digitally converted signal and sequentially delaying and sequentially outputting the signal; Multiplication means for receiving the one-bit digitally converted signal and the output signal of the fifth delay storage means and multiplying predetermined correlation coefficient values; (K-x3) bit detection means for receiving the K output signals of the multiplication means and detecting a predetermined logic state of (K-x3) bits or more according to a predetermined x3 value; Comparison means for receiving the detected signal and comparing the detected signal with a predetermined threshold value to output a comparison value; And decoding means for receiving the output signals of the fifth delay storage means and decoding the detected signal as a synchronous signal.