KR0144800B1 - Conditional subtracting apparatus - Google Patents

Abstract

The present invention relates to a conditional subtraction method and a subtractor, which delays the computation time and increases the chip area, which is pointed out as a conventional problem, and performs the subtraction operation immediately without taking a two's complement or a one's complement. It reduces the righteousness and eliminates the delay of computation.

In the present invention as described above, the first operation means for calculating the subtracted and subtracted bits of the M bits by two bits, respectively, and outputting the difference between the 1-bit lease and the 2-bit, and the 1-bit lease obtained by the first calculation means. Second arithmetic means for calculating the subtracted and subtracted bits of the next two bits from the M bits, and outputting the difference value of the two bits and the borrowed number of 1 bit; And third subtraction means for calculating a subtracting value of one bit and a borrowing value of four bits by calculating and subtracting.

Description

Conditional Subtraction Process

1 is a block diagram of a general subtractor.

2 is a general 1-bit full adder circuit diagram.

3 is a general ripple carry 8-bit full adder configuration.

4 is a block diagram of the conditional subtraction processing apparatus of the present invention.

5 is a basic configuration of the subtractor of FIG.

6 is a truth table of the subtractor of FIG.

7 is an operation explanatory diagram of the 8-bit conditional subtractor of FIG.

* Explanation of symbols for main parts of the drawings

300 to 200: first to third calculation means 300a: first subtractor

300c: first selector 302a to 302d: fifth to eighth subtractors

The present invention relates to a subtractor, and in particular, to reduce the chip area and double the processing speed by using a method of subtracting the subtracted from the subtracted directly without taking a two's complement or a one's complement of the subtractive operation. A subtraction processing apparatus.

FIG. 1 shows the structure of a general subtractor. The inverter 100 takes a two's complement of an 8-bit subtracted Y, and the two's complement value obtained through the inverter 100 is input. It consists of an adder 101 which adds and outputs the 8-bit tolerant X.

Such a general subtractor takes a two's complement of the input 8-bit subtractor Y through the inverter 100, and then adds the 8-bit subtracted number X and the adder 101 to carry a one-bit rounding number. And sum of 8 bits.

However, such a subtractor requires the use of an adder in designing a subtractor requiring only a subtraction operation, and the use of the adder requires the use of an exclusive logical sum element (XOR) or an inverter in order to take the subtraction to two's complement. There was a problem that the time delay and the chip area became large.

FIG. 2 is the simplest general 1-bit full adder circuit diagram. As shown in FIG. 2, the rounded number (C) of the front end after logically combining the input subtracted (X) and the subtracted (Y) through the first ogate (OR1). And a AND multiplied through the first end gate AND1, and a value obtained by ANDing the subtracted value X and the subtracted Y through the second end gate AND2 and the first NOA gate NOR1. A round-up generation unit 200a for generating a round-up number C by inverting the OR-inverted value and inverting the OR-inverted value through the first inverter IN1, the to-be-decreased X, the subtracted Y, and After the rounded-up number C obtained in the previous stage is ORed through the second oragate OR2, the OR is multiplied by the output value of the first NOAgate NOR1 and the third end gate AND3. The value obtained by multiplying the subtracted (X), the subtracted (Y) and the rounded-up number C of the front end by the fourth end gate AND4 and the first value The sum value generation unit 200b generates a sum value SUM by inverting the logic sum through the two-nore gate NOR2 and inverting it through the second inverter IN2.

3 illustrates a general ripple carry 8-bit full adder, and each of the first to eighth full adders 200 to 207 connects eight 1-bit full adders of FIG. 2 in parallel.

Since the first to eighth full adders 200 to 207 which are the respective one bits connected in parallel are configured in the same way as the one-bit full adder shown in FIG. 2, the third diagram will be described with reference to the one-bit full adder. Is as follows.

First, the first full adder 200, which is the least significant bit, logicalizes the subtracted bit X0 and the subtracted Y0 of the least significant bit input to output a rounded number C of one bit and a sum value S0 of one bit. The second full adder 201 performs a logical operation by logicalizing the rounded-up number C of the lower bit input from the first full adder 200 and the next higher bit, the to-be-decreased (X1) and the reduced (Y1). The rounded-up number C and the sum value S1 of one bit are output.

In this way, when the data of the most significant bit from the least significant bit is calculated through the first through eighth adders 200 to 207, an eight-bit sum value S0 to S7 and a one-bit rounding number C can be obtained. have.

The first to eighth full adders 200 to 207 will be described with reference to FIG. 2 as an example.

For example, the values of the to-be-decreased (X0 to X7) from the most significant bit to the least significant bit are sequentially input to the first to eighth full adders (200 to 207) corresponding to 10101111, respectively. Assuming that the value Y7) is sequentially input to the first to eighth adders 200 to 207 respectively corresponding to 11100110, the first or second of the rounding number generator 200a configured in the first full adder 200 is provided. The gate OR1 logically adds the inputted subtracted bit (X0) value 1 of the least significant bit and the reduced bit (Y0) value 0 of the least significant bit to input 1 to one input terminal of the first end gate AND1. The first end gate AND1 outputs the result of logically multiplying the value of 1 input from the first oracle OR1 with the external rounding number C. At this time, the rounding number C in the least significant bit is output. Since the first adder AND1 is generated by the adder at the front end and is not inputted, the first end gate AND1 is 1 and all input from the first oragate OR1. Number, and outputs a logical 0 is multiplied by the 0 and of (C).

On the other hand, the second end gate AND2 of the rounding generator 200a multiplies 1 by the subtracted value X0 and 0 by the subtracted Y0, and 0 is input to the other input terminal of the first NOR gate NOR1. Will be entered.

Accordingly, the first NOR gate NOR1 outputs 1 by inverting 0 and 0 inputted from the first and second end gates AND1 and AND2, respectively, and outputs 1. The value of 1 output from is inverted to 0 through the first inverter IN1 and is input to the second full adder 201 of the next stage as the rounded-up C value, that is, C = 0.

On the other hand, under the same input bit condition, the second oA gate OR2 of the sum value generator 200b of the first adder 200 logically sums 1 of the subtracted value X0 and 0 of the subtracted Y0 which are the least significant bits. Will output 1.

The value 1 output from the second OR gate OR2 is logically multiplied by the value 1 output from the first NOOR gate NOR1 and the third end gate AND3 to 1, and thus, one side of the second NOA gate NOR2. It is entered at the input terminal.

In addition, the fourth end gate AND4 of the summing value generator 200b multiplies the value 1 of the input least significant bit X0 and the value 0 of the subtracted Y0 by 0 to generate the second nogate. Input is made to the other input terminal of (NOR2).

Therefore, the second NOR gate NOR2 inverts the value of 1 input from the third end gate AND3 and the value of 0 input from the fourth end gate AND4 to output 0.

0 output from the second NOR gate NOR2 is inverted 1 through the second inverter IN2 and output as a sum value SUM, that is, S0 = 1.

In addition, since the second full adder 201 is configured in the same manner as the one-bit full adder in FIG. 2 described above, the subtracted (X1) value 1 and the subtracted (Y1) value 1 of the next lower bit and the first first end. Since the rounded-up C value 0 input to the full adder 200 is logicalized in the same manner as in FIG. 2, the rounded-up number C is outputted as 1, and the third full adder 202 of the next stage is outputted. Is input to the sum value S1.

In this way, when eight bits calculate the value 10101111 of the subtracted (X0 to X7) and the value 11100110 of the subtracted (Y0 to Y7) with the first to eighth adders (200 to 207), the final value S7 = 1. , S6 = 0, S5 = 0, S4 = 0, S3 = 0, S2 = 1, S1 = 0, S0 = 1, and the value of the final rounded number C is 1.

However, an adder having such a structure requires a lot of computation time because the output rounds of the lower bits propagate to the input rounds of the upper bits to reach the most significant bit in order to calculate 8-bit data. Due to this slow computation of the adder, high-speed signal processing systems often use conditional adders with fast computation time.

However, even if a conditional adder is used, if a subtraction operation is performed using an adder, one of the input data must be 2's complement or 1's complement, which increases the delay time and the chip area. There was also a problem that occurred.

Accordingly, the object of the present invention is to reduce the chip area by performing the subtraction operation immediately without taking the two's complement or the one's complement for the delay of the computation time and the increase of the chip area, which is pointed out as such a conventional problem. It is an object of the present invention to provide a conditional subtraction processing apparatus for eliminating delay in trial.

As a means for achieving the object of the present invention, the first operation means for outputting the borrowed number and the 2-bit difference value of each bit by separately calculating the M-to-reduced subtracted and subtracted by one bit, respectively; A second operation means for separately calculating the to-be-decreased and subtracted bits of the next two bits from the M bits by one bit according to the borrowed value of the one bit obtained by the calculation means, and outputting the difference value of the two bits and the borrowed number of one bit; A third operation means for outputting a difference value of four bits and a lease value of one bit by calculating the remaining tolerant and the subtraction of M bits according to the lease value obtained by the second operation means is made. When described in detail based on the drawings as follows.

4 is a block diagram of an 8-bit conditional subtraction processing apparatus according to the present invention. As shown in FIG. 4, one bit of the 8-bit subtracted (X) and the subtracted (Y) is calculated, and each bit is borrowed (B). And the first bit means (300) for obtaining the difference value (D) of two bits, and the next two bits of the M bits are reduced depending on the borrowing number (B) of one bit obtained by the first calculation means (300). And a second operation means 301 which calculates a difference value of two bits and a lease number of one bit by calculating a subtraction and Y reduction, and M according to the lease number B obtained by the second operation means 301. The third operation means 302 calculates the residual value D and the subtracted number B of the bits and finally obtains the difference value D of four bits and the borrowing number B of one bit.

In the above description, the first operation means 300 subtracts the least significant one bit from the 8-bit subtracted subtracted X and the subtracted Y, thereby obtaining a borrowing value B0 (B1) of two bits and a difference value of two bits ( A first subtractor 300a for calculating D0) (D1), and the subtracted subtraction (X) and the subtraction (Y) of the next lower bit among the 8 bits, subtracting two bits of borrowing number (B0) (B1) and two bits. The second subtractor 300b obtaining the difference values D0 and D1 and the two-bit borrowing number B0 obtained by the second subtractor 300b according to the borrowing number B0 value obtained by the first subtractor 300a. ) B1 and a first selector 300c for selecting and outputting the difference values D0 and D1.

In the above, the second operation means 301 subtracts the third and fourth subtracted numbers X and the subtracted numbers Y from the eight bits, respectively, to respectively borrow two bits B0 and B1 and two bits. The fourth subtractor 301b according to the third and fourth subtractors 301a and 301b for obtaining the difference values D0 and D1 and the respective borrowing numbers B0 and B1 obtained from the third subtractor 301a. Second and third selectors 301c and 301d respectively selecting and outputting the borrowing number B0 (B1) and difference value D0 (D1) of the two bits obtained from The 4-bit value obtained by the selection in 301c and 301d and the difference value D0 and D1 of the two bits obtained in the third subtractor 301a according to the number of borrows output from the first selector 300c. It consists of a 4th selector 301e which selects and outputs only.

The third calculating means 302 subtracts the remaining 4 bits of the subtracted X and the subtracted Y by 1 bit from the 8 bits of the input 8 bits, respectively, so that the borrowing number B0 (B1) of the two bits and the difference value ( The fifth to eighth subtractors 302a to 302d for obtaining D0) (D1) and the sixth subtractor 302b according to the respective borrowing numbers B0 and B1 values obtained from the fifth subtractor 302a. The fifth and sixth selectors 302e and 302f respectively selecting and outputting the difference values D0 (D1) and the borrowing numbers B0 and B1 of the two bits obtained, respectively, and the respective values obtained by the seventh subtractor 302c. 7th and 7th to select and output the difference value D0 (D1) and the borrowing number B0 (B1) of the two bits obtained by the eighth subtractor 302b according to the borrowing number B0 (B1) of Two bits each of the seventh and eighth selectors 302g and 302h according to the eighth selectors 302g and 302h and the respective borrowing numbers B0 and B1 obtained from the sixth selector 302f. The difference value obtained from the difference value and the borrowed value value, and each bit obtained by the seventh subtractor 302c, and The ninth and tenth selectors 302i and 302j for selecting and outputting the rim number by 3 bits, respectively, and the ninth and tenth selectors 302i and 302j according to the borrowing numbers obtained by the fourth selector 302e. 5 bits out of the values obtained by 3 bits respectively, and the values obtained by the difference values D0 (D1) of the two bits obtained by the fifth subtractor 302a and by one bit each of the seventh and eighth selectors 302g and 302h. The eleventh selector 302k selects and outputs a value of.

The first to eighth subtractors 300a and 300b (301a and 301b) and 302a to 302d, which are one bit in the above, are subjected to the subtracted (X) and the subtracted (Y) of the input bits as shown in FIG. ) And the exclusive logic element XOR1 for outputting the difference value D0, and the output value of the exclusive logic sum element XOR1 and the bit-decreased input X of one bit to be logically inverted to obtain the borrowing number B1. Inverter IN1 outputting the difference value D1 by inverting the NAND gate NAND1 to be output, the output value of the exclusive logical sum element XOR1, and the output value of the exclusive logic sum element XOR1 and a bit bit reduction Y ) And the end gate AND1 outputting the borrowing number B0.

Thus, the operation and effect of the present invention configured as described in detail with reference to FIGS. 4 to 7 as follows.

First, FIG. 6 is a truth table of the subtractor shown in FIG.

Where X and Y are the subtracted and subtracted, respectively, and represent the input bit value, and D0 is the difference between the two input subtracted (X) and the subtracted (Y) when the subtracted (X) does not lend to the lower bit. , B0 represents the number of borrows required from the upper bits when the to-be-decreased (X) does not lend the lower bits.

In addition, D1 and B1 represent the difference between the two input subtracted (X) and the subtracted (Y) and the number of leases required from the upper bit when the subtracted (X) lends a lower bit.

As an example, the third of the four cases of FIG. 6, that is, the case where the to-be-decreased (X) is 0 and the subtracted (Y) is 1 is as follows.

In the case where the to-be-decreased (X) does not lend to the lower bit, if the input bit of the to-be-determined (X) is 0 and the input bit of the subtracted (Y) is 1, the difference is -1, and therefore 1 from the higher bit. Since the borrowing number B0 is 1, the difference is 1 by borrowing 1, and the difference D0 is also 1.

On the other hand, if the subtracted value (X) lends a lower value to the lower bit under the same input bit condition, the borrowed number (B1) also becomes 1, and the difference value (D1) lends 1 to the lower bit. It is 0 because there is one.

In the truth table of Figure 6, the other cases are explained in the same sense.

FIG. 5 is a circuit diagram of the subtractor with respect to the truth table of FIG. 6, showing the basic circuits for the difference values D0 (D1) and the borrowing numbers B0 (B1) for the circuit of the conditional subtraction processing apparatus of FIG. .

Specifically, referring to the truth table of FIG. 6, first, in the first case of the four cases of the truth table, when the input bit of the superimposed (X) is 0 and the input bit of the subtracted (Y) is 0, The exclusive OR unit XOR1 outputs the difference value D0 as 0 by exclusively ORing the bit values 0 and 0 of the two input subtracted values X and the subtracted Y, and the end gate AND1 outputs the subtracted value Y. ) And the output of the borrowing number B0 as 0 by logically multiplying the input bit 0 of the X1 and the output value 0 of the exclusive OR element XOR1.

On the other hand, when the to-be-reduced X lends the lower bit under the same input bit condition, the NAND gate NAND1 logics the input bit 0 of the to-be-reduced X and the output value 0 of the exclusive logical sum element XOR1. The borrowed number B1 becomes 1 because the product must be borrowed from the output and the upper bit by borrowing the number B1 to 1 by inverting the product.

The inverter IN1 inverts the output value of the exclusive logical sum element XOR1 and outputs the difference value D1 as 1, which is 1 since no 1 is borrowed from the lower bit.

In the same way, the fourth of the four cases of the truth table of the sixth case is as follows.

Since the input bit of the superimposed (X) is 1 and the input bit of the subtracted (Y) is 1, the exclusive logical sum element XOR1 outputs the difference value D0 as 0 by exclusively ORing the two input bit values 1 and 1, and ending with The gate AND1 logically multiplies the output 0 of the exclusive logical sum element XOR1 by the input bit value 1 of the subtractive Y and outputs the borrowing number B0 as zero.

The NAND gate NOR1 inverts the input bit value 1 of the to-be-determined X and the output 0 of the exclusive-OR device XOR1 to output the borrowing number B1 to 1, and the inverter IN1 outputs the exclusive-OR. The output value 0 of the element XOR1 is inverted to output the difference value D1.

As described above, there is no difference when the input bit of the subtracted X is 1 and the input bit of the subtracted Y is 1 in the case where the subtracted X does not lend to the lower bit as described above. Since it becomes 0 and therefore does not need to borrow 1 from the upper bit, the borrowing number B0 becomes 0 and the difference value D0 also becomes 0.

In the case where the to-be-decreased (X) lends a lower bit, the borrowed number (B1) becomes 1 and the difference (D1) does not lend 1 to the lower bit. It becomes 1.

Thus, with reference to the basic configuration of the subtractor of FIG. 5, the truth table of the subtractor of FIG. 6 and the operation explanatory diagram of the 8-bit conditional subtractor of FIG. 7, FIG.

First, the first to eighth subtractors 300a, 300b, 301a, 301b, and 302a to 30 of FIG.

2d) is a module including the basic circuit of FIG. 5, and outputs a difference value D0 (D1) and a lease number B0 (B1) for two input bit values based on the truth table of FIG. Indicates the operation of step 1.

The first to third selectors 300c, 301c and 301d and the fifth to eighth selectors 302e to 302h select two output values from the four inputs.

At this time, the control signals of the first to third selectors 300c, 301c and 301d and the fifth to eighth selectors 302e to 302h are selected by the borrowing value of the previous stage as shown in FIG. The second step of FIG. 7 is shown.

The fourth selector 302e and the ninth and tenth selectors 302i and 302j receive six inputs and output three outputs, and the third step is illustrated in FIG.

The eleventh selector 302k receives 10 inputs and emits 5 outputs, which corresponds to the fourth step in FIG.

For example, a result of the process of selecting an output value by a borrowing value in each of the first to eleventh selectors 300c and 301c to 301e and 302e to 302k, i. Since the borrowing number at = 3 is 1, as shown in the fourth step of FIG. 7, in FIG. 4, a value obtained by assuming the borrowing number is 1 out of two pieces of data input to the eleventh selector 302k.

In another example, since i = 1 in step 2 of FIG. 7, the borrowing number is 1, and the result obtained in step 3 of FIG. 7 is assumed to be 1 and the value obtained is selected.

Arrows in FIG. 7 respectively indicate a process of selecting data through a selector in the next step.

That is, in the first step of FIG. 7, D0 (1) and D1 (1) for the inputs given in the eight first to eighth subtractors 300a, 300b, 301a, 301b, and 302a to 302d. , B0 (1), and B1 (1) are obtained.

Where the number in the horizontal line represents the step and the subscript means the value of the assumed lease.

In the second step, the first to third selectors 300c, 301c and 301d and the fifth to eighth selectors 302e to 302h are obtained by using the resultant value and the borrowed number value obtained in the first step. Select two values from four inputs.

At this time, the two groups are assumed to be borrowed, and the first to third selectors 300c, 301c and 301d and the fifth to eighth selectors 302e to 302h are performed.

For example, in the first step (i = 0, i = 1), (i = 2, i = 3), (i = 4, i = 5), (i = 6, i = 7) Tie up and process.

The process of selecting input data in each of the first to third selectors 300c, 301c and 301d and the fifth to eighth selectors 302e to 302h is indicated by arrows in FIG.

In the case of (i = 0 and i = 1), since the borrowing number is 0 at the position of i = 0, only one selector, that is, the first selector 300c, needs to be used.

In the third step, three of the six inputs are selected by the fourth, ninth, tenth selectors 301e, 302i, and 302j using the value and lease number obtained in the second step.

In the fourth step, five values of ten inputs are selected by the eleventh selector 302k by using the value and lease number obtained in the third step.

Note that the difference value from i = 0 to i = 1 is determined in the second step, the difference value from i = 2 to i = 3 is determined as the difference value in the third step, and the difference value obtained in the third step is determined in the fourth step. The remaining values are determined by the borrowing value at i = 3.

This will be described using an example of FIG. 7 as follows.

First to eighth subtractors 300a, 300b, and 301a of the first to third arithmetic means 300 to 302, wherein the input eight bit values of the subtracted Xi and the subtracted Yi are 10011010 and 1001111, respectively. ) 301b and 302a to 302d, the first subtractor 300a of the first calculating means 300 is the least significant bit of the subtracted Xi among the input bits of the subtracted Xi and the subtracted Yi. The least significant bit value 1 of the value 0 and the subtracted Yi is logicalized in the same manner as described above with reference to FIG. 5 to output the difference value D0 as 1 and to output the borrowing number B0 as 1 to select the first selector ( 300c).

As described above, the second subtractor 300b of the first operation means 300 compares the input bit value 1 of the subtracted Xi, the second bit of the least significant bit, and the input bit value 1 of the subtracted Yi, as described above. In operation, the difference value D0 and the borrowing number B0 are output as 0, and the difference value D1 and the borrowing number B1 are output as 1 and input to the first selector 300c.

Therefore, as shown in FIG. 7, the first selector 300c of the first operation means 300 has a second subtractor (B0) since the value of the borrowing number B0 input from the first subtractor 300a at the front end is 1. Difference value (D1) 1 and borrowing number (B1) when the subtracted value Xi lends a lower bit among the difference values D0 (D1) and borrowing number B0 (B1) obtained from 300b). Each value 1 is selected (B0) and output as a difference value (D0).

On the other hand, the third subtractor 301a of the second operation means 301 logicalizes the input bit value 0 of the subtracted Xi and the input bit value 1 of the subtracted Yi, the third bit of the least significant bit. Therefore, the borrowing numbers B0 and B1 are output as 1 and 1, respectively, and the difference value D0 is output as 1 and the difference value D1 is output as 0.

In the same manner as described above, the fourth subtractor 301b logicalizes the input bit value 1 of the fourth sub-bit to be subtracted (Xi) and the input bit value 1 of the subtraction (Yi) to decrease the subtracted value Xi. When one bit difference value (D0) and the number of borrowed values (B0) are output as 0 when the borrow value is not given to the lower bit, and each of the cases where the subtracted value Xi lends the borrow value to the lower bit. The 1-bit difference value D1 and the borrowing number B1 value of 1 are input to the second and third selectors 301c and 301d, respectively.

At this time, the second selector 301c has a difference value D0 obtained from the fourth subtractor 301b since the borrowing number B0 value input from the third subtractor 301a is 1, as shown in FIG. From among the values of D1 and borrowing number B0 and B1, a difference value D1 having a value of 1 and a borrowing number B1 having a value of 1 are selected, and the fourth selector (B1) is selected as the difference value D0 and the borrowing number B0 value. And the third selector 301d inputs the borrowing number B1 from the third subtractor 301a to 1 so that the difference value D0 (D1) obtained by the fourth subtractor 301d is obtained. ) And the borrow value B1 having a value 1 and the borrow value B1 having a value 1 from among the values of the number and the borrowing number B0 and B1 are directly input to the fourth selector 301e.

The fourth selector 301e of the second calculating means 301 is D0 = 1, D1 = 0 obtained from the third subtractor 301a, and D0 = 1, B0 = 1 and the first selected from the second selector 301c. 3 bits are selected from among D1 = 1 and B1 = 1 selected by the three selector 301d. In this case, since the borrowing number B0 value from the first selector 300c of the front stage is input as 1, FIG. As in, D0 = 0, D0 = 1 and B0 = 1 are selected and output.

On the other hand, the fifth to eighth subtractors 302a to 302d of the third calculating means 302 also use the same method as described above to determine the eighth to eighth values of the input bits of the subtracted Xi and the subtracted Yi. As shown in Fig. 7, the two-bit difference value D0 (D1) and the two-bit borrowing number B0 (B1) are obtained.

That is, the fifth subtractor 302a logicalizes the input bit value 1 of the fifth subtracted Xi and the input bit value 0 of the subtracted Yi, so that D = 1, B0 = 0, D1 = 0, B1 = The sixth subtractor 302b outputs D0 = 0, B0 = 0, D1 = 1, and B1 = 1 by logicalizing the values of 0 and 0 of the 6th subtracted Xi and the subtracted Yi. The seventh subtractor 302c outputs D0 = 1, B0 = 1, D1 = 0, and B1 = 1 by logicalizing the value 0 of the seventh subtracted Xi and the value 1 of the subtracted Yi. Finally, the eighth subtractor 302d logicalizes the value 1 of the most significant bit (Xi) and the value 0 of the subtraction (Yi) to output D0 = 1, B0 = 0, D1 = 0, and B1 = 0. do.

Accordingly, the fifth selector 302e of the third calculating means 302 is obtained by the sixth subtractor 302b by the value 0 of the borrowing number B0 input from the fifth subtractor 302a. ) 0 and the borrowing number (B0) value 0 are selected and input to the eleventh selector 302k, and the sixth selector 302f is based on the borrowing number (B1) value 0 obtained by the fifth subtractor 302a. From the difference value D0 (D1) and the borrowing number B0 (B1) values obtained by the six subtractor 302b, the difference value D0 and the borrowing number B0 having zero are selected, respectively, and the difference value D1 and the borrowing number ( Will output to B1).

On the other hand, the seventh selector 302g is the difference value D0 (D1) and the borrowing number (obtained from the eighth subtractor 302d) by the value 1 of the borrowing number B0 inputted from the seventh subtractor 302c. Among the values B0) and B1, a difference value D1 having a zero and a borrowing number B1 are selected and input to the ninth and tenth selectors 302i and 302j as the difference value D0 and the borrowing number B0. Selects the difference value D1 and the borrowing number B1 having 0 from the difference values D0, D1 and the borrowing number B0 and B1 obtained by the eighth selector 302d, respectively. Input to selectors 302i and 302j.

Accordingly, the ninth selector 302i is obtained by the seventh subtractor 302c by 0 of the borrow number B0 selected and input from the fifth selector 302e, and D0 = 1, D1 = 0 and 7 selects three bits of D0 = 1, D0 = 0, and B0 = 0 from D0 = 0, B0 = 0 and D1 = 0 and B1 = 0 obtained in the eighth selector 302h. The tenth selector 302j inputs to the selector 302k, and D0 = 1, D1 obtained from the seventh subtractor 302c by the borrowing number B1 value 0 input from the sixth selector 302f. 3 bits of D0 = 1, D0 = 0, B0 = 0 among D0 = 0, B0 = 0 and D1 = 0 and B1 = 0 obtained in the seventh selector 302g D1 = 1, D1 = 0, and B1 = 0 are selected and input to the eleventh selector 302k.

Accordingly, the eleventh selector 302k includes D0 = 1, D1 = 0 obtained by the fifth subtractor 302a, and D0 = 0, respectively obtained by one bit from the fifth and sixth selectors 302e and 302f. The fourth selector 302e of D1 = 0 and D0 = 1, D0 = 0, B0 = 0, D1 = 1, D1 = 0, and B1 = 0 obtained from the ninth and tenth selector 302i (302j). The D1 = 0, D1 = 0, D1 = 1, D1 = 0, and B1 = 0 are selected and output from the lower bits by the borrowing number (B0) value 1 obtained from.

Therefore, when the first subtractor 300a, the first, the fourth selector 300c, 301e, and the eleventh selector 302k are combined in the lower bit order, the finally subtracted 8-bit value Z0 = 1, Z1 = 1, Z2 = 0, Z3 = 1, Z4 = 0, Z5 = 0, Z6 = 1, Z7 = 0, Z8 = 0.

As described in detail above, according to the present invention, a subtraction operation is performed directly from pure two inputs without using an exclusive logic element or other element such as an inverter, so that the subtraction operation can be performed considerably faster. In addition, the chip area can be considerably reduced by using as few logic gates as possible to configure the basic cell of the subtractor.

Claims (6)

A first subtractor for subtracting the least significant one bit from the subtracted and subtracted M bits to obtain the difference between the lease of two bits and the difference between the two bits; A second subtractor for obtaining the difference between the borrowing number and the two bits, a first selector for calculating and outputting the borrowing number and the difference value of the two bits obtained from the second subtractor as M / 2 based on the borrowing value obtained from the first subtractor; Third and fourth subtractors each subtracting the third and fourth subtracted subtracted and subtracted bits from the M bits to obtain two-digit borrowed values and a difference value between the two bits, respectively; and each of the two bits borrowed from the third subtractor. The second and third selectors for selecting and outputting the borrowing number and difference value of the two bits obtained by the fourth subtractor according to the numerical value as M / 2, and the 4-bit values selected and selected from the second and third selectors, respectively. remind A fourth selector for selecting a difference value between the two bits obtained by the third subtractor as M / 2 according to the lease output from the first selector, and outputting a 3-bit value; Subtract one bit each to obtain the borrowing number and the difference value of two bits, respectively; and the difference value of the two bits obtained from the sixth subtractor according to the borrowing value of two bits obtained from the fifth subtractor; The fifth and sixth selectors for selecting and outputting the borrowing number as M / 2, respectively, and the difference value and the borrowing value of the two bits obtained from the eighth subtractor according to the two-bit borrowing value obtained from the seventh subtractor, respectively. The difference value, the borrow value, and the seventh subtractor obtained by two bits, respectively, in the seventh and eighth selectors according to each of the seventh and eighth selectors and the sixth selector to output the selected second value. 1 bit A ninth and tenth selector for selecting a difference value and a borrowing value M / 2 to obtain three bit values, respectively; and a value obtained by three bits in each of the ninth and tenth selectors by the number of rounds obtained by the fourth selector; And an eleventh selector configured to select M / 2 as a difference value between two bits obtained by the fifth subtractor and a value obtained by one bit from the seventh and eighth selectors as M / 2 to obtain a result value of the remaining bits. Conditional Subtraction Process. 2. The apparatus of claim 1, wherein the first to eighth subtractors are configured to output an exclusive logic element for outputting the difference value D0 by exclusively ORing the subtracted and subtracted bits of the input bit, and the output value of the exclusive logical sum element and the input subtracted bit of the bit. A NAND gate that multiplies and outputs the borrowing number (B1), an inverter that outputs the difference value (D1) by inverting the output value of the exclusive logical sum device, and an output value of the exclusive logical sum element and a subtractive value of one bit A conditional subtraction processing apparatus comprising an end gate for outputting a borrowing number B0. The conditional subtraction processing apparatus according to claim 1, wherein the first subtractor is configured to obtain and output the result of the subtraction of the least significant bit when the input bits of the subtracted and subtracted bits are 8 bits. The conditional part of claim 1, wherein the first selector is configured to calculate and output a subtraction result of the second bit in the least significant bit by the borrowing value of the first selector when the input bit of the subtracted and subtracted bits is 8 bits. Subtraction processing device. The conditional subtraction processing apparatus according to claim 1, wherein the fourth selector is configured to obtain and output a subtraction result value of the third light fourth bit from the least significant bit when the input bit of the subtracted and subtracted bits is 8 bits. The conditional subtraction processing apparatus according to claim 1, wherein the eleventh selector is configured to obtain and output the remaining 4 bits of the subtraction result value when the input bits of the subtracted and subtracted bits are 8 bits.