KR0143252B1 - Triple well formation method - Google Patents
Triple well formation methodInfo
- Publication number
- KR0143252B1 KR0143252B1 KR1019950018871A KR19950018871A KR0143252B1 KR 0143252 B1 KR0143252 B1 KR 0143252B1 KR 1019950018871 A KR1019950018871 A KR 1019950018871A KR 19950018871 A KR19950018871 A KR 19950018871A KR 0143252 B1 KR0143252 B1 KR 0143252B1
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- South Korea
- Prior art keywords
- well
- ion implantation
- conductive
- type
- triple
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 title abstract description 4
- 238000005468 ion implantation Methods 0.000 claims abstract description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 25
- 239000012535 impurity Substances 0.000 claims abstract description 25
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 25
- 239000010703 silicon Substances 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 14
- 210000001747 pupil Anatomy 0.000 claims description 13
- 238000009826 distribution Methods 0.000 abstract description 8
- 238000002513 implantation Methods 0.000 description 7
- 230000007547 defect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 반도체소자 제조시 3중 웰(triple well) 형성방법에 관한 것으로, COMS에 적용되는 3중 웰 형성시 고 이온주입에 의해 발생하는 실리콘 격자내의 격자간 불순물(interstitial impurity)과 동공(vacancy)의 분포를 서로 상쇄하도록 상기 제2도전형의 웰의 이온주입시 형성되는 동공과 제1도전형의 제2월의 이온주입시 형성되는 격자간 불순물 영역을 근접하게 형성하는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming triple wells in the manufacture of semiconductor devices, wherein interstitial impurity and vacancy in silicon lattice generated by high ion implantation during triple well formation applied to COMS The hole formed during ion implantation of the well of the second conductivity type and the lattice impurity region formed during ion implantation of the second month of the first conductivity type are closely formed so as to cancel the distribution of
Description
제1도는 반도체소자의 3중 웰을 형성한 단면도.1 is a cross-sectional view of a triple well of a semiconductor device.
제2도는 종래의 3중 웰의 도핑 프로파일을 도시한 도면.2 shows the doping profile of a conventional triple well.
제3도는 종래의 3중 웰의 순수 결합 프로파일을 도시한 도면.3 shows the net binding profile of a conventional triple well.
제4도는 본 발명의 3중 웰의 도핑 프로파일을 도시한 도면.4 shows the doping profile of the triple well of the present invention.
제5도는 본 발명의 3중 웰 순수 결함 프로파일을 도시한 도면.5 shows a triple well pure defect profile of the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1:제2P웰2:N 웰1: 2nd P well 2: N well
3:제1P웰4:P형 실리콘기판3: 1st P well 4: P-type silicon substrate
14,17:동공(vacancy)14, 17: vacancy
15,16:격자간 불순물(interstitial impurity)15,16 interstitial impurity
본 발명은 반도체소자 제조시 3중 웰(triple well) 형성방법에 관한 것으로, CMOS에 적용되는 3중 웰 형성시 고 이온주입에 의해 발생하는 실리콘 격자내의 격자간 불순물(interstitial impurity)과 동공(vacancy)의 분포를 서로 상쇄하도록 하는 3중 웰 형성방법에 과한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming triple wells in the manufacture of semiconductor devices. The present invention relates to interstitial impurity and vacancy in silicon lattice generated by high ion implantation during triple well formation applied to CMOS. The triple well formation method which cancels | distributes) distribution from each other is exceeded.
일반적으로 디램(DRAM)의 주변회로에는 CMOS가 널리 사용되며, 이러한 CMOS는 3중 웰이 구비된 실리콘기판에 형성되는데 3중 웰은 종래의 2중 웰 구조의 N웰 영역에 또 다른 P웰 영역이 형성된다. 물론 N형 기판에는 상기와 반대의 구조로 구성될 것이다.In general, CMOS is widely used in a peripheral circuit of a DRAM, and such a CMOS is formed on a silicon substrate having a triple well, and the triple well is another P well region in an N well region of a conventional double well structure. Is formed. Of course, the N-type substrate will be configured in the opposite structure.
제1도는 P형 실리콘기판(4)의 예정된 지역에 도즈량 5×1013, 이온주입에너지 2 MeV에서 인을 이온주입하여 웰(2)을 형성하고, 상기 N웰(2)의 예정된 지역과 실리콘기판(4)의 예정된 지역에 도즈량 5×1013, 이온주입에너지 700KeV에서 붕소를 이온주입하여 제2P웰(1)과 제1웰(3)을 각각 형성하여 3중 웰이 구비된 것을 도시한 단면도이다.FIG. 1 shows wells 2 formed by implanting phosphorus at a dose of 5 × 10 13 and ion implantation energy 2 MeV in a predetermined region of a P-type silicon substrate 4, and forming a well 2 with the predetermined region of the N well 2. The second P well 1 and the first well 3 were formed by ion implanting boron at a dose of 5 × 10 13 and an ion implantation energy of 700 KeV in a predetermined region of the silicon substrate 4 to form a triple well. It is sectional drawing.
제2도는 제1도의 Ⅰ-Ⅰ를 따라 절개하여 실리콘기판의 깊이에 따라 불순물 농도 분포와 격자간 불순물과 동공의 분포를 도시한 도면으로서, 도면에서 부호 11로 도시한 피크는 제2 P웰지역이고, 부호 12는 N웰 지역이고, 부호 13은 P형 실리콘기판 지역을 도시하는 것이고, 부호 17은 제2 P웰의 이온주입시 형성된 동공이며, 부호 14는 N웰의 이온주입시 형성된 동공이며, 부호 15는 제2 P웰의 이온주입시 형성된 격자간 불순물 이며, 부호 16은 N웰 이온주입시 형성된 격자간 불순물 분포를 나타낸 것이다.FIG. 2 is a diagram showing the distribution of impurity concentrations and the distribution of interstitial impurities and pupils according to the depth of the silicon substrate by cutting along the line I-I of FIG. 1, and the peak indicated by reference numeral 11 in the drawing is the second P well region. 12 is an N well region, 13 is a P-type silicon substrate region, 17 is a pupil formed during ion implantation of a second P well, and 14 is a pupil formed during ion implantation of an N well Denotes an interstitial impurity distribution formed upon implantation of the second P well, and a reference numeral 16 denotes an interstitial impurity distribution formed upon implantation of the N well ion.
제3도는 제1도의 Ⅰ-Ⅰ를 절개하여 도시한 단면에서 순수한 결함 프로파일을 도시한 도면으로서, 부호 21은 제2 P웰 이온주입시 실리콘 격자내에 형성된 동공이며, 부호 22는 N웰 이온주입시 실리콘 격자 내에 형성된 동공이고, 부호 23은 제2 P웰 이온주입시 실리콘 격자내에 형성된 격자간 불순물이며, 부호 24는 N웰 이온주입시 실리콘 격자 내에 형성된 격자간의 불순물이다.FIG. 3 is a diagram showing pure defect profiles in a cross-sectional view taken along the line I-I of FIG. 1, where 21 is a pupil formed in the silicon lattice during the second P well ion implantation, and 22 is the N well ion implantation. A hole formed in the silicon lattice, reference numeral 23 denotes interstitial impurities formed in the silicon lattice at the time of second P well ion implantation, and reference numeral 24 denotes an impurity between lattice formed in the silicon lattice at the N well ion implantation.
상기와 같이 N형 웰 이온주입에 의해 실리콘 격자내에 동공과 제2 P웰 이온주입에 의해 격자간 불순물이 서로 분리되어 존재하고 있으므로 웰 접합의 디플리션(depletion) 층이 형성됨에 따라 이것이 누설전류의 원인으로 작용한다는 점이다.As described above, since the lattice impurities are separated from each other by the pupil and the second P well ion implantation in the silicon lattice by the N-type well ion implantation, this results in a leakage current as a depletion layer of the well junction is formed. It acts as a cause.
따라서, 상기의 웰 접합의 누설전류를 감소시키기 위해서는 동공과 격자간 불순물의 위치를 근접시켜 서로 상쇄되도록 하는 3중 웰 형성방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a triple well forming method in which the leakage current of the well junction is reduced so that the positions of the impurities between the pupil and the lattice are close to each other.
상기한 목적을 달성하기 위한 본 발명은 제1도전형 실리콘기판의 예정된 지역에 제2도전형 웰을 형성하고, 상기 제2도전형 웰의 일정부분과 제1도전형의 실리콘기판의 예정된 지역에 제1 도전형의 제2 웰과 제1웰을 각각 형성하여 3중 웰이 구비되는 반도체소자 제조 방법에 있어서, 상기 제2도전형 웰의 이온주입시 형성되는 동공과 제1도전형의 제2웰의 이온주입시 형성되는 격자간 불순물 영역이 근접하게 형성되도록 제2도전형 웰과 제1도전형 제2웰의 이온주입에너지를 조절하는 것을 특징으로 한다.The present invention for achieving the above object is to form a second conductive well in a predetermined region of the first conductive silicon substrate, a predetermined portion of the second conductive well and the predetermined region of the first conductive silicon substrate A method of manufacturing a semiconductor device, in which a second well and a first well of a first conductivity type are formed to have triple wells, wherein the pupil and the second conductive type are formed when the second conductive well is implanted. The ion implantation energy of the second conductive well and the first conductive second well may be adjusted to closely form the interstitial impurity regions formed during the ion implantation of the well.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제4도 및 제5도는 본 발명에 의해 P형 실리콘기판에 3중 웰을 형성할 때 제2 P웰 이온주입에너지와 N웰 이온주입에너지를 적당히 조절하여 동공과 격자간 불순물의 위치를 근접시킨 것을 도시한 도면이다.4 and 5 show that the second P well ion implantation energy and the N well ion implantation energy are appropriately adjusted when the triple wells are formed on the P-type silicon substrate according to the present invention. It is a figure which shows that.
제4도는 N 형 웰(2)을 형성하기 위한 이온주입에너지를 종래와 동일한 에너지를 이용하고, 제2 P웰(1)을 형성하기 위한 이온주입에너지는 종래보다 이온주입에너지를 감소시켜서 제2P 웰(1)을 형성한상태에서 제1도의 Ⅰ-Ⅰ를 따라 절개하여 실리콘기판의 깊이에 따라 불순물 농도와 격자간 불순물과 동공이 존재하는 것을 도시한 도면으로서, 도면에서 부호 11로 도시한 피크는 제2P웰지역이고, 부호 12는 N웰 지역이고, 부호 13은 P형 실리콘기판 지역을 도시하는 것이고, 부호 17은 제2P웰의 이온주입시 형성된 동공이며, 부호 14는 N웰의 이온주입시 형성된 동공이며, 부호 15는 제2P웰의 이온주입시 형성된 격자간 불순물이며, 부호 16은 N웰 이온주입시 형성된 격자간 불순물로서, N웰의 이온주입시 형성된 동공(14)와 제2 P웰의 이온주입시 형성된 격자간 불순물(15) 영역이 근접하게 형성된 것을 도시한다.4 shows the ion implantation energy for forming the N-type well 2 using the same energy as in the prior art, and the ion implantation energy for forming the second P well 1 reduces the ion implantation energy than the conventional 2P. In the state in which the well 1 is formed, it is cut along the line I-I of FIG. 1 to show that impurity concentration, interstitial impurities and pores exist depending on the depth of the silicon substrate. A second P well region, 12 is an N well region, 13 is a P-type silicon substrate region, 17 is a pupil formed during ion implantation of the second P well, and 14 is an ion implantation of the N well The pupil is formed, and reference numeral 15 denotes interstitial impurities formed during ion implantation of the second P well, and reference numeral 16 denotes interstitial impurities formed during N well ion implantation. The pupils 14 and the second P wells formed when implanting the N wells are implanted. Interstitial impurities formed during ion implantation of 15) shows that the region is formed in close proximity.
제5도는 제4도에 도시된 도면에 대한 순수함 결함 프로파일을 도시한 도면으로서, 부호 21은 제2P웰 이온주입시 실리콘 격자내에 형성된 동공이며, 부호 32은 제2P웰 이온주입시 실리콘 격자 내에 형성된 동공이고, 부호 33은 제2P웰 이온주입시 실리콘 격자내에 형성된 불순물이며, 부호 24는 N웰 이온주입시 실리콘 격자 내에 형성된 격자간의 불순물을 도시한 것으로, 본 발명에 의해 N웰의 이온주입시 형성된 동공(32)과 제2P웰의 이온주입시 형성된 격자간 불순물(33) 분포가 근접하게 형성하는 경우에 서로 상쇄되어 웰 접합 부근에서 순수한 결함 농도가 현저하게 감소하고, 웰 접합의 누설전류가 감소한다.FIG. 5 shows a purity defect profile for the figure shown in FIG. 4, where 21 is a pupil formed in the silicon lattice during implantation of the second P well and 32 is formed in the silicon lattice during implantation of the second P well. 33, which is an impurity formed in the silicon lattice during the implantation of the second P well ion, and 24 is an impurity formed between the lattice formed in the silicon lattice during the N well ion implantation. In the case where the distribution of interstitial impurities 33 formed during ion implantation of the pupil 32 and the second P well is close to each other, the net defect concentration is significantly reduced near the well junction, and the leakage current of the well junction is reduced. do.
본 발명의 다른 실시에는 N형 웰(2)을 형성하기 위한 이온주입에너지를 종래보다 더 큰 에너지를 이용하고, 제2P웰(1)을 형성하기 위한 이온주입에너지를 종래와 동일한 이온주입 에너지를 이용하여 N웰의 이온주입 시 형성된 동공(14)와 제2P웰의 이온주입 시 형성된 격자간 불순물(15) 영역이 근접하게 형성하는 것이다.In another embodiment of the present invention, the ion implantation energy for forming the N-type well 2 is larger than that of the conventional art, and the ion implantation energy for forming the second P well 1 is the same as the conventional implantation energy. The hole 14 formed during the ion implantation of the N well and the interstitial impurity 15 region formed during the ion implantation of the second P well are closely formed.
본 발명의 또 다른 실시예는 N웰과 제2P웰의 이온주입 에너지는 종래와 동일하게 하면서 이온주입 도즈량을 변화 시켜 순수 결함의 농도를 줄이는 방법이 있다.Another embodiment of the present invention is a method of reducing the concentration of pure defects by changing the ion implantation dose while maintaining the ion implantation energy of the N well and the second P well the same.
상기한 발명에 의하면 3중 웰 형성시 상기 제2도전형의 웰의 이온주입 시 형성되는 동공과 제1도전형의 제2웰의 이온주입 시 형성되는 격자간 불순물 영역이 근접하게 형성함으로서 실리콘 격자내의 격자간 불순물과 동공의 분포가 서로 상쇄되어 웰 접합 누설 전류를 줄일 수 있는 효과가 있다.According to the above-described invention, the silicon lattice is formed by the proximity of the interstitial impurity regions formed during ion implantation of the wells of the second conductivity type and the implantation holes of the second conductivity type wells when the triple well is formed. The distribution of impurities and inter-lattices within the lattice are canceled with each other, thereby reducing the well junction leakage current.
Claims (3)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950018871A KR0143252B1 (en) | 1995-06-30 | 1995-06-30 | Triple well formation method |
| CN96110390A CN1049068C (en) | 1995-06-30 | 1996-06-28 | Method for forming triple well |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950018871A KR0143252B1 (en) | 1995-06-30 | 1995-06-30 | Triple well formation method |
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| Publication Number | Publication Date |
|---|---|
| KR970003942A KR970003942A (en) | 1997-01-29 |
| KR0143252B1 true KR0143252B1 (en) | 1998-07-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019950018871A KR0143252B1 (en) | 1995-06-30 | 1995-06-30 | Triple well formation method |
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| KR (1) | KR0143252B1 (en) |
| CN (1) | CN1049068C (en) |
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| KR970003942A (en) | 1997-01-29 |
| CN1146068A (en) | 1997-03-26 |
| CN1049068C (en) | 2000-02-02 |
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