KR0142953B1 - Back bias voltage generator ciruit of semiconductor memory apparatus - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a back bias voltage generating circuit of a semiconductor memory device.

2. The technical problem to be solved by the invention

Implementing back bias voltage generation circuit that reduces current consumption in self refresh mode, generates a certain level of back bias voltage, and easily sets up back bias voltage level when performing normal mode in self refresh mode. do.

3. Summary of Solution to Invention

An oscillating means which is deactivated in the refresh mode operation in response to the refresh activation signal and activated in the normal mode operation to generate a charge pump clock; And a charge pumping means for generating a back bias voltage at a normal level in normal mode operation and generating a back bias voltage at a reference level in refresh mode operation in response to the charge pump clock.

4. Important uses of the invention

The amount of current consumed in the self refresh mode can be reduced.

Description

Back bias voltage generation circuit of semiconductor memory device

1 is a configuration diagram of a conventional back bias voltage generation circuit.

2 is a timing diagram according to the configuration of FIG.

3 is a configuration diagram of a back bias voltage generation circuit according to the present invention.

4 is a timing diagram according to the configuration of FIG.

5 is a self refresh activation signal according to the present invention ( A diagram showing the principle for generating the

* Explanation of symbols for main parts of the drawings

30: oscillator 40: charge pumping circuit

60: voltage level detection circuit

The present invention relates to a semiconductor memory device, and more particularly to a back bias voltage generation circuit of a semiconductor memory device.

In general, lowering the power of semiconductor memory devices, particularly Dynamic Random Access Memory (DRAM), is a great advantage, and this trend has recently become stronger. As a solution for this, data retention mode (or self refresh mode) is used and used in DRAM, which performs only minimal operations for information retention of memory cells. This is to minimize power consumption when not accessed.

For example, assuming that the memory cell has a data retention time of 250 ms and a refresh cycle of 1 kHz, if the chip's self-refresh operation is performed every 250 μs (250 ms ÷ 1 kHz ≒ 250 μs), the loss of preserved data will be avoided. You can prevent it. In this case, if the self-refresh operation is performed every 200 μs in consideration of the operation margin, the data of the cell can be almost completely preserved. On the other hand, assuming that the current consumption for 200ns is 100mA while reading or writing data in the memory cell once, only 100μA ((200ns ÷ 200μs) × 100mA) is consumed during the 200μs refresh cycle of data. Can also preserve data.

In reality, however, there is always a current flowing at 100mA for 200ns regardless of chip operation, also known as standby current. If the standby current is assumed to be 50 μA, the current consumption I _SELF in the self-refresh mode can be expressed by Equation (1) below.

I _SELF = 50 μA + (100 mA-50 μA) x (200 ns / 200 μs) ≒ 150 μA. … (One)

Looking at Equation (1), the portion of the standby current 50μA occupies a considerable amount of current I _SELF in the self-refresh mode. Most of these standby currents are due to the influence of the reference voltage generator existing in the chip, in particular the back bias voltage generator circuit applying the back bias voltage to the chip.

Meanwhile, in DRAM, a back bias voltage generation circuit is essential for reducing bit line junction capacitance, stabilizing a threshold voltage of an NMOS transistor, and preventing a latch up of a chip.

FIG. 1 shows a configuration of such a back bias voltage generation circuit in the related art, and a back bias enable signal. As E is applied, the back bias voltage V _BB is pumped by the oscillator 10 generating a square wave of a predetermined frequency and the charge charged in the charge pumping capacitor 22 according to the logic state of the square wave generated in the oscillator 10. It consists of a charge pumping circuit 20 for generating a.

FIG. 2 is a timing diagram of a back bias voltage generation circuit as shown in FIG. 1, and FIG. 2A shows a back bias enable signal. E is shown, and the second (B) shows the square wave appearing at the output node (N1) of the oscillator 10, the second diagram (C) is shown as the output node (N3) of the charge pumping circuit 20. The output back bias voltage V _BB is shown.

1 and 2, a low-level back bias enable signal is initially present. When E is applied, a high level signal is output to the NAND gate 12, and the two inverters 14 and 16 buffer the high level signal and then output a high level signal. At this time, the low-level back bias enable signal When E transitions to a high level, a high level signal is inputted to both input terminals of the NAND gate 12, so a low level signal is output. Accordingly, a low level signal is output to the output node N1 of the oscillator 10. The signal is output. Next, a high level back bias enable signal If E is still applied, a high level signal is applied to one input terminal of the NAND gate 12 and a low level signal is applied to the other input terminal, so the high level signal is again applied to the output node N1 of the oscillator 10. Is output. In this manner, the output node N1 of the oscillator 10 repeatedly displays high-level and low-level signals, that is, square waves as shown in FIG. Then, the square wave of FIG. 2B is applied to the charge pumping capacitor 22 of the charge pump circuit 20.

On the other hand, when the signal input to the charge pumping capacitor 22 is a rising edge of the square wave, the capacitor 22 starts charging. At this point, since the high level signal appears at the node N2, the NMOS transistor 24 is turned on and the NMOS transistor 26 is turned off. As a result, the charge of the node N2 is bypassed through the NMOS transistor 24.

On the other hand, if the signal input to the charge pumping capacitor 22 is a falling edge of the square wave, the capacitor 22 starts to discharge. At this point, since the negative voltage appears at the node N2, the NMOS transistor 24 is turned off. At this time, when the voltage of the node N3 becomes higher than the threshold voltage of the NMOS transistor 26 than the voltage of the node N2, the NMOS transistor 26 is turned on. Accordingly, the negative charge of the node N2 is transferred to the node N3 through the enMOS transistor 26 and applied to the substrate of the semiconductor memory device as a back bias voltage VBB of -2 volts to -3 volts.

The back bias voltage generator circuit starts operation by a power source applied to a chip, and the operation of the oscillator 10 is stopped by a voltage level detection circuit (not shown) that is typically connected to the back bias voltage generator circuit. It works until Such a back bias voltage generation circuit has a great influence on the formation of current consumption, particularly standby current, in the self-refresh mode of DRAM.

In order to reduce the current consumed by the back bias voltage generating circuit, a method of operating the back bias voltage generating circuit only during the time actually involved in the operation of the chip in the self refresh mode has been proposed. The method is disclosed under the heading A 38-ns 4-Mb DRAM with a Battery-Backup Mode on pages 1112-1117 of IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL 25, NO.5, issued October 1990. However, since the method operates the back bias voltage generating circuit only for a given time, it is difficult to maintain a constant back bias voltage level. In addition, there is a problem in that it is not easy to set up the back bias voltage level when starting a mode of reading or writing data (hereinafter, referred to as a normal mode) in the self refresh mode.

Accordingly, an object of the present invention is to provide a back bias voltage generation circuit for reducing current consumed in a self refresh mode of a semiconductor memory device.

Another object of the present invention is to provide a back bias voltage generation circuit which maintains a constant back bias voltage level in a self refresh mode of a semiconductor memory device.

It is still another object of the present invention to provide a back bias voltage generation circuit for easily setting up a back bias voltage level when performing a normal mode operation in a self refresh mode of a semiconductor memory device.

According to the above objects, a normal level back bias voltage is generated during normal mode operation of a semiconductor memory device, and less than an absolute value of the back bias voltage during normal mode operation during a self-refresh mode operation. Towards a back bias voltage generation circuit that generates a back bias voltage to reduce current consumption.

In addition, the back bias voltage generation circuit according to the present invention,

An oscillation means which is deactivated in the refresh mode operation in response to the refresh activation signal and activated in the normal mode operation to generate the charge pump clock;

And a charge pumping means for generating a back bias voltage at a normal level in normal mode operation and a back bias voltage at a reference level in refresh mode operation in response to the charge pump clock.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

The back bias voltage generation circuit according to the present invention generates a back bias voltage of a normal level in the normal mode operation, and generates a back bias voltage having a magnitude smaller than the absolute value of the back bias voltage in the normal mode operation in the self refresh mode. Occurs. However, in the following description, the back bias voltage generation circuit generates a back bias voltage of -2 volts to -3 volts in the normal mode operation, and generates a back bias voltage of the ground level in the self refresh mode operation. Note that the explanation.

3 is a configuration diagram of a back bias voltage generation circuit according to the present invention, and the inverted refresh activation signal ( An oscillator 30 deactivated during the refresh mode operation and activated during the normal mode operation to generate a charge pump clock of a predetermined frequency in response to A charge pumping circuit 40 generating a back bias voltage of a normal level (-2 volts to -3 volts) in a normal mode operation and a back bias voltage of a ground level in a refresh mode operation in response to the charge pump clock; ; The voltage detection circuit 60 detects the back bias voltage level output from the charge pumping circuit 40 and blocks the operation of the oscillator 30 when the voltage level below the normal level is detected.

4 is a timing diagram according to the configuration of FIG. 3, and FIG. 4A is a refresh activation signal ( SR is shown, and FIG. 4B shows the inverted refresh activation signal FIG. 4C shows a charge pump clock that is a square wave of a predetermined frequency appearing on the output node N4 of the oscillator 30, and FIG. 4C shows a node N7. Fig. 4E shows the back bias voltage appearing on the output node N6 of the charge pumping circuit 40, and Fig. 4F shows the switching control signal ) Is shown. In FIG. 4, reference numeral T1 denotes an interval in which the back bias circuit output is at a low level because the back bias level is higher than the target value during normal mode operation of the back bias voltage generation circuit, and thus the back bias circuit is not operated. The section according to the operation in the normal mode of the bias voltage generation circuit is shown. Reference numeral T3 denotes a cell refresh mode section.

The operation in the normal mode and the operation in the refresh mode of the back bias voltage generation circuit according to the present invention will now be described with reference to FIGS. 3 to 4.

First, the operation in the section T2 corresponding to the normal mode of the back bias voltage generation circuit will be described.

In normal mode, the low-level refresh enable signal ( SR) and the high level inverted refresh enable signal ( ) Is input to one input terminal 32a of the NAND gate 32 of the oscillator 30. The other high level signal is applied from the node N7 of the voltage level detection circuit 60 to the other input terminal 32b of the NAND gate 32. This is because the V _BB level is not sufficiently low, and the output of the back bias circuit becomes high by the resistance value of the resistance value 64 of the resistance ratio 62). In this case, it is assumed that a high level signal is applied to another input terminal 32c of the NAND gate 32. Then, a low level signal is output to the output terminal of the NAND gate 32, and a low level signal buffered through two inverters 34 and 36 is output to the output node N4 of the oscillator 30. .

In the next normal mode operation, a high level signal is applied to the input terminal 32a of the NAND gate 32, and a high level signal is also applied to the other input terminal 32b of the NAND gate 32, The low level signal is also applied to the other input terminal 32c of (32). Then, a high level signal is output to the output terminal of the NAND gate 32, and a high level signal buffered through the two inverters 34 and 36 is output to the output node N4 of the oscillator 30. .

As described above, the output node N4 of the oscillator 30 in the normal mode repeatedly shows a high level and a low level signal, that is, a charge pumping clock as shown in FIG. The charge pumping clock is applied to the charge pumping capacitor 42 of the charge pumping circuit 40.

Meanwhile, when the signal applied to the charge pumping capacitor 42 is a rising edge of the charge pumping clock, the capacitor 42 starts charging. At this point, the high level signal is displayed at the node N5, so the NMOS transistor 44 is turned on and the NMOS transistor 46 is turned off. As a result, the charge of the node N4 is bypassed through the NMOS transistor 44.

On the other hand, when the signal applied to the charge pumping capacitor 42 is a falling edge of the charge pumping clock, the capacitor 42 starts discharging. At this point, since the negative voltage appears at the node N5, the NMOS transistor 44 is turned off. At this time, when the voltage of the node N6 becomes higher than the threshold voltage of the NMOS transistor 46 than the voltage of the node N3, the NMOS transistor 46 is turned on. As a result, the negative charge of the node N5 is output as the negative back bias voltage to the node N6 through the NMOS transistor 46. At this time, the switching control signal shown in FIG. ) Is a high level signal, the PMOS transistor 54 is turned off, the NMOS transistor 52 is turned on, and a negative back bias voltage is applied to the gate terminal of the NMOS transistor 56 so that the NMOS Transistor 56 is turned off.

As a result, the back bias voltage appearing at the output node N6 of the charge pumping circuit 40 is lowered by the coupling of the node N5 by the oscillator 30, and the back bias voltage level is lowered to any target value. When the in period T1 is reached, the operation of the oscillator 30 is cut off by the voltage level detection circuit 60. When the period T1 is reached, the turn-on resistance values of the PMOS transistor 64 and the NMOS transistor 66 of the voltage level detection circuit 60 are lowered so that a low level signal appears at the node N7. Accordingly, since a low level signal is applied to the input terminal 32b of the NAND gate 32, a high level signal is output to the output terminal of the NAND gate 32. This high level signal is buffered via two inverters 34 and 36 and then output as a high level signal to node N4. The node N4 continuously displays a high level signal until the output of the voltage level detection circuit 60 becomes a high level, that is, until the back bias voltage level becomes above a certain target value.

When the back bias voltage level is higher than a certain target value, the oscillator 30 resumes operation to repeatedly generate the charge pumping clock. Accordingly, a back bias voltage VBB of -2 volts to -3 volts is output to the output node N6 of the charge pumping circuit 40, and the back bias voltage is applied to the substrate of the semiconductor memory device.

Next, the operation in the section T3 corresponding to the refresh mode of the back bias voltage generation circuit will be described.

In the refresh mode, a high level refresh enable signal ( SR) and the low level inverted refresh enable signal ( ) Is input to one input terminal 32a of the NAND gate 32 of the oscillator 30. Then, a high level signal is output to the output terminal of the NAND gate 32, and a high level signal buffered through the two inverters 34 and 36 is output to the output node N4 of the oscillator 30. .

As such, the high level signal is continuously displayed on the output node N4 of the oscillator 30 in the refresh mode as shown in FIG. When the high level charge pumping clock is applied to the charge pumping capacitor 42 of the charge pumping circuit 40, at this point, the high voltage signal is displayed at the node N5, so that the NMOS transistor 44 is turned on. NMOS transistor 46 is turned off. As a result, the charge of the node N4 is bypassed through the NMOS transistor 44. At this time, a high level switching control signal as shown in FIG. ) Is a low level signal, so the NMOS transistor 52 is turned off and the PMOS transistor 54 is turned on. Then, a high level signal is applied to the gate terminal of the NMOS transistor 56, and the NMOS transistor 56 is turned on so that the potential of the ground terminal is displayed at the output node N6 of the charge pumping circuit 40.

In the refresh mode, when the absolute value of the back bias voltage appearing at the output node N6 of the charge pumping circuit 40 is greater than the threshold voltage of the NMOS transistor 52, the PMOS transistor 54 and the NMOS transistor ( A current path through the 52) is formed to reduce the back bias voltage level. When the absolute value of the back bias voltage is equal to the threshold voltage of the NMOS transistor 52, the current path through the NMOS transistor 52 is blocked. do.

As described above, in the refresh mode of the DRAM, a self refresh activation signal ( SR) and switching control signal Current consumption can be reduced by controlling the operation of the back-bias voltage generation circuit by applying the ground potential to the substrate.

Although the back bias voltage generating circuit has been described as applying a ground potential to the substrate in the refresh mode of the DRAM, it should be noted that the present invention holds true even when a ground bias or a back bias voltage close to the ground potential is applied to the substrate.

5 is a refresh activation signal according to the present invention ( FIG. 5A illustrates a row address signal (RAS) generally used in a semiconductor memory device. FIG. 5B illustrates a column. A column address signal (CAS) is illustrated.

Referring to FIGS. 5A and 5B, the CBR (CAS Before RAS) timing at which the column address signal descends before the row address signal descends is performed, thereby performing the self refresh operation. Refresh enable signal for SR). In other words, if access is not made for T4 (preferably 125μs) at the timing of the CD, the self refresh mode starts and the refresh activation signal ( SR).

As described above, when the back bias voltage level approaches the ground level in the self-refresh mode, the current reduction amount due to the back bias voltage generation circuit and the junction leakage current amount of the memory cell can be reduced, thereby reducing the data retention time of the cell itself. There is an advantage to increase. In addition, in the self-refresh mode, the operation of the chip can be performed very intermittently, thereby preventing the occurrence of latch-up in the back bias voltage generation circuit.

Claims (3)

A back bias voltage generation circuit for supplying a back bias voltage to a substrate of a semiconductor memory device, the back bias voltage generating circuit comprising: an oscillating means which is inactivated in a refresh mode operation in response to a refresh activation signal and activated in a normal mode operation to generate a charge pump clock; And a charge pumping means for generating a back bias voltage of a normal level in the normal mode operation in response to a charge pump clock, and generating a back bias voltage of a reference level in the refresh mode operation. The reference level of claim 1, wherein the charge pumping means generates the back bias voltage of the normal level in the normal mode operation, and the reference level at a level smaller than an absolute value of the back bias voltage of the normal level in the refresh mode operation. A back bias voltage generation circuit, characterized in that for generating a back bias voltage. The back bias voltage generating circuit according to claim 1, wherein said charge pumping means generates a back bias voltage of said reference level of ground voltage.