KR0142035B1 - Ds/ cdma receiver using moving averaged pilot signals for weighting rotation - Google Patents

Abstract

In a direct sequence spread spectrum receiver, the spread orthogonal data signal and spread orthogonal pilot signal are correlated with the orthogonal despread sequence at the chip rate. These despread signals are integrated at a symbol rate to output orthogonal data symbols and orthogonal pilot symbols. A predetermined number of pilot symbols of each phase component are moving averaged. Each phase component of the orthogonal data symbol is weighted by the moving average of the corresponding phase component of the pilot symbol and summed with the other weighted components of the data symbol to produce an output signal of the spread spectrum receiver.

Description

Direct Sequence Spread Spectrum (DS / CDMA) Receiver Using Phase Shifted Orthogonal Data Symbol Vector and Moving Averaged Pilot Signal for Weighting

1 is a block diagram of a direct sequence spread spectrum receiver according to the present invention;

2 is a block diagram of a phase shift controller of the synchatch tracking circuit of FIG.

3 shows a graphical representation of a data signal and a pilot signal in a complex plane,

4 and 5 are flow charts describing the sequence of operations performed by the controller of FIG. 2;

FIG. 6 is a timing diagram showing an example of a series of correlation values accumulated in the accumulator of FIG. 1 in relation to signal power varying with Rayleigh fading,

* Explanation of symbols for main parts of drawings

10; Spherical demodulator 11; Analog to Digital Converter

12; Rake receiver 13; Sync Acquisition Tracking Circuit

14; Channel decoders 21, 22 and 23; Demodulator

24,29; Adder 30; Exclusive logic-0R gate

31i, 31q; Multipliers 32i, 32q; switch

33i, 33q, 36i, 36q, 42: Totalizer 34i, 34q: Moving average circuit

35i, 35q: correlator 37i, 36q: delay circuit

40: orthogonal correlator 41, 54: PN sequence generator

43: absolute value circuit 44, 52: selector

45: phase shift controller 50: controller

A1-AN: Accumulator 53: Walsh Code Generator

FIELD OF THE INVENTION The present invention relates generally to direct sequences spread spectrum receivers, particularly for cellular mobile communication systems where signals are severely affected by Ray1eighfading. Direct sequence spread spectrum technology for

Commercial interest in direct sequence spread spectrum communication systems that serve more users than other multiple access technologies offer has recently been fueled by the potential strength of such systems. In the cell-site station of a DS / CDMA system, data symbols are assigned to the cell-location as well as the orthogona1 wa1sh code assigned to the channel through which the spread signal is transmitted. Spread by multiplying a frequency orthogonal pseudo-randum number (PN) sequence with the data symbol. The pilot (pi1ot) signal is superimposed on the data symbol sequence to give the mobile base station a synchatch tracking operation. The mobile base station shifts the phase timing of the local PN sequence by a predetermined amount whenever correlation between the received local sequences is taken, and when the correlation exceeds a certain threshold, provides the correct phase timing for the local sequence. To determine this, we use a sliding correlation technique. Once synchronization is established, the phase difference is monitored and kept within a portion of the chip interval. During transmission, the signal is subjected to reflections and scattering from various terrain structures, creating a complex pattern of standing waves due to mutual interference of the multipath signals at the mobile base station. As a result, the propagation path of the signal exhibits an electric field intensity distribution that approximates the Rayleigh distribution. Thus, the signal is called Rayleigh fading and the envelope of the signal and its phase in the mobile base station vary considerably.

Under these adverse conditions, the transmitted signal is varied by noise and the chip-rate phase timing of the signal deviates momentarily from the local timing of the receiver.

It is therefore an object of the present invention to provide a direct sequence spread spectrum receiver that can overcome the effects of noise introduced during transmission.

According to the present invention, a correlator for multiplying an in-phase and quadrature spread data signal and an in-phase and quadrature spread pilot signal by a chip rate with an orthogonal despreading sequence to output an in-phase and quadrature orthogonal despread data signal and an in-phase and nodular despread pilot signal A direct sequence spread spectrum receiver is provided that includes. The data accumulator integrates in-phase and spherical despreading data signals at symbol rates to output in-phase and spherical data symbols, and the pilot integrator integrates in-phase and spherical despreading pilot signals at symbol rates to output in-phase and spherical data symbols. First and second moving average means are provided for continuously summing a predetermined number of in-phase and spherical pilot symbols to output first and second moving average values, respectively. In-phase and spherical data symbols from the data accumulator are multiplied by the first and second moving average values by the first and second multipliers, respectively. The output signal of the direct sequence spread spectrum receiver is output by summing the outputs of the first and second multipliers. Since the pilot symbols are moving averaged and the data symbols are weighted and the phase is rotated by the moving average value, the noise effect on the pilot signal, and consequently the noise effect on the weighted and rotated data signal is reduced.

Preferably, a delay is introduced into each of the in-phase and spherical data symbols by an amount corresponding to half of a predetermined number of in-phase pilot symbols prior to being applied to the first and second multipliers. Thus, for each delayed data symbol, the moving average is derived from half of the predetermined number of pilot symbols preceding the delayed symbol and half of the predetermined number of pilot symbols following the delayed symbol.

It is desirable to use multiple demodulators and adders connected to the demodulator outputs in a multipath fading channel. Each demodulator includes a correlator for multiplying in-phase and quadrature spreading data signals and in-phase and quadrature spreading pilot signals by the chip rate at orthogonal despreading sequences to output in-phase and spherical orthogonal despreading data signals and in-phase and spherical despreading pilot signals. A direct sequence spread spectrum receiver is provided.

The data accumulator integrates in-phase and spherical despreading data signals at symbol rates to output in-phase and spherical data symbols, and the pilot integrator integrates in-phase and spherical despreading pilot signals at symbol rates to output in-phase and spherical data symbols.

First and second moving average means are provided for continuously summing a predetermined number of in-phase and spherical pilot symbols to output first and second moving average values, respectively. In-phase and spherical data symbols from the data accumulator are multiplied by the first and second moving average values by the first and second multipliers, respectively. The output signal of the demodulator is output by summing the outputs of the first and second multipliers and applied to the adder.

In a more preferred embodiment, a synchronization acquisition tracking circuit is provided comprising a register for storing a plurality of phase position signals and a first selector for periodically selecting each one of said phase position signals in response to a shift command signal. The pseudo-random number (PN) generator outputs an orthogonal PN sequence according to the selected phase position signal, the correlator implements correlation between the in-phase and nodal spread pilot signal and the orthogonal PN sequence to output in-phase and nodal despread pilot signals, The in-phase and spherical despreading pilot signals are then integrated over a predetermined interval. Both of the in-phase and innocuous signal integrated are squared and the results are summed to produce a correlation power value. Multiple accumulators are provided. The second selector periodically selects each of the accumulators so that the phase position signal corresponding to the accumulator is repeatedly selected to output the sum of the correlation values output by the correlator for the time applied to the PN sequence generator, and the correlation values are selected in the selected accumulator. Respond to the shift command signal by applying. The sum of the largest correlation values is selected from the outputs of all the accumulators, and the phase position signal corresponding to the selected sum is selected. An orthogonal despreading sequence of the receiver is generated corresponding to the selected phase position signal. If multiple demodulators are used, a larger number of total sum values are selected and the corresponding phase position signals are selected to generate a plurality of orthogonal despreading sequences.

The shift command signal is preferably generated at a higher rate than the rate at which Rayleigh fading occurs.

The invention is described in more detail with reference to the accompanying drawings.

1 shows a receiving circuit of a mobile base station for a DS / CDMA cellular communication system according to the present invention. In a cell-location base station, the baseband downlink (cell to mobile station) signal is initially encoded by the channel encoder in a known coded form optimized for wireless transmission. At a much higher chip rate than the symbol rate, the symbols of the coded signal are made using a PN (Pseudo-random number) spreading sequence (PNi and PNq) that is commonly assigned to the service area in which the mobile base station is currently located. It is further spread using an orthogonal Walsh code uniquely assigned to the downlink channel. Pilot signals that are all zero or one-value series are spread at the same chip rate using the same PN sequences (PNi and PNq) with orthogonal Walsh full zero codes. The in-phase and spherical components of the spread spectrum downlink signal combine with the corresponding components of the spread spectrum pilot signal to output I and Q signals that are modulated, amplified, and transmitted with an orthogonal radio-frequency carrier.

The spread spectrum signal from the cell-location is received by the mobile base station and fed to a spherical demodulator 10 comprising radio-frequency amplification and demodulation stages. Using orthogonal local carriers, demodulator 10 recovers the original in-phase signal i and the spherical signal q. Preferably, the analog to digital converter 11 is used to convert the i and q signals in digital form. The receiving circuit includes a RAKE receiver 12, a sync acquisition tracking circuit 13, and a channel decoder 14.

The rake, receiver 12 comprises a number of equivalent demodulators 21, 22, 23. For practical purposes, three demodulators are sufficient to account for multipath-fading related problems. For clarity, only one demodulator 21 is shown in detail. The demodulator 21 includes a pair of multipliers 31i and 31q for the product of the I and Q digital signals from the A / D converter 11 and the pseudo-random despreading sequences PNi1 and PNq1, which are multipliers 31i. ) Outputs in-phase output i1 = 1 × PNi1 and the spherical output signal q1 = Q × PNq1 from the multiplier 31q. The PN sequences PNi1 and PNq1 are the two inputs of the exclusive logic-OR gate 30 which output the switching signal. The output signal i1 of the multiplier 31i and the output signal q1 of the multiplier 31q become inputs of the switches 32i and 32q. If the switching signal is binary 1, output 32i of multiplier 32i appears as signal Ids at the output of switch 32i. If the switching signal is binary 0, the signal Ids becomes equal to the output of multiplier 32q, i.e. q1. Similarly, when the switching signal is 1, the output of the multiplier 31q appears at the output of the switch 32q as the signal Qds. If not, the output of multiplier 31i is represented as Qds. Since the pilot signal was spread at the transmitter using an all-zero Walsh code, the signals Ids and Qds represent the in-phase and globular components of the despread pilot signal.

In order to extract the pilot signal component, each of the in-phase and globular signals (Ids and Qds) are integrated over a period of n chips (where n represents the number of chips for which data symbols have been spread at the transmitter). 33q). In order to absorb random noise, another accumulator, or moving average circuits 34i and 34q, is connected to each of the accumulators 33i and 33q. In the moving average circuit, the integrated Ids and Qds signals are divided into m symbols ( Where m is a predetermined number).

In particular, each moving average circuit is implemented with an m-stage register and an adder. The shift register receives an input signal from the circuit in front of it and an adder is connected to all stages of the register to successively sum the values held by the register so that the adder is the m pilot symbol value (corresponding to the m data symbol) for each phase component. A signal representing the moving average of is outputted.

Since the data signal has been spread to the channel-check Walsh code at the transmitter, the Ids and Qds signals are applied to multipliers (correlators) 35i and 35q, respectively, which are applied to each multiplier from the sync acquisition tracking circuit 13. Multiplied by the supplied local Walsh code (Wj; j = 1). Multipliers 35i and 35q outputs are fed to accumulators 36i and 36q, respectively, to be integrated over the n-chip intervals to produce the original for each phase component. Will print a duplicate of the symbol. Each of the accumulators 36i and 36q outputs is fed to delay circuits 37i and 36q which have a delay of m / 2 symbols.

Each of the in-phase and globular data symbols is delayed by an interval of m / 2 heart lights so that the delayed symbols of each phase component correspond to the midpoint stage of the moving average shift register. Thus, for each delayed data symbol, the moving average value is derived from half of the predetermined number of pilot symbols preceding the delayed symbol and half of the predetermined number of pilot symbols following the delayed symbol.

If the chip-rate timing of the PN sequences (PNi1, PNq1) and Walsh code (W1) are in proper phase relationship with the input I and Q signals, the despread energy of the input signal is despread (collected) and the pilot signal components are r _p cosθ _p and r _p sinθ _p as large amplitudes at the outputs of the accumulators 34i and 34q, and the data signal components are rd cosθd and rd sinθd as outputs of the m / 2 symbol delay circuits 37i and 37q, respectively. Will appear in large amplitude.

The vector of pilot and data signals is shown in FIG. As shown in the coordinate system of the IQ complex plane, the amplitude of the pilot signal has a small difference Δθ between negligibly judging always large and θ _p and θ _d than the amplitude of the data signal is compared with θ _p and θ _d.

To obtain the output signal r1 of the demodulator 21, the data signal vector is projected onto the I-axis of the coordinate system by multiplying each data signal component by the conjugate complex number of the corresponding pilot signal component and summing the values thus obtained. do.

r1 = Re [r _d cosθ _d (r _p cosθ _p -jr _p sinθ _p ) +

r _d sinθ _d (r _p sinθ _p + jr _p cosθ _p ) 1

= Re (r _p r _d (cosθ _p cosθ _d + sinθ _p sin θ _d ) +

jr _p r _d (cosθ _p sin θ _d -sinθ _p cosθ _d )]

= r _p r _d (cosθ _p cosθ _d + sinθ _p sinθ _d )

= r _p r _d cos (θ _p -θ _d ) (1)

Equation (1) indicates that the unit vector of the data signal is rotated clockwise on the I axis of the IQ complex plane and has a weight of a scalar r _p r _d .

If some data symbols are severely contaminated by noise during transmission, the corresponding pilot symbols are shift averaged so that the noise effect on the pilot signal is reduced in this way, thereby reducing the noise effect on the signal r1.

In FIG. 1, the in-phase signal is multiplied by the multiplier 38i to output the in-phase product by multiplying the in-phase signal component and the in-phase data signal component by the multiplier 38i, and outputting the spherical product by multiplying the spherical pilot signal and the data signal component using the multiplier 38q. The output signal r1 is obtained by summing the output values with the adder 29. In the same way, the output signals r2 and r3 are output by the demodulators 22 and 23, which are summed by the adder 24 with the output signal r1 of the demodulator 21 so that this adder output is the channel of the transmitter. The channel decoder 14 undergoes a process opposite to that of the encoder.

In the adder 24, the signals r1, r2, r3 simply need to be summed by the rotation of the data vector on the I-Q complex plane I-axis. The pilot vector weights the data symbols and the stronger multipath signal is a stronger moving averaged pilot, which is a strong signal indicating low level fading, so that the use of the pilot vector in the above described rotation method is dependent on the signal output from adder 24. This will reduce the fading effect.

The synchronization acquisition tracking circuit 13 includes an orthogonal correlator 40 and a PN sequence generator 41 for generating an orthogonal despreading sequence from the phase shift controller 45 in accordance with the phase position signal. As described, the phase shift signal is generated at a window interval Tw that is much smaller than the interval where Rayleigh fading occurs. The window period Tw is equal to L × Tc, where Tc is the chip rate and L is selected so that the pilot signal will never do more than π / 2 radians of rotation during the period of L consecutive chips, and PN sequence generator 41 Is phase shifted in the period Tw and the phase shift is repeated periodically when phase shifted by N times (where N represents the number of phases to be shifted within Tw x N) for each cycle. The I and Q data signals from the A / D converter 11 are applied to the correlator 40 where the I and Q pilot signal components are despread and the correlation value is detected for each pilot signal phase component during the window period Tw. do. An L-chip accumulator 42 is connected to the output of the correlator 40, in which the correlation values of the respective pilot signal phase components for the L chip are summed to sum the in phase and the spherical phase components of the pilot signal. Output the vector. The output of the accumulator 42 is provided to an absolute value circuit 43 where the result for these two vector components representing the pilot's cross-correlation magnitudes (ie, the square root of the sum of the squares of each sum vector component). A scalar vector of the ordinary vector is derived within the window interval Tw.

The output of the absolute value circuit 43 is applied to the input selector 44, which is controlled by a phase shift signal that changes the terminal position of its moving contact arm. Accumulators A1 to AN are connected to terminal positions of selector 43, respectively. Each of the accumulators A1-AN provides the sum of the M input signals from the corresponding terminals of the selector 43 and is reset in response to the signal from the phase shift controller 45. The outputs of the accumulators A1 to AN are fed to the controller 45, which signals supplied to the controller determine their magnitude sequences compared to the other sum values and select the three largest correlation values.

As shown in detail in FIG. 2, the phase shift controller 45 stores the phase position signals P1 (= φo + Δφ) to PN (= φo + NΔφ) loaded from the phase position data source 51. Registers PRa and registers RS0 for storing the correlation sum signals S1 to SN loaded from the accumulators A1 to AN. Each of the phase position signals stored in the register PRa is selectively supplied to the PN sequence generator 52 through the selector 52. Loading the appropriate signal into registers PRa and RS0 and selecting the phase position signal with selector 52 is controlled by controller 50. The registers RS1-RS3 and RP1-RP3 are connected to the controller 50. The three largest correlation sum values are stored in registers RS1 through RS3, respectively, and the corresponding phase position signals are stored in registers RP1 through RP3. Phase position signals stored in registers RP1-RP3 are loaded into output registers OR1-0R3, respectively, where the registers are coupled to Walsh code generator 53 and PN sequence generator 54. Using the phase position signals stored in the output registers, Walsh codes (W1, W2, W3) and three sets of orthogonal PN sequences (PNi1, PNq1, PNi2, PNq2, PNi3, PNq3) are generated, each of which is a demodulator (21, 22, 23).

Initially, the controller 50 commands the phase position data source 51 to cause a set of phase position signals P1-PN to be loaded into the register PRa. The controller 50 includes a clock generator (not shown), which uses the clock to generate a shift command pulse in the period Tw and supply it to the selectors 44 and 52. The phase position signals P1-PN are continuously selected in response to the shift command signal and are applied to the PN sequence generator 41. In response to each phase position signal, the PN sequence generator 41 phases the despread PN sequence. The timing is shifted by kΔφ (where k = 1.2 ..... N). During each successive window period Tw, the L correlation values are summed by the accumulator 42 and the summated accumulators A1 to corresponding to the phase position signal applied to the PN sequence generator 41 during the window period. Is applied via selector 44 in one of AN). This process is repeated M times for each phase position signal and therefore for each accumulator so that the sum total of the M correlation values in the accumulator is stored in the corresponding phase position. When the shift command signal is generated N x M repetitions, the phase position signal is transferred from register PRa to register PRb so that a new set of phase position signals can be loaded into register PRa, while the correlation sum is Subsequent determination of the greater of the values makes it possible to use the transmitted phase position signal during processing. At the same time, in the accumulators A1-AN, the corresponding phase position signals from the registers PRb are compared with each other to select the largest first, second and third values among the correlation sum values, and the output registers om-0R3. The correlation sum is loaded into the register RS0 to load it into.

The operation of the controller 50 will be described using the flowcharts of FIGS. 4 and 5. In FIG. 4, the synchronization acquisition starts at step 60 and resets all accumulators A1 to AN and sets N pairs. A new phase position signal P1-PN is loaded from the data source 51 into the register PRa. The process then proceeds to step 61 in which the count variable h is initialized to zero. Control proceeds to step 62 where a shift command pulse is supplied to the selectors 44 and 52 so that the phase position signal P1 is initially supplied to the PN generator 41, and the correlation value L times by the correlator 40. An abnormality is generated and summed by the accumulator 42 and stored in the accumulator A1. In step 63, the count variable h is incremented by 1 to proceed to step 64 to check if h is equal to or greater than N × M. If this condition is not satisfied, control returns to step 62 to read out the phase position signal P2 from the register PRa to the PN generator 41 and the controller 50 to accumulate the sum of the resulting L correlation values. To A2). The same operation proceeds until the determination at step 64 is assured, and the sum of the correlation sums S1 to SN is thus stored in the accumulators A1-AN with respect to the phase position signals P1-PN.

Control proceeds to step 65 where it transfers the phase position signal from register PRa to register PRb and returns to step 60 to repeat the shift operation for a set of new phase positions.

In FIG. 5, the read operation starts from step 70 when h is equal to N x M, in which the correlation sum S1-SN is loaded from the accumulators A1-AN into the register RSO and the register RS1. , RS2, RS3) are all reset to zero. In step 71, the count variables i and j are reset to zero and incremented one by one in steps 72 and 73 in succession. Count variable i (where i = 1 to 3) identifies registers RP1-RP3 and RS1-RS3 and variable j (where j = 1 to N) correlates with phase position signal P1-PN Check the sum (S1-SN). In decision step 74, the correlation sum Sj in the register RS0 is compared with the correlation sum si previously stored in the register RSi. If Sj is greater than si, control proceeds from step 74 to step 75 to set the correlation sum Sj to the register Rsi, to place the corresponding phase position signal Pj in the register PRb and register it ( RPi). If Sj is less than si, control proceeds to step 76 to check if j is equal to N. If j is not equal to N, steps 73, 74 and 75 are repeated for the next correlation sum Sj for testing the relative value and Sj.

Thus, the latter is zero and stored in register RS1 as data S1 and S1 is initially determined to be greater than the previous value since the next correlation sum S2 is compared with S1. If it is S2S1, steps 73 to 74 are repeated, and if S2S1, S1 is replaced with S2 in the register RS1 in step 75.

When the maximum correlation sum is determined for a set of N correlation values, the decision at step 76 is assured, and control goes to decision step 77 to exit the loop and checks whether i = 3. Otherwise, control proceeds to step 78 to remove the maximum value of register Rsi from register RS0, and control returns to step 72 until the third largest value is determined and stored in register RS3. The process is repeated. When this occurs, the determination at step 77 is assured, and control proceeds to step 79 to load the phase position signal from the registers RP1-RP3 to the output register OR1-0R3.

In this way, three correlation sums from the largest value are determined for a set of N correlation sums and the corresponding phase position signals are stored in output registers OR1, OR2, OR3. During the read operation, the shift operation is in progress for the next set of correlation sums for the next phase position signal.

Since the window interval Tw is far smaller than any interval taken from the sample points distributed in the interval Tw XN, where Rayleigh fading occurs, the rail-fading related signal power variation It is also distributed and averaged for each correlation sum.

On the other hand, conventional sync acquisition and tracking circuits using sliding window correlators have longer window intervals for the correlation sums A1, A2, A3, shown in dashed lines. As a result, each conventional correlation sum is severely affected by Rayleigh fading. The interval (L x M x N) where the product L that provides the amount of chips that can be used to correct the sample from the pilot signal (LXM) is sufficient to provide a valid correlation sum for each phase position, and where the N correlation sum is obtained The constant M is chosen so as not to deviate from the tolerance of this maximum frequency shift.

Claims (12)

Correlator means for multiplying in-phase and quadrature spreading data signals and in-phase and quadrature spreading pilot signals and orthogonal spreading sequences by a chip rate to output in-phase and quadrature despreading data signals and in-phase and spherical spreading pilot signals (30-32, 35) ); Data integrators 33i and 33q for integrating in-phase and spherical despreading data signals at a symbol rate to output in-phase and spherical data symbols; Pilot integrator means 36i and 36q for integrating in-phase and spherical despread pilot signals at the symbol rate to output in-phase and in-plane pilot symbols; First and second moving average means 34i and 34q for successively adding up a predetermined number of in-phase and spherical pilot symbols to output first and second moving average values, respectively; First and second multiplier means (38i, 38q) for multiplying in-phase and spherical data symbols of the data integrator means by the first and second moving average values, respectively; And means (39) for summing output signals of said first and second multiplier means. The first multiplier according to claim 1, further comprising: a first delaying the in-phase data symbol of the data accumulator by an amount corresponding to half of the predetermined number of in-phase pilot symbols and applying the delayed symbol to the first multiplier means 38i. Delay means 37i; And second delay means 37q for delaying the spherical data symbols of the data accumulator by an amount corresponding to half of the predetermined number of spherical pilot symbols and applying the delayed symbols to the first multiplier means 38q. The direct sequence spread spectrum receiver further comprises. 3. The register according to claim 1 or 2, further comprising: register means (PRa) for storing a plurality of phase position signals; First selector means (52) for periodically selecting each one of said phase position signals in response to a shift command signal; A pseudo-random number (PN) generator 41 for outputting an orthogonal PN sequence in accordance with the selected phase position signal; Multiplying the in-phase and nodular spread pilot signal by the chip rate with the PN sequence of the PN generator 41 to output the in-phase and nodular despread pilot signal, and integrating the in-phase and nodular despread pilot signal in a predetermined section to output a correlation value. Correlator means 40, 42, 43; A plurality of accumulator means A1-AN; Periodically selecting one of the accumulator means in response to the shift command signal to apply a correlation value to the selected accumulator means, so that the phase position signal is periodically selected and applied to the PN sequence generator while Second selector means (44) for causing the accumulator to output the sum of correlation values output by the accumulator; And generating the shift command signal at a predetermined rate, selecting the total sum of the largest correlation values from the total sum of all the accumulator means, selecting the phase position signal corresponding to the selected sum, and selecting the selected phase position signal. Generating a corresponding orthogonal despreading sequence and including control means 45 connected to the accumulator means (A1-AN) to apply the orthogonal despreading sequence to the correlator means (31-32, 35). A direct sequence spread spectrum receiver further comprising a tracking circuit. 4. The method of claim 3, wherein the plurality of different pairs of phase position signals are stored, and the plurality of different pairs of phases when the accumulator means all output the sum of virtual group correlation values for a set of phase position signals currently stored in the register means. Further comprising means (51) for loading each one of a position signal into said register means (RPa). 4. The direct sequence spread spectrum receiver of claim 3, wherein the predetermined rate at which the shift command signal is generated is higher than a rate at which Rayleigh fading occurs. 6. The direct sequence spread spectrum receiver of claim 5, wherein the predetermined rate corresponds to a period not exceeding [pi] / 2 radian rotation of the in-phase and spherical pilot signals. A plurality of demodulators 21, 22, 23; And an adder 24 connected to the demodulator output, wherein each demodulator multiplies the in-phase and quadrature spread data signal and the in-phase and quadrature spread pilot signal by the quadrature spreading sequence at a chip rate; Correlator means (31-32, 35) for outputting in-phase and quadrature despread data signals and in-phase and nodular despread pilot signals; Data integrators 33i and 33q for integrating in-phase and spherical despreading data signals at a symbol rate to output in-phase and spherical data symbols; Pilot integrator means 36i and 36q for integrating in-phase and spherical despread pilot signals at the symbol rate to output in-phase and in-plane pilot symbols; First and second moving average means 34i and 34q for successively summing a predetermined number of in-phase and spherical pilot symbols to output first and second moving average values, respectively; First and second multiplier means (38i, 38q) for multiplying in-phase and spherical data symbols of the data integrator means with the first and second moving average values, respectively; And means (39) for summing output signals of the first and second multiplier means to output a sum signal and to supply the sum signal to the adder (24). 8. The method of claim 7, further comprising: a first delaying the in-phase data symbols of the data integrator by an amount corresponding to half of the predetermined number of in-phase pilot symbols and applying the delayed symbols to the first multiplier means 38i. Delay means 37i; And second delay means 37q for delaying the spherical data symbols of the data accumulator by an amount corresponding to half of the predetermined number of spherical pilot symbols and applying the delayed symbols to the first multiplier means 38q. The direct sequence spread spectrum receiver further comprises. 9. The apparatus of claim 7 or 8, further comprising: register means (PRa) for storing a plurality of phase position signals; First selector means (52) for periodically selecting each one of said phase position signals in response to a shift command signal; A pseudo-random number (PN) generator 41 for outputting an orthogonal PN sequence in accordance with the selected phase position signal; Multiplying the in-phase and nodular spread pilot signal by the chip rate with the PN sequence of the PN generator 41 to output the in-phase and nodular despread pilot signal, and integrating the in-phase and nodular despread pilot signal in a predetermined section to output a correlation value. Correlator means 40, 42, 43; A plurality of accumulator means A1-AN; Periodically selecting one of the accumulator means in response to the shift command signal and applying a correlation value to the selected accumulator means, so that the correlator means is periodically selected and applied to the PN sequence generator. Second selector means (44) for causing the accumulator to output the sum of the correlation values output by the accumulator; And generating the shift command signal to a predetermined example, selecting a total of the largest correlation value from the total of the accumulator means celestial bodies, selecting the phase position signal corresponding to the selected total, and selecting the selected phase position signal. A synchronization means for generating a corresponding orthogonal despreading sequence and connected to said accumulator means (A1-AN) to apply said plurality of orthogonal spreading sequences to each of said demodulators (21,22,23). A direct sequence spread spectrum receiver further comprising an acquisition tracking circuit. 8. The plurality of different pairs of phase position signals according to claim 7, wherein a plurality of different pairs of phase position signals are stored, and when all the accumulator means output the sum of the correlation values for a set of phase position signals currently stored in the register means. And a means (51) for loading each one of a position signal into said register means (RPa). 8. The direct sequence spread spectrum receiver of claim 7, wherein the predetermined rate at which the shift command signal is generated is higher than the rate at which Rayleigh fading occurs. 12. The direct sequence spread spectrum receiver of claim 11, wherein the predetermined rate corresponds to a section not exceeding [pi] / 2 radians rotation of the in-phase and quadrature alert signals.