KR0141285B1 - Direct digital frequency synthesizer - Google Patents

Abstract

The synthesized frequency of a direct digital frequency synthesizer (DDS) fabricated by conventional CMOS device technology is inadequate for high frequency synthesizers of 50 MHz or more due to the low output frequency corresponding to one-quarter of the maximum operating clock frequency.

In order to improve the low frequency output, which is a disadvantage of the prior art, a parallel accumulator includes a phase accumulator and a noise molding machine, so that the final output is four or more synthesized output frequencies than the output frequency of one DDS. It can be configured to obtain a small size and low power when manufactured by the conventional low power CMOS device technology.

Description

Direct digital frequency synthesizer

1 is a block diagram of a conventional direct digital frequency synthesizer.

2 is a block diagram of a single direct digital frequency synthesizer according to the first embodiment of the present invention.

3 is a block diagram of a noise shaper according to the present invention.

4 is a block diagram of a phase adder of a pipeline structure according to the present invention.

5 is a block diagram of a direct digital frequency synthesizer having a parallel structure according to a second embodiment of the present invention.

6 is a block diagram of a 4: 1 mux according to a second embodiment of the present invention.

7 is a waveform diagram of a clock and a selection control signal applied to a 4: 1 mux according to a second embodiment of the present invention.

8 is a view for explaining a method for synthesizing a parallel output by a multiplexing method according to the present invention.

9 is an output waveform diagram of an output terminal and a final terminal of sinerom 1 obtained by simulating a digital frequency synthesizer according to the present invention.

* Explanation of symbols for main parts of the drawings

201, 501: Pre-Slew Latches

202: frequency register 203: phase adder

204: phase register 205: noise molding machine

206, 511-514: De-Skew Latch

207, 515-518: Sign ROM (ROM)

208 digital-to-analog converter 209 low-pass filter

502: frequency adjustment word generator 503 to 506: phase accumulator

507 ~ 510: Adder 519: mux

The present invention relates to a direct digital frequency synthesizer (Direct Digital Frequency Synthesizer), in particular, to improve the low output frequency of the direct digital frequency synthesizer made of a conventional low power CMOS device is configured to obtain a high output frequency of high-speed operation Relates directly to a digital frequency synthesizer.

The direct digital frequency synthesizer is a digital signal generator that outputs a frequency corresponding to the binary data word value when a frequency adjusted binary data word is input to the frequency input register.

1 is a block diagram of a conventional direct digital frequency synthesizer.

When a binary data value is input to a phase accumulator 102 based on a numerical oscillator (NCO), it is added according to the clock frequency, and the output value of the phase accumulator is fed back and added back to the original value. And counting the phase value of the output signal, inputting the generated address bit into the sine ROM 104, and outputting a series of data values representing a sinusoidal waveform. When this output passes through a digital analog converter (D / A Converter) 105, a quantized quantized waveform is obtained.

In order to obtain a sine wave at the final output stage, a low pass filter 106 that removes high frequency components has to be passed again. On the other hand, the output frequency, F0, obtained directly from the digital frequency synthesizer can be calculated from the relationship of F0 = K × FCLK / 2N, and the maximum synthesized frequency is only about 1/4 of the clock frequency used.

In the above relation, K denotes a frequency adjustment word, N denotes the number of bits of the phase accumulator, and FCLK denotes a clock frequency.

Therefore, in order to obtain a high synthesized frequency output, the circuit configuration method must be changed to increase the clock frequency, which is an operating frequency, or to increase the phase addition speed and the output efficiency.

Only the upper bits of the output of the phase accumulator in the conventional direct digital frequency synthesizer are used as the address bits of the sine lookup table. This results in phase truncation and limited sinerom size, that is, limited sampling ( Amplitude Truncation noise due to Sampling data is generated.

In addition, discrete harmonic components and white noise were generated due to sampling in Sinerom 2, (4), resulting in intermodulation components.

In order to eliminate this phenomenon, the conventional apparatus uses all of the outputs of the phase accumulator as the address bits of the sinerom and output noise by an amplitude quantization method of reducing the phase truncation by increasing the rom of the sinerom. Although improved, a large amount of output storage (ROM) data, which is exponentially weighted by the square of the address bits, was required, resulting in a large chip size of the frequency synthesizer.

In addition, white noise due to intrinsic phase truncation and amplitude quantization generated even when all output bits of the phase accumulator are used as address bits of a sine lookup table to generate high stability and high resolution sine wave. ) And spurious noise cannot be removed, resulting in a poor frequency synthesis function.

In addition, since a synthesized frequency of only 1/4 of a clock frequency can be obtained, it is not suitable for a high output frequency synthesizer of 20 MHz or more in a conventional circuit configuration using low power CMOS technology.

Therefore, the present invention improves the above-described problems, it is possible to synthesize a high frequency (50MHz or more), improve the frequency resolution and stability of the phase and frequency, by reducing the device chip size of the frequency synthesizer, The objective is to provide an improved digital frequency synthesizer suitable for the frequency synthesizer of today's mobile communication devices.

In order to achieve the object as described above, the present invention is characterized in that it is configured by connecting a phase accumulator in parallel to the conventional direct digital frequency synthesizer.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2 is a block diagram of a direct digital frequency synthesizer according to an embodiment of the present invention.

As shown in FIG. 2, a noise corrector in the form of another type of pipeline structure NCO type phase accumulator is inserted between the pipeline structure NCO type phase accumulator and sinomrom. This is different from a direct digital frequency synthesizer.

The lower bit of the output of the phase accumulator is reduced, and then the lower bit passes the filtered output to the noise corrector to use the output bit as the address bit of the sine ROM, thereby storing the stored sampling in the sine ROM. White noise and spurious appearing in the output spectrum generated by phase truncation in a conventional digital signal generator that uses an oversampling method that reduces the amount of data and lengthens the tooling interval of sampling data. High speed processing is possible while minimizing spurious noise.

3 is a block diagram of a noise shaper used in a direct digital frequency synthesizer according to the present invention, and shows a structure in which a plurality of NCO type phase accumulators of a pipeline structure are connected.

4 is a structural diagram of a phase adder used in the present invention, showing a pipeline structure.

5 is a block diagram of a direct digital frequency synthesizer according to a second embodiment of the present invention.

Frequency adjusting word generator 502 generates FCWD0, FCWD1, FCWD2, FCWD3 and 4 * FCW, respectively, which are synchronized to clock 4 (corresponding to 4 times the period of clock 1) to add the intermediate frequency of the digital frequency synthesizer. It is used as control input of and phase adder.

Here, FCWD0, FCWD1, FCWD2, FCWD3 and 4 * FCW are frequency adjustment words, meaning that the clocks are delayed by 0 clock (corresponding to the period of clock 4), 1 clock, 2 clocks, 3 clocks, and 4 clocks.

Therefore, the output of each of the sineroms of the new digital frequency synthesizers connected in parallel in four stages can be configured to be delayed by one, two, three, and four cycles based on the clock 4, which is again 4: 1 Mux Multiplex from

6 is a block diagram of a 4: 1 mux according to a second embodiment of the present invention.

Multiplexing using clock and select signals produces a single output with four times the combined output efficiency.

7 is a waveform diagram of a clock and a selection signal in the mux, and FIG. 8 is a waveform diagram of a final output terminal in the mux.

8 is a waveform diagram of simulation results of a direct digital frequency synthesizer according to a second embodiment of the present invention.

In relation to the eighth degree, it can be seen that the period of the output result of the mux is four times faster.

First, when each binary data value is input, the frequency adjustment word generator 502 is reached through a pre-skew latch, and a frequency adjustment word of 4 clock delayed 4 FCW is generated to form a 4-stage parallel structure. The NCO type phase accumulators 503 to 506 of the connected pipeline structure are respectively delivered.

In the phase accumulator, the input data is added according to the clock frequency, and the added output value is fed back to the original value, counts the phase value of the output signal, and then sends m outputs to the noise shaper.

In addition to the number of bits required by the noise modifier, the lower bits are fed back to the input of the noise modifier and counted again.In the adder inside the noise modifier, a carry bit is generated to be input to the sinroms 515 to 518. Correct the adder output of the noise shaper.

That is, the adder in the noise shaper inputs as many high-bit output values as required by the sine ROM into the sine ROM, and the remaining low-bit output values are input again to the noise shaper serving as a filtering function to feed back the output values.

In the sine ROM, a series of waveform information data bits determined by sampling the number of input bits is output to the 4: 1 mux 519.

The above functional operation occurs simultaneously in parallel phase adders configured in parallel, and the phase delay value is controlled by the FCWD0, FCWD1, FCWD2 and FCWD3 signals generated in the frequency adjustment word, respectively.

In the MUX, as shown in FIG. 5, four sine-ROM outputs are delayed by one clock and arrive in parallel. The outputs are reconfigured and output as a series of single waveform information data bits with a clock cycle reduced to 1/4. .

This output bit passes through the digital-to-analog converter and the lowpass filter to produce a sinusoidal output.

On the other hand, the first embodiment or the second embodiment of the present invention described above is configured by inserting only one stage of a noise corrector in the form of an NCO type phase accumulator in a pipeline structure, but when the same type of noise corrector is configured in multiple stages, Improved frequency characteristics can be obtained.

The effects of the present invention configured as described above are as follows.

First, it has a high processing speed in terms of operating speed.

Second, by using the pipelined NCO type phase accumulator, the accumulation speed is greatly improved regardless of the clock speed, and thus a synthesis frequency several times higher than that of a conventional direct digital frequency synthesizer can be obtained.

Third, in case of direct circuit with low-power CMOS technology, chip size of existing CMOS digital devices can be reduced not only in terms of power consumption but also in chip area, enabling miniaturization and low power.

Fourth, since it has a fast switching speed and high-resolution frequency characteristics of about nanoseconds, it can be used alone in the frequency synthesizer of the system.

Fifth, it can be utilized in a hybrid frequency synthesizer using the advantages of a conventional direct digital frequency synthesizer and the advantages of a phase-locked loop frequency synthesizer having low noise and high stability broadband frequency characteristics.

Claims (7)

An input for receiving a frequency adjustment input; A pre-skew latch connected to the input terminal and storing a frequency adjustment input in response to a system clock; A pipeline structure NCO type phase adder connected to one input unit and counting a phase value of an output signal because a frequency adjustment input input through the preskew latch is added in response to a system clock; and A phase accumulator comprising a phase register coupled to an input of an output of the phase adder, outputting a predetermined upper byte and outputting other lower bits to another input of the phase adder; An noise molding machine connected to an input of an output of the phase accumulator, outputting predetermined upper bits, and remaining lower bits fed back to the input unit to perform a filtering function; An input unit connected to an output of the noise molding machine and configured to store an output of the noise molding machine for synchronizing with a plurality of full adders constituting the noise molding machine (De-Skew Latch); An input connected to an output of the deskew latch and configured to output a series of waveform information data bits determined by sampling the number of bits inputted through the deskew latch; An input unit connected to an output of the sine ROM and converting the waveform information data bits outputted from the sine ROM into an analog signal; And a low pass filter connected to an output of the digital / analog converter, the low pass filter outputting a sine wave by receiving an analog signal output from the digital / analog converter and removing a high frequency wave. The direct digital frequency synthesizer of claim 1, wherein the noise shaper is formed by connecting a plurality of phase accumulators comprising a phase adder and a phase register in series. 3. The direct digital frequency synthesizer of claim 1 or 2, wherein the phase adder is a pipeline structure. An input for receiving a frequency adjustment input; A pre-skew latch connected to the input terminal for storing a frequency adjustment input in response to a system clock; An input is connected to an output of the preskew latch to receive the frequency adjustment input, and a system clock of 0 clock delayed FCDW0, 1 clock delayed FCDW1, 2 clock delayed FCDW2, 3 clock delayed FCDW3, 4 clock delayed 4 * FCW A frequency tuned word generator for generating a frequency tuned word; A phase accumulator and a noise molding machine with N connected in parallel; An output unit of the noise molding machine and one input unit are connected, and one output unit of the frequency adjusting word generator is connected to another input unit, and an output unit of the noise molding machine and the frequency adjusting words FCWDi (i = 1 to 4) are added. 1 to 4 adders; An input unit connected to an output unit of the adder and configured to store outputs of the adder for synchronizing with a plurality of full adders constituting the noise molding machine (De-Skew Latch); An input unit connected to an output of the deskew latch and outputting a series of waveform information data bits determined by sampling the number of bits inputted through the deskew latch; A mux for receiving and outputting the output from the first to fourth sine-roms as a single signal; A digital-to-analog converter connected to an output of the mux and converting the waveform information data bits output from the mux into an analog signal; And a low pass filter connected to an output part of the digital / analog converter and outputting a sine wave by removing an input munde high frequency from the analog signal output from the digital / analog converter. 5. The pipelined NCO type phase adder of claim 4, wherein the phase accumulator counts the phase value of the output signal since 4 * FCW from the frequency adjusted word generator is added in response to the system clock. And an input coupled to an output of the phase register, the predetermined upper bit being output and the other lower bits being composed of a phase register for feeding back to another input of the phase adder. 5. The direct digital according to claim 4, wherein the noise molding machine has an input connected to an output of the phase accumulator, outputs a predetermined upper bit, and the remaining lower bits are fed back to the input to perform a filtering function. Frequency synthesizer. 5. The direct digital frequency synthesizer according to claim 4, wherein the noise shaping machine is composed of two or more stages.