KR0141241B1 - Noise limitation circuit - Google Patents

Abstract

The present invention relates to a noise limiting circuit for limiting the magnitude of noise.

The present invention provides a switching unit for outputting a synchronous level signal when the pseudo composite synchronization signal output from the ghost elimination circuit is high, and outputting a signal selected by the selection signal output from the ghost elimination circuit, and the output of the switching unit is The controller is configured to limit the output level of the switching unit to a reference level when the external level is greater than a predetermined reference level. When the level of the input noise signal is higher than the predetermined reference level, the AGC circuit of the tuner is controlled to reference the level of the noise signal. By limiting the level, the pseudo composite sync signal can be stabilized to stably display the noise signal, and the OSD signal can be reliably recognized, thereby solving the problem of OSD characters not flowing or appearing on the noise screen.

Description

Noise limiting circuit

1 is a simple block diagram of a conventional ghost eliminator,

2 is a detailed block diagram of the ghost removal circuit of FIG.

3 is an operational waveform diagram of each part of FIGS. 1 and 2 during noise input;

4 is a simple block diagram of a ghost eliminator including a noise limiting circuit according to the present invention;

5 is a detailed circuit diagram of the noise control unit of FIG. 4;

6 is an operation waveform diagram of each part of FIGS. 4 and 5 at the time of noise input.

* Explanation of symbols for main parts of the drawings

20: Tuner and intermediate frequency converter 40: Ghost elimination circuit

50: clamp part 60: switching part

70: control unit 80: adder

41: analog / digital transducer 42: ghost removal unit

43: memory 44: synchronous and field ID separator

45: window pulse generator 46: microprocessor

47: Romans 48: Digital / Analog Converter

Q1, Q2: Transistor R1, R2, R3: Resistance

C1: Capacitor Vref: Reference Level Adjuster

MC: Mycom

The present invention relates to a noise limiting circuit. More particularly, the present invention relates to a video signal in a video medium such as a television by controlling a tuner's automatic gain control circuit according to a preset reference level. The present invention relates to a noise limiting circuit for stably displaying a noise screen by limiting a noise level of a channel having no channel.

In a channel without a video signal, a noise screen is displayed. In this case, since a synchronization signal does not exist in the noise signal, a television in a noise state can be displayed relatively stably by using a fly-back pulse.

However, when the ghost eliminator is an adapter type such as a VTR, a flyback pulse does not exist, so it is used to generate pseudo sync, or a device such as a VTR does not output a noise screen if a synchronous signal is not detected. It also displays a blue screen.

At this time, in order to eliminate the so-called ghost phenomenon caused by radio wave reflection of a mountain area or a building group, a broadcasting station transmits a constant reference signal so that the receiving side can know the characteristics of the transmitting channel. Eliminate ghosts by identifying the ghost characteristics and filtering by their inverse characteristics. In this case, the reference signal transmitted from the broadcasting station is referred to as a ghost canceling reference signal (hereinafter referred to as a GCR).

1 is a block diagram of a conventional ghost canceller, which includes a tuner and an intermediate frequency converter 20 for processing a signal received by an antenna ANT, a ghost cancellation circuit 40 for removing a ghost signal, and a ghost removed signal. By the clamp unit 50 for clamping the original signal that is not ghost removed to a predetermined level, the switching unit 60 for selecting and outputting one of the ghost removed signal and the original signal that is not ghost removed, by the horizontal / vertical synchronous signal On Screen Display (hereinafter referred to as OSD) A microcomputer (MC) for outputting a signal, the video signal output from the switching unit 60 and the OSD signal output from the micom (MC) is superimposed and output It consists of an adder (80).

FIG. 2 is a detailed block diagram of the ghost removal circuit 40. The output terminal of the analog / digital converter 41 for converting the video signal output from the tuner and the intermediate frequency converter 20 of FIG. 1 into a digital signal is shown in FIG. A ghost removing unit 42 for removing ghost is connected, and an output terminal of the ghost removing unit 42 is connected to one input terminal of a memory 43 for storing a video signal, and a micro pro is connected to an output terminal of the memory 43. One input terminal of the introduction 46 is connected.

In addition, a window pulse generator 45 is connected to one output terminal of the microprocessor 46. At this time, the memory 43 is composed of a FIFO (First IN First OUT) memory.

On the other hand, in the video signal output from the tuner and the intermediate frequency converter 20 of FIG. 1, the horizontal / vertical sync signal (HD, VD), the field ID (signal distinguishing whether the input video signal is an odd field or an even field) ), Horizontal / vertical synchronous signals HD and VD and field ID signals outputted from the synchronous and field ID separator 44 are output to the synchronous and field ID separator 44 for outputting the sync detection signal HDet. And a window pulse generator 45 for outputting a window pulse corresponding to a line on which the GCR signal is loaded by line information output from the microprocessor 46.

The other end of the memory 43 is connected to an output terminal of the window pulse generator 45.

On the other hand, the other input terminal of the microprocessor 46 is connected to the output terminal of the GCR ROM 47 in which the reference GCR signal is stored, and the other output terminal of the microprocessor 46 is output from the analog-to-digital converter 41. The other input terminal of the ghost removing unit 42 for removing a ghost signal from the video signal is connected.

In addition, the memory 43 is connected to an output terminal of the ghost remover 42, and a digital / analog converter 48 for converting a signal from which ghost is removed from the ghost remover 42 to an analog signal is connected. .

On the other hand, a pseudo compound synchronization generator 49 is connected to the synchronization and field ID separator 44, and the pseudo compound synchronization generator 49 is horizontal / vertical of the synchronization and field ID separator 44. An AND gate A1 connected to the synchronization signal HD and VD terminals, an AND gate connected to an output terminal of the AND gate A1 and a synchronization signal detection terminal HDet of the synchronization and field ID separation unit 44. It consists of (A2).

At this time, the function of the synchronization and field ID separation unit 44 is a product that is actually implemented, for example, there is a uPC1860 timing IC of NEC of Japan.

The conventional ghost eliminator configured as described above converts the signal received by the antenna ANT into a video signal of the baseband through tuning and VIF module processing by the tuner and the intermediate frequency changer 20 to ghost elimination circuit 40 and clamp. Output to the unit 50.

The ghost removal circuit 40 removes the ghost signal from the input video signal and outputs the ghost signal to the clamp unit 50 and outputs the horizontal / vertical synchronization signals HD and VD to the microcomputer MC. The ghost removal circuit 40 outputs a selection signal cl for selecting the original video signal PG and the ghost removed signal DG to the control terminal of the switching unit 60. At this time, the selection signal cl is configured to be selected by the user.

The ghost elimination circuit 40 will be described in more detail with reference to FIG. 2.

The video signal of the baseband output from the tuner and the intermediate frequency converter 20 is output to the analog-to-digital converter 41 to be converted into a digital signal, and at the same time, to the sync and field ID separator 44 to be horizontal. Detect and detect the vertical synchronization signals HD, VD, the field ID signal, and the synchronization detection signal HDet. In this case, the synchronization detection signal HDet is a signal indicating whether or not there is a synchronization component in the input video signal, that is, a signal for determining the presence or absence of a video signal.

In this case, since the horizontal / vertical synchronization signal is required for the OSD operation, the horizontal synchronization signal HD and the vertical synchronization signal VD are output to the microcomputer MC of FIG. .

In addition, the synchronization and field ID separation unit 44 outputs the horizontal / vertical synchronization signals HD and VD and the field ID signal to the window pulse generator 45, and the microprocessor 46 generates the window pulse generator. Line information is output to (45). The window pulse generator 45 generates a window pulse corresponding to a line carrying a GCR signal based on the horizontal / vertical synchronization signals HD and VD, the field ID signal, and the line information, and outputs the generated window pulse to the FIFO memory 43. do.

On the other hand, the output of the analog-to-digital converter 41 is output to the ghost remover 42, the ghost remover 42 outputs the original video signal from which the ghost signal is not removed to the FIFO memory 43 Save it.

The microprocessor 46 generates only the GCR video signal from the FIFO memory 43 by the window pulse output from the window pulse generator 45 and outputs the GCR video signal from the GCR ROM 47. The characteristics of the channel are grasped in comparison with the reference GCR signal, and the reverse characteristic thereof is output as a control signal (filter coefficient) to the ghost removal unit 42.

Since the ghost removing unit 42 is usually a combination of a plurality of FIR filters and a plurality of IIR filters, the video signal output from the analog / digital converter 41 by the control signal output from the microprocessor 46. The ghost is removed from and output to the clamp unit 50 of FIG. 1 through the digital / analog converter 48.

The microprocessor 46 outputs, to the control terminal of the switching unit 60, an original video signal i1 that is not ghost removed and a selection signal c1 for selecting the ghost removed signal i2. . In this case, the selection signal c1 may be configured to be selected by the user. In other words, it is sufficient to end the signal selected by the user and the selection signal of the microprocessor 46.

The feedback of the output of the ghost removing unit 42 back to the FIFO memory 43 is obtained in order to obtain a channel characteristic, to verify whether or not ghost removal is properly performed, and to prepare for an initial signal processing or an abnormal occurrence. Is present, the microprocessor 46 controls the switching unit 60 to select the original signal i1 that is not ghost removed.

On the other hand, the horizontal and vertical synchronization signals HD and VD of the synchronization and field ID separation unit 44 are logically multiplied by the AND gate A1 of the pseudo compound synchronization generation unit 49, and the AND gate A1. ) Output is logically multiplied by the sync detection signal HDet to generate a pseudo compound sync signal.

At this time, the synchronization detection signal HDet outputs a low value when there is a synchronization component in the input video signal and a high level when there is no synchronization component. Accordingly, the pseudo compound synchronizing generator 49 outputs a low signal if there is a synchronization component in the input video signal, and if there is no synchronization component, the pseudo compound synchronizing signal c2, such as an actual horizontal / vertical synchronization signal, is switched. Output to (60).

On the other hand, the ghost removed signal i2 and the original ghost signal not ghost removed from the ghost removal circuit 40 are output to the clamp unit 50 to a predetermined level as shown in FIG. After being clamped, it is output to the switching unit 60. The switching unit 60 selects the ghost removed signal i2 clamped to a predetermined level and the original signal ghost not removed by the selection signal c1 input to the control terminal and outputs the added signal to the adder 80. In addition, when the adder 80 adds the OSD signal output from the microcomputer MC and outputs it on the screen, a channel number or a volume indicator is displayed on the OSD.

However, in the above-described circuit of FIG. 3A, the OSD signal may not be shaken or the OSD characters may be hidden due to the noise, depending on the noise state, and affect the synchronization. That is, if the noise level is very large, it is not locked by the pseudo compound synchronization signal, and thus, the OSD screen flows or the OSD expression is unstable as shown in FIG.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to control the AGC circuit of the tuner according to a preset reference level to adaptively limit an excessively loud noise level to stabilize the pseudo compound sync signal, thereby making the noise signal The present invention provides a noise limiting circuit that can stably display and to recognize OSD signals reliably and to solve problems in channels without video signals.

Features of the noise limiting circuit according to the present invention for achieving this object are a tuner and an intermediate frequency converter for converting the signal received by the antenna into a video signal of the baseband, and if there is a synchronous component in the video signal, the ghost And a ghost elimination circuit for generating and outputting a pseudo compound synchronizing signal when there is no synchronous component, a clamp unit for clamping and outputting the output of the tuner and the intermediate frequency converter and the ghost eliminating circuit to a predetermined level, and a horizontal / vertical synchronizer. A ghost eliminator comprising a microcomputer for outputting an on-screen display signal locked to a signal, an adder for adding the output of the microcomputer and the output of the switching unit, the switching unit for selectively outputting the output of the clamp unit or the other input, The output of the switching means is greater than the predetermined reference level And a control unit for limiting the output level of the switching means to the reference level.

Hereinafter, a preferred embodiment of the noise limiting circuit according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a ghost eliminator including a noise limiting circuit according to the present invention, the configuration and operation of the tuner and the intermediate frequency converter 20, the ghost elimination circuit 40, the microcomputer (MC), the clamp unit 50 is conventional Are the same as in FIG. 1 and FIG.

Only the difference between FIG. 1 and FIG. 1 is different from that of the switching unit 60 that receives the original ghost signal ie not removed and the ghost removal signal i 2, which is clamped and output from the clamp unit 50 at a predetermined level. The input terminal is configured to provide a synchronization level signal i3.

In addition, the control terminal of the switching unit 60 has a selection signal c1 output from the microprocessor 46 of the ghost elimination circuit 40 and a pseudo compound synchronization signal output from the pseudo compound synchronization generating unit 49. c2) is configured to be provided independently.

In addition, a control unit 70 for limiting noise is connected to an output terminal of the switching unit 60, and one side of the control unit 70 includes a tuner and an intermediate frequency converter 20. An AGC circuit (not shown) is connected and an adder 80 is connected to the other output terminal.

The OSD signal terminal of the microcomputer MC is connected to the other input terminal of the adder 80.

FIG. 5 is a detailed circuit diagram of the controller 70, which is composed of first and second transistors Q1 and Q2. An input terminal and an output terminal are commonly connected to the emitter terminal of the first transistor Q1. At this time, the input terminal is coupled to the output terminal of the switching unit 60, the output terminal is coupled to the adder 80. A reference level adjuster Vref for adjusting a reference level is connected to a base end of the first transistor Q1, and a second transistor Q2 is connected to a collector end through a capacitor C1 and resistors R1 and R2. ) Base end is connected.

The emitter terminal of the second transistor Q2 is grounded, and the collector terminal is connected to the AGC circuit of the tuner and the intermediate frequency converter 20 through the resistor R3.

In this case, the reference level regulator Vref may be configured as a variable resistor.

In the present invention configured as described above, the horizontal and vertical synchronization signals HD and VD of the synchronization and field ID separation unit 44 of the ghost cancellation circuit 40 of FIG. 2 are the AND gate A1 of the similar complex synchronization generation unit 49. ), And the output of the AND gate A1 is logically multiplied by the synchronization detection signal HDet to generate a pseudo compound synchronization signal c2.

At this time, the synchronization detection signal HDet outputs a low value when there is a synchronization component in the input video signal, and a high level when there is no synchronization component. Accordingly, the similar composite synchronization generating unit 49 outputs a low signal when there is a synchronous component in the input video signal, and when the synchronous component is absent, that is, when there is no video signal, the horizontal / vertical synchronous signals HD and VD are combined. The pseudo composite synchronization signal c2 is output to the control terminal of the switching unit 60.

In addition, the microprocessor 46 of the ghost elimination circuit 40 selects a selection signal c1 for selecting an original signal i1 from which ghost is not removed and a signal i2 from which ghost is removed. Output to the other control stage.

Then, the clamp unit 50 clamps a noise signal as shown in FIG. 6 (a) to a predetermined level as shown in FIG. ) And the ghost-free signal i2 are respectively output to the input terminal of the switching unit 60.

The synchronization level signal i3 input from the outside is also output to the other input terminal of the switching unit 60.

At this time, the signals (i1, i2, i3) input to the input terminal of the switching unit 60, the signals (c1, c2) input to the control terminal of the switching unit 60 and the output of the switching unit 60 and The relationship between is as follows.

In this case, when the video signal is normally input, since the pseudo composite synchronizing signal c2 is always low, the output of the switching unit 60 is the selection signal c1 output from the microprocessor 46 of the ghost elimination circuit 40. Depends). If the selection signal c1 is low, the original signal i1 that is not ghost removed is selected and output, and if it is high, the signal i2 from which ghost is removed is selected and output.

On the other hand, when no image signal is input and only noise is input, since the GCR signal will not be present in the noise, the selection signal c1 becomes low and noise input as the original signal i1 that is not ghost removed. Is selected and output.

In addition, when there is no video signal and only noise is input, the pseudo complex synchronizing unit 49 of the noise removing circuit 40 generates a pseudo compound synchronizing signal c2 and outputs it to the switching unit 60. If (c2) is high, the synchronization level signal i3 is selected and outputted. If low, the noise signal input to i1 is selected and outputted as described above, and the output of the switching unit 60 is shown in FIG. ), The synchronization signal is loaded on the noise signal.

In addition, the controller 70 presets the noise output from the switching unit 60 so as not to affect the normal state (including the state considering the margin in the presence of ghost) as shown in FIG. If the reference level or more, the tuner and the AGC circuit of the intermediate frequency converter 20 is operated.

That is, when the input signal level of the first transistor Q1, which is the output of the switching unit 60, is higher than the externally set reference level Vref, the first transistor Q1 is turned on. When the first transistor Q1 is turned on, the capacitor C1 is charged. When the capacitor is completely charged, the second transistor Q2 is also turned on, and the AGC circuit is provided inside the tuner and the intermediate frequency converter 20. By operating the control unit, the level of the noise signal output from the tuner and the intermediate frequency converter 20 is limited to the reference signal level Vref as shown in FIG.

At this time, the resistors R1 and R2 and the capacitor C1 are values related to the time constant of the AGC circuit.

Therefore, the noise signal limited by the reference level by the AGC circuit of the tuner and the intermediate frequency converter 20 is added to the OSD signal output from the microcomputer MC and the adder 80 and then output to the screen.

At this time, since the noise level is limited, the pseudo compound sync signal is stabilized, so that the noise signal can be stably displayed. As shown in FIG. This is solved.

Meanwhile, when the input signal level of the first transistor Q1 is lower than the reference signal level Vref, the first transistor Q1 is turned off, and when the first transistor Q1 is turned off, the second transistor Q2 is turned off. ) Is also turned off and the signal input to the first transistor Q1 is output to the adder 80 as it is, and is added to the OSD signal output from the microcomputer MC in the adder 80 and output to the screen.

As described above, according to the noise limiting circuit according to the present invention, when the level of the input noise signal is higher than the preset reference level, the AGC circuit of the tuner is controlled to adaptively limit the noise level of excessive magnitude so that the similar complex synchronization signal is suppressed. By stabilizing, the noise signal can be stably displayed, and the OSD signal can be reliably recognized, thereby eliminating the problem of OSD characters flowing or not being displayed on the noise screen.

Claims (3)

In a circuit that superimposes an OSD on a noise signal output from a channel without a video signal, a circuit for limiting the level of the noise signal, comprising: a tuner and an intermediate apparatus for converting and outputting a video signal received from an antenna into a video signal of a baseband A frequency converter; If the video signal outputted from the tuner and the intermediate frequency converter includes a synchronous component, a signal i2 is removed from the ghost. If there is no synchronous component, a pseudo-synchronized synchronous signal c2 is generated and output, and the ghost is not removed. a ghost removal circuit for outputting a selection signal c1 for selecting (i2) or a signal i2 from which ghost is removed; A clamp unit configured to input a signal output from the tuner and the intermediate frequency converter and a signal output from the ghost elimination circuit to clamp a predetermined level; According to the selection signal c1 and the pseudo-synchronized synchronous signal c2 output from the ghost elimination circuit, when the pseudo-synchronized synchronous signal c2 is input, the ghost is not removed by the selection signal c1 ( i1) or a signal from which ghost is removed is selected, and if the pseudo-synchronized synchronous signal c2 is not input, the ghost is not removed by the synchronization level signal i3 and the selection signal c1. switching means for selecting i1 or a signal i2 from which ghost is removed; And a noise control unit for limiting the noise level by controlling the tuner and the intermediate frequency conversion unit when the signal output from the switching means is greater than a reference level. The noise limiting circuit of claim 1, wherein the noise controller controls an automatic gain control circuit of the tuner and the intermediate frequency converter. The method of claim 1, wherein the noise control unit generates a control signal for outputting a control signal by comparing a reference level setting unit, a sensing unit sensing an output level of the switching means, and an output of the reference level setting unit and an output of the sensing unit. Negative noise limiting circuit.