KR0141198B1 - Data recovering apparatus by automatic voltage control - Google Patents

Abstract

The present invention relates to a data recovery apparatus by automatic potential control, and recovers a clock signal directly from a signal restored first in a digital form, and then returns the recovered clock signal back to the automatic potential control part to reproduce a signal having a large amplitude change. An amplitude control unit for adjusting the gain of the reproduced signal reproduced from the recording medium to output the in-phase and in-phase signals so that the optimum data can be restored by reproducing the signal more accurately, and the in-phase signal applied from the amplitude control unit. A potential detection unit that detects only a potential of a predetermined level or more from the signal and detects only a potential of a predetermined level or more from an antiphase signal applied from the amplitude control unit, and a signal of a predetermined level or more detected by the potential detection unit in the form of original digital data. A clock-asynchronous data detector for restoring the clock-asynchronous data The clock reproducing unit receives digital data from the other detection unit and detects the reproduction clock signal, and the digital data is received from the clock-asynchronous data detection unit, and the reproduction clock is applied from the clock reproducing unit to synchronize the digital data with the reproduction clock. A clock-synchronous data detector for outputting was configured. Therefore, it is possible to detect the correct data by setting the proper potential corresponding to the amplitude of the input signal through the automatic potential controller, and to extract the regeneration clock from the recovered data to determine the automatic potential control amount by using this to secure a stable clock. This can improve the bit error rate for data recovery. The present invention can be used in any device for reproducing digital data recorded on a recording medium.

Description

Data restoration device by automatic potential control

1 is a schematic block diagram of a conventional data recovery apparatus;

(A)-(g) of FIG. 2 is a waveform diagram of each part shown in FIG.

3 is a diagram showing a relationship between a composite signal and a pilot signal;

4 is a schematic block diagram of an apparatus for restoring data by automatic potential control according to the present invention;

5 is a detailed block diagram of the potential detection unit shown in FIG. 4;

6 is a detailed circuit diagram of the automatic potential controller shown in FIG. 5;

7 is a detailed circuit diagram of the clock-asynchronous data detector shown in FIG. 4;

8 is a waveform diagram of each part shown in FIG. 4;

FIG. 9 is a waveform diagram of each part shown in FIG.

* Explanation of symbols for main parts of the drawings

10: Playback head 11: video tape

12: Reproduction amplifier 13: Reproduction equalizer

14: amplitude control unit 15: non-inverting amplitude controller

16: Inverted amplitude controller 17: Voltage comparison unit

18,19,28,29: comparator 20: data restoration

21: data clock synchronization unit 22: filter unit

23: clock regeneration unit 24: potential detection unit

25: clock-synchronous data detector 26: clock-synchronous data detector

27: automatic potential control unit 30: first delay

31: second delay 32, 33: endgate

34: switch 35: integral part

35a: half-wave rectifier circuit 35b: integrating circuit

36,37: amplifier 38: gain control

Vcc: Constant voltage Q1: Switching transistor

R1 to R4: Resistance VR: Variable resistance

C1: Condenser

The present invention relates to an apparatus for restoring data by automatic potential control, and more particularly, in an apparatus for converting an analog signal into a digital signal for recording / reproducing or transmitting / receiving, a clock directly from a first restored signal in a digital form. The present invention relates to a data restoring apparatus by automatic potential control that recovers optimal data by returning a restored clock signal back to the automatic potential control unit to more accurately reproduce a reproduction signal having a large amplitude change. .

In general, a data recovery device refers to a device that allows playback data to be restored to be identical to the original data when the data recorded on the recording medium is reproduced in a digital form. Referring to FIG. The description is as follows.

FIG. 1 is a schematic block diagram of a conventional data restoration apparatus. The reproduction head 10 reproduces digital information recorded on the video tape 11 and outputs it to the reproduction amplifier 12. At this time, the digital information reproduced from the video tape 11 includes a composite signal (video signal + audio signal) and a pilot signal.

The reproduction amplifier section 11 amplifies the digital information reproduced by the reproduction head 10 to a size suitable for signal processing. That is, when reproducing the information recorded on the video tape 11, the size of the reproduced signal is smaller than the size of the original signal, which is not suitable for signal processing. Can play in the state.

The reproduction equalizer 13 receives the reproduction signal output from the reproduction amplifier 12 to compensate for the frequency characteristic of the reproduction signal and then outputs it to the amplitude control unit 14.

The amplitude control unit 14 is composed of a non-inverting amplitude controller 15 and an inverted amplitude controller 16. The amplitude control unit 17 receives the reproduction signal from the reproduction equalizer 13, adjusts the amplitude in the in-phase and inverse phase, and then compares the voltage in the comparison unit 17. )

The voltage comparator 17 is composed of two comparators 18 and 19. The voltage comparator 17 converts only a signal of a portion of the reproduced signal amplitude controlled by the amplitude control unit 14 that is greater than or equal to the reference voltage (± ref) into a square wave. Output to the restoration unit 20.

The data recovery unit 20 restores the digital data by combining the square waves applied by the voltage comparing unit 17 and outputs the digital data to the data-clock synchronization unit 21.

On the other hand, the reproduction signal (composite signal + pilot signal) output from the reproduction amplifier 12 is applied to the filter unit 22 together with the reproduction equalizer 13, which filters the data on the recording medium. At this time, the low frequency pilot signal recorded with the digital data is filtered and then output to the clock reproducing section 23.

The clock reproducing unit 23 receives a low frequency pilot signal from the filter unit 22 and restores the clock signal to the data-clock synchronizing unit 21.

The data-clock synchronizing unit 21 receives data from the data restoring unit 20 and simultaneously receives the clock signal reproduced through the clock reproducing unit 23 to detect and output data synchronized with the clock signal.

A data recovery apparatus having the configuration as described above will be described in more detail with reference to FIG.

The digital signal (see (a) of FIG. 2) recorded on a recording medium such as a video tape 10 or the like is reproduced by the reproduction head 10, amplified by the reproduction amplifier 12, and the reproduction equalizer 13 Receives the reproduction signal (composite signal + pilot signal) amplified by the reproduction amplifier 12 receives the frequency and outputs.

The reproduction signal whose frequency is compensated by the reproduction equalizer 13 is applied to the non-inverted amplitude controller 15 and the inverted amplitude controller 16 configured in the amplitude control unit 14, respectively, in phase through the non-inverted amplitude controller 15. Amplitude controlled in the reverse phase through the inverted amplitude controller 16, and each of the reproduced signals adjusted in the amplitude is non-inverted (+) of the comparators 18 and 19 configured in the voltage comparator 17. Is applied to each.

On the other hand, a reference voltage is applied to the inverting terminals (-) of the comparators 18 and 19, wherein the reference voltage applied to each of the comparators 18 and 19 is a predetermined fixed voltage value. Are + Vref and -Vref respectively (see (b) and (c) in FIG. 2).

The comparator 18 compares the in-phase reproduction signal output from the amplitude control unit 14 with the reference voltage (+ Vref) and outputs the result. The comparator 19 outputs the reverse phase output from the amplitude control unit 14. After comparing the reproduction signal with the reference voltage (-Vref) and outputting the result, at this time, the result of comparing the value output from the non-inverting amplitude controller 15 with the reference voltage (+ Vref) through the comparator 18 is As shown in (d) of FIG. 2, the result of comparing the reference voltage (-Vref) with the value output from the inverted amplitude controller 16 through the comparator 19 is shown in (e) of FIG. same.

The outputs of the comparators 18, 19 as shown in (d) and (e) of FIG. 2 are applied to the data recovery unit 20, respectively, and the data recovery unit 20 is provided with the respective comparators 18. , Combined with the output waveforms output in (19), are restored to digital data as shown in FIG. 2 (f), and then output to the data-clock synchronizer 21. FIG.

On the other hand, the reproduction signal (composite signal + pilot signal) output from the reproduction amplifier unit 12 is simultaneously applied to the filter unit 22, and the filter unit 22 filters only the pilot signal among the applied reproduction signals and filters the filtered pilot signal. Is output to the clock reproducing unit 23.

The clock reproducing unit 23 is applied from the filter unit 22 to reproduce the clock signal using the pilot signal, and then outputs the data signal to the data-clock synchronizing unit 21. The data-clock synchronizing unit 21 is a data reconstructing unit. By synchronizing and outputting the reproduction signal applied from the 20 and the clock signal applied from the clock reproducing unit 23, the user can recognize the information recorded on the video tape 11.

In this case, however, as shown in (f) of FIG. 2, a difference occurs between the delay times T1 to T4 according to the respective data output from the data recovery unit 20, so that the clock regeneration unit 23 In the case of outputting in synchronization with the clock signal reproduced in Fig. 2), as shown in Fig. 2G, the reproduced data is different from the original data recorded on the video tape 11. In other words, when one period of T1 to T4 is selected and the group delay is selected as much as the selected period, any one selected period can be reproduced in the same way as the one data, but the remaining period does not coincide with the one data. Is lost.

In other words, since the reference voltage for comparison in the voltage comparison section is always fixed constantly, the delay periods are different from each other for the reproduction signals reproduced at various amplitudes, resulting in a bit error rate (BER). There was a problem caused.

In addition, when a pilot signal for clock reproduction is loaded on the data, the clock is affected by the second and third harmonics (see FIG. 3) generated by the pilot signal itself. There was a problem that the signal could not be reproduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to calculate the potential level of a reproduction signal and to set an appropriate potential so that the reproduction data identical to the one data can be obtained by easily corresponding to the data having various widths. In addition, the present invention provides an apparatus for restoring a data by automatic potential control by extracting a reproduction clock directly from the reproduction data and using the same to determine the automatic potential control amount.

A feature of the data recovery apparatus by the automatic potential control according to the present invention for achieving the above object is a data recovery apparatus for restoring original digital data by reproducing data recorded in a digital form on a recording medium; An amplitude control unit for adjusting the gain of the reproduction signal reproduced from the recording medium and outputting in-phase and anti-phase signals; A potential detector for detecting a peak point of a predetermined level or more from the in-phase signal applied from the amplitude control unit, and detecting a peak point of a predetermined level or more from an antiphase signal applied from the amplitude control unit; A clock-asynchronous data detection unit for combining the signals of a predetermined level or more detected by the potential detection unit to restore the original digital data form; A clock reproducing unit receiving digital data from the clock-asynchronous data detecting unit and detecting a reproducing clock signal; And a clock-synchronous data detection unit for receiving digital data from the clock-asynchronous data detection unit, receiving a reproduction clock from the clock reproducing unit, and outputting the digital data in synchronization with the reproduction clock.

In the present invention, it is preferable that the amplitude control unit is configured with a differential amplifier so as to adjust the output gain of each in-phase and anti-phase signal.

In addition, the potential detection unit is an automatic potential control unit for setting the reference potential in accordance with the amplitude of the in-phase and inverse abnormal signal applied from the wing full width control unit, the reference potential set by the automatic potential control unit is received through the amplitude control unit A comparator configured to receive in-phase and anti-phase signals and output only a region of the applied in-phase and anti-phase signals that are greater than or equal to the reference potential as a square wave; A delay unit, a first end gate for performing an AND operation on the output of the comparator corresponding to the in-phase signal and the output of the first delay unit, and a square wave corresponding to a delayed square wave corresponding to the antiphase signal output from the comparator for a predetermined time. Performing a logical AND operation on the output of the comparator and the output of the second To consist of two AND gates are preferred.

In addition, the automatic potential control unit includes an integrator for evaluating the amplitude of the in-phase and anti-phase signals applied from the amplitude control unit, a switch for switching between the amplitude control unit and the integrator by a clock signal applied from the clock reproducing unit; It is preferable that the gain adjuster is applied to the reference potential of the comparator after adjusting the signal applied from the integrator to a proper gain.

The integrator is preferably composed of a half-wave rectifier circuit for passing only signals of ground level or higher among the reproduction signals, and an integrating circuit for integrating the signal applied from the half-wave rectifier circuit.

In addition, the clock-asynchronous data detector includes an inverter for inverting the signals applied from the first and second gates, and a de-flip flop for performing logical operation on the inverted signal through the inverter to restore the original digital data. It is desirable to.

In addition, the clock-asynchronous data detector may be configured to perform an OR operation on the OR signal applied from the first and second AND gates, and the OR signal received through the OR gate to the clock signal input terminal. It is preferable to construct a J-Flip-flop that logically performs a signal applied from the AND gate and restores the original digital data.

The clock reproducing unit reproduces a clock using a digital signal applied from the clock-asynchronous data detection unit, and then applies the clock signal to a switch of the automatic potential control unit to adjust a switching time, and convert the clock signal into the clock signal. It is preferable to output to the synchronous data detection section to supply a clock signal source synchronized with the data.

In addition, the clock-synchronous data detector may be configured as a flip-flop to synchronize the digital data applied from the clock-asynchronous data detector and the clock signal applied from the clock reproducing unit.

EMBODIMENT OF THE INVENTION Hereinafter, one preferred embodiment of the data restoration apparatus by automatic potential control which concerns on this invention is demonstrated in detail with reference to an accompanying drawing.

4 is a schematic block diagram of an apparatus for restoring data by automatic potential control according to the present invention. In FIG. 4, the same reference numerals as those in FIG. 1 denote the same parts, and thus, description thereof will be omitted. Only parts are described.

Referring to FIG. 4, the full width control unit 14 receives the reproduction signal from the reproduction equalizer 13 and adjusts the amplitude in the in-phase and inverse phase as described in FIG. 1, and then outputs it to the potential detection unit 24. do.

The potential detection unit 24 receives the in-phase and inverse phase signals applied from the amplitude control unit 14 to detect only the potential above the ground level, and then outputs the same to the clock-asynchronous data detection unit 24.

The clock-asynchronous data detector 25 restores the digital data by combining a signal of a ground level or more applied from the potential detector 24, and simultaneously outputs the same to the clock regenerator 23 and the clock-synchronous data detector 26. do.

The clock regeneration unit 23 restores the regeneration clock by using the data detected by the clock-asynchronous data detection unit 25 as a signal source, and then outputs the regeneration clock to the potential detection unit 24 and the clock-synchronous data detection unit 26. do.

The clock-synchronous data detector 26 outputs the same playback data as the one data by synchronizing the playback clock applied from the clock playback section 23 with the playback data applied from the clock-synchronization data detection section 25. FIG.

Meanwhile, referring to FIG. 5, the potential detection unit 24 will be described in more detail. The automatic potential control unit 27 calculates the level of the in-phase and anti-phase signals applied from the amplitude control unit 14 to reference voltage. The reference potential is applied to the inverting ends (-) of the comparators 28 and 29.

The comparators 28 and 29 compare the in-phase and in-phase signals applied from the amplitude control unit 14 with the reference potentials applied from the automatic potential control unit 27, and compare the corresponding square waves with the first and second delayers. Output to (30) and (31).

The first and second delayers 30 and 31 delay the square waves applied from the two comparators 28 and 29 for a predetermined time, and then, respectively, to the two end gates 32 and 33, respectively. Output

The two Nadgates 32 and 33 are provided with a square wave applied from two comparators 28 and 29, and a square wave delayed by the first and second delayers 30 and 31 for a predetermined time. After the logic bear operation, it outputs to the clock-asynchronous data detection unit 25.

Meanwhile, referring to FIG. 6, the automatic potential control unit 27 will be described in more detail. The switch 34 is switched according to the clock signal applied from the clock regeneration unit 23 so that the reproduction data applied from the amplitude control unit 14 is integrator. The control is applied to (35).

The integrator 35 also includes a half-wave rectifier circuit 35a consisting of two amplifiers 36, 37, two diodes D1, and D2, a plurality of resistors R1 to R4, and a capacitor C1. ) And an integrated circuit 35b composed of a transistor Q1, detecting only a signal having a potential above ground level among the signals applied through the half-wave rectifying circuit 35a, and then detecting this signal with an appropriate potential in the integrated circuit 35b. Integrate by and output this result to the gain adjuster 38.

The gain adjuster 38 is composed of a variable resistor VR. The gain adjuster 38 receives the output of the integrator 35 and adjusts the output to two comparators 38 and 39.

The data recovery apparatus by the automatic potential control having the configuration as described above will be described in more detail by way of example.

Reference (a) of FIG. 8 of the digital signal recorded on the video tape 11 is reproduced by the reproduction head 10, and then applied to the reproduction amplifier 12, and the reproduction amplifier 12 receives the applied reproduction signal ( The composite signal + pilot signal) is amplified and output to the reproduction equalizer 13.

That is, when the digital data recorded on the video tape 11 is reproduced, the waveform is converted into a waveform close to the analog form in which the amplitude is shifted up or down in the transition point of each digital data due to the characteristics of the recording medium.

The reproduction equalizer 13 compensates each frequency characteristic of the reproduction signal amplified by the reproduction amplifier 12 and outputs it to the amplitude control unit 14. In this case, even if the frequency characteristics are compensated by the reproduction equalizer 13, the magnitude of the peak value of each frequency is different from each other.

The amplitude control unit 14 (e.g., an automatic amplifier) receives the reproduction signal from the reproduction equalizer 13 and adjusts the amplitude in phase and in phase so that the reference phase (b) of FIG. (c), and outputs to the comparators 28 and 29 and the automatic potential control unit 27 in the potential detection unit 24.

On the other hand, the switching signal is applied to the integrating unit 35 by the switch 34 is applied to the automatic potential control unit 27, the switch 34 is applied to the clock signal applied from the clock regeneration unit 23 Is controlled by

References (a) and (b) of the reproduction signal 9 applied to the integrator 35 after being switched by the switch 34 are half-waves composed of amplifiers 36, 37, diodes D1, and D2. After only the ground level signal of the reproduction signal is passed through the rectifying circuit 35a (see (c) and (d) of FIG. 9), the transistor Q1 and the plurality of resistors R1 to R4 and the capacitor C1 are passed. After integration through the integrating circuit 35b, it is applied to the reference gain regulator 38 in FIG.

The gain adjuster 38 (in one example, the variable resistor) adjusts the gain of the reproduction signal applied from the integrator 35 and applies this result to the inverting stages (-) of the comparators 28 and 29. That is, the gain regulator 38 controls the overall DC voltage level of the integrator output (see (e) in FIG. 9).

The comparators 36 and 37 compare the differential amplification outputs of the in-phase and inverse phases applied by the amplitude control unit 14 with the reference potentials applied from the automatic potential control unit 27, and then only the sections above the reference potentials are compared. Output as a square wave (see (d) and (e) in FIG. 8), and after a certain time delay through two delayers (30) and (31) (see (f) and (g) in FIG. 8) The AND gates 32 and 33 of the logical AND operation of the aforementioned square wave output (see (d) and (e) of FIG. 8) and the delayed square wave (see (f) and (g) of FIG. 8) are performed. (See Figures 8 (h) and (i).)

At this time, the rising edge portion ↑ of the waveforms shown in (h) and (i) of FIG. 8 becomes the peak point of the reproduction waveform, that is, the inversion time of the recording data.

Therefore, the waveform as shown in (h) and (i) of FIG. 8, which is the final output of the peak detector 24, is applied to the clock-asynchronous data detector 25, and the clock-asynchronous data detector 25 is applied. Square wave (refer to (h) and (i) of FIG. 8), and then convert it into an appropriate logic signal and restore the original digital data (see (j) of FIG. 8). At this time, it is preferable that the clock-asynchronous data detector 25 is configured as a flip flop as shown in FIGS. 7A and 7B.

The digital data reconstructed through the above process is output to the clock-asynchronous data detector 25, and the clock regenerator 23 makes the clock-asynchronous data detector 25 generate the reproduced clock signal using the output waveform. The reproduction clock signal is then output to the autopotential control unit 27 and the clock-asynchronous data detection unit 26, respectively.

Here, since the clock regeneration unit 23 can be realized by a known phase locked loop or the like, detailed description thereof will be omitted.

The clock-synchronous data detector 26 receives the clock signal applied from the clock reproducer 23 and the digital data applied from the clock-synchronous data detector 25 to output data synchronized with the reproduced clock. At this time, the clock-synchronous data detector 26 may be configured as a D flip-flop or the like.

Therefore, as detailed in Figs. 8A to 8J, the digital data detected from the video tape 11 (see Fig. 8A) and the digital signal signaled by the potential detection unit 24 are processed. It can be seen that the data (see (j) in FIG. 8) becomes identical to each other so that the original digital data is correctly restored.

As described above, according to the apparatus for restoring data by the automatic potential control according to the present invention, it is possible to detect the correct data by setting the appropriate potential corresponding to the amplitude of the input signal through the automatic potential control unit, and to reproduce the clock from the restored data. By extracting and using this to determine the autopotential control amount, it is possible to secure a stable clock, thereby improving the bit error rate for data recovery.

Claims (9)

A data recovery apparatus for reproducing original digital data by reproducing data recorded in a digital form on a recording medium; An amplitude control unit for adjusting the gain of the reproduction signal reproduced from the recording medium and outputting in-phase and anti-phase signals; A potential detector for detecting a peak point of a predetermined level or more from the in-phase signal applied from the amplitude control unit, and detecting a peak point of a predetermined level or more from an antiphase signal applied from the amplitude control unit; A clock-asynchronous data detection unit for combining the signals of a predetermined level or more detected by the potential detection unit to restore the original digital data form; A clock reproducing unit receiving digital data from the clock-asynchronous data detecting unit and detecting a reproducing clock signal; And a clock-synchronous data detection unit configured to receive digital data from the clock-asynchronous data detection unit, receive a reproduction clock from the clock reproducing unit, and output the digital data in synchronization with the reproduction clock. The data recovery apparatus according to claim 1, wherein the amplitude control unit is configured as a differential amplifier to adjust the output gain of each in-phase and in-phase signal. 2. The apparatus of claim 1, wherein the potential detection unit comprises: an automatic potential control unit for setting a reference potential in accordance with amplitudes of in-phase and inverse phase signals applied from the amplitude control unit; A comparator configured to receive a reference potential set by the automatic potential control unit, and to receive an in-phase and an in-phase signal input through the amplitude control unit and output only a region of the applied in-phase and in-phase signal that is equal to or greater than the reference potential as a square wave; ; A first delay unit for delaying a square wave corresponding to the in-phase signal output from the comparator for a predetermined time; A first AND gate performing an AND operation on the output of the comparator corresponding to the in-phase signal and the output of the first delay unit; A second delay unit for delaying a square wave corresponding to an anti-phase signal output from the comparator for a predetermined time; And a second end gate configured to perform an AND operation on the output of the comparator corresponding to the anti-phase signal and the output of the second delay unit. 4. The apparatus of claim 3, wherein the automatic potential control unit comprises: an integrator for evaluating amplitudes of in-phase and inverse phase signals applied from the amplitude control unit; A switch for switching between the amplitude control unit and the integrator by a clock signal applied from the clock reproducing unit; And a gain adjuster configured to apply a reference potential of the comparator after adjusting the signal applied from the integrator to an appropriate gain. 5. The data recovery apparatus according to claim 4, wherein the integrator comprises a half-wave rectifier circuit for passing only signals of a ground level or higher among reproduction signals, and an integrator circuit for integrating a signal applied from the half-wave rectifier circuit. 2. The apparatus of claim 1, wherein the clock-asynchronous data detection unit comprises: an inverter for inverting signals applied from the first and first and gates; And a de-flip flop for performing logical operation on the inverted signal through the inverter and restoring the original digital data. 2. The apparatus of claim 1, wherein the clock-asynchronous data detector comprises: an orifice for calculating a logic applied to the signals applied from the first and second end gates; The auto-potential is composed of a J-flip-flop that receives the OR operation through the OR gate to the clock signal input terminal, and performs a logical operation on the signals applied from the first and second end gates to restore the original digital data. Data restoration device by control. The clock reproducing unit of claim 1, wherein the clock reproducing unit reproduces a clock using a digital signal applied from the clock-asynchronous data detecting unit, and then applies the clock signal to a switch of the automatic potential control unit to adjust a switching time. And a clock signal source synchronized with the data by outputting the clock signal to the clock-synchronous data detector. The method of claim 1, wherein the clock-synchronous data detection unit comprises a flip-flop, and the digital data applied from the clock-asynchronous data detection unit and the clock signal applied from the clock reproducing unit are synchronized. Data recovery apparatus by potential control.