KR0140751B1 - Method of forming trench on semiconductor device - Google Patents

Abstract

The present invention relates to a trench isolation layer of a semiconductor device and a method of forming the same. A trench is formed in a predetermined width at an interface between an active area and a field area of a device to fill an insulating film and a conductive material in the trench, and to maintain a constant potential in the conductive material. The present invention relates to a method for preventing the loss of an insulating film embedded in a trench during the insulating film etching process after the formation of the trench element molecules, and maintaining a constant potential of the lower device isolation region in the trench.

Description

Trench isolation film and method of forming the same

1 is a MOSFET structure formed according to a conventional method, in which a gate electrode and a source / drain electrode are formed, and a source electrode is connected to a substrate.

2 is a cross-sectional view of a MOSFET formed according to a conventional method, taken along the line X-X 'of FIG.

3 is a layout showing a structure in which a gate electrode and a source / drain electrode are formed and a source electrode is connected to an engine as a MOSFET structure formed according to the present invention.

4A to 4F are cross-sectional views of a MOSFET formed by the present invention, taken along the line X-X 'of FIG.

* Names of symbols on the main parts of the drawings

A: device isolation mask B: gate electrode mask

C: active area (inside of device isolation mask A)

D: Field area (outside of device isolation mask A)

E: contact mask F: source electrode connecting line mask

G: drain electrode connecting line mask 1: semiconductor substrate

2 device isolation insulating film 3 gate oxide film

4: conductive material for gate electrode 4 ': gate electrode

5A: source electrode 5B: drain electrode

5C: substrate electrode 6: interlayer insulating film

7: contact photoresist pattern 8A: source electrode connection line

8B: drain electrode connection line 10: trench

11 insulating film 12 conductive material

13: Burj Bek

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trench isolation layer and a method of forming the semiconductor device. In particular, a trench for isolation of a device is formed at an interface between an active region and a field region of a device. It relates to a device isolation film forming method of applying a constant potential to the conductive material.

In general, the conventional LOCOS (Local Oxidation of Silicon) method that separates the active devices with the increase in the degree of integration of the semiconductor device has the disadvantages such as insufficient active area due to excessive Buzzbee and insufficient depth of the device isolation film. This increases the level of integration.

In order to solve the drawbacks of the LOCOS method, a trench type device isolation structure has been developed, but in the conventional trench type device isolation structure, the device isolation region formed in the trench is easily planarized in a device isolation region having a narrow width. On the other hand, in the device isolation region having a wide width, it was difficult to planarize.

1 is a layout of a MOSFET formed according to a conventional method, showing a structure in which a gate electrode and a source / drain electrode are formed, and a source electrode is connected to a substrate.

FIG. 2 is a cross-sectional view of a MOSFET formed according to a conventional method, and is a cross-sectional view taken along the line X-X 'of FIG. 1, which is a layout diagram. The device isolation insulating film 2, the gate electrode 4, Source / drain electrodes 5A and 5B are sequentially formed, and an interlayer insulating film 6 is entirely stacked thereon, then a contact is formed by a photoresist pattern (not shown) and an etching process, followed by source electrode connection lines 8A. And cross-sectional view where the drain electrode connecting line 8B is formed.

The conventional LOCOS method is an obstacle to an increase in the density due to problems such as insufficient active area and insufficient depth of the device isolation layer due to excessive buzz beak 13.

Therefore, the present invention can easily planarize the device isolation insulating film formed inside the trench by forming the trench isolation layer in a predetermined width at the interface between the active region and the field region of the device, and fill the trench with an insulating film and a conductive material. It is an object of the present invention to provide a trench isolation layer of a semiconductor device and a method for forming the same, which can improve device characteristics by maintaining a constant potential in a conductive material embedded in the trench.

In order to achieve the above object, a trench device isolation film of a semiconductor device according to the present invention,

In the trench isolation film of a semiconductor device,

Device isolation trenches are provided at the interface between the active and field regions of the device,

An insulating film is provided on the trench surface,

A conductive material having a predetermined potential is embedded in the trench.

In addition, in order to achieve the above object, a trench device isolation film forming method of a semiconductor device according to the present invention,

In the trench device isolation film forming method of a semiconductor device,

Forming a trench in an interface between an active region and a field region in the upper part of the semiconductor organ,

Forming a thickness of an insulating film on the trench surface;

Embedding a conductive material on the insulating film;

Etching the conductive material and leaving the conductive material only inside the trench;

Forming a gate electrode, a source / drain electrode and a substrate electrode on the semiconductor substrate;

Laminating and patterning an interlayer insulating film over the entire surface;

And forming a connection line on the source electrode, the drain electrode, the substrate electrode, and the conductive material in the trench.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a layout diagram showing a structure in which a gate electrode and a source / drain electrode are formed as a structure of a MOSFET formed by the present invention, and a source electrode is connected to an engine.

4A to 4F are cross-sectional views of the MOSFET formed by the present invention, and are cross-sectional views taken along the line X-X 'of FIG. 3 which is a layout diagram.

Referring to FIG. 4A, a trench 10 having a predetermined width is formed on an interface between the active region C and the field region D on the semiconductor substrate 1.

Referring to FIG. 4B, the trench 10 is filled with the insulating film 11 and the sufficiently thick conductive material 12 having a predetermined thickness as a whole. In this case, the conductive material 12 may use a silicon film.

Referring to FIG. 4C, the conductive material 12 is etched back so that the conductive material 12 remains only inside the trench 10.

Referring to FIG. 4D, the gate oxide film 3 and the conductive material 4 for the gate electrode are stacked.

Referring to FIG. 4E, after forming the gate electrode 4 ', the source / drain electrodes 5A and 5B, the substrate electrode 5C, and stacking the interlayer insulating film 6, the contact photoresist film pattern 7 is formed. do.

In this case, the contact photoresist pattern 7 formed on the source electrode simultaneously exposes the source electrode 5A, the conductive material 12 and the substrate electrode 5C in the trench 10, and may be separated separately according to the purpose.

Referring to FIG. 4F, the interlayer insulating layer 6 is etched by an etching process using the contact photoresist pattern 7 to etch the source electrode 5A, the drain electrode 5B, the substrate electrode 5C, and the conductive material in the trench. A contact hole is formed in (12), and a source electrode connecting line (8A) is formed in the conductive material (12) and the substrate electrode (5C) in the source electrode (5A) and the trench (10), and in the drain electrode (5B). The drain electrode connection line 8B is formed. In this case, when the potentials of the source electrode 5A and the semiconductor substrate 1 are used differently, the conductive material 12 in the trench 10 may be connected to the substrate electrode 5C, and the trench 10 may be separately. It is also possible to apply a constant potential to the conductive material 12 in the interior.

On the other hand, when the semiconductor substrate 1 is p-type, a conductive material embedded in the trench 10 has a lower potential than that of the semiconductor substrate, and when the semiconductor substrate 1 is n-type, it is embedded in the trench. The conductive material is applied with a higher potential than that of the semiconductor substrate.

The conductive material 12 embedded in the trench 10 is connected to the substrate electrode 5C or the source electrode 5A of the MOSFET structure and applied with a constant potential, or the substrate electrode 5C and the source of the MOSFET structure are sourced. Connected to the electrode 5A, a constant potential is applied.

In addition, an isolation trench 10 may be formed under the gate electrode of the field region.

As described above, the trench isolation layer of the semiconductor device and the method of forming the semiconductor device according to the present invention provide a device isolation insulating film formed in the trench by forming the trench isolation layer at a predetermined width between the active region and the field region of the device. After the trench isolation is formed by embedding the insulating film and the conductive material in the trench for device isolation and applying a constant potential to the conductive material embedded in the trench, the insulating film is etched in the process. The loss of the insulating layer embedded in the trench can be prevented and the potential of the device isolation region under the trench can be kept constant.

Claims (8)

In the trench isolation layer of a semiconductor device, a trench for device isolation is provided at an interface between an active area and a field area of the device, an insulating film is provided on the trench surface, and a conductive material having a constant potential is embedded in the trench. A trench device isolation film of a semiconductor device. The semiconductor device isolation film of claim 1, wherein in the case of the P-type semiconductor substrate, a conductive material embedded in the trench has a lower potential than that of the semiconductor substrate. The trench device isolation film of claim 1, wherein when the semiconductor substrate is N-type, the conductive material embedded in the trench has a higher potential than that of the semiconductor substrate. The trench isolation layer of claim 1, wherein the conductive material is connected to a source electrode and provided with a predetermined potential. The trench device isolation film of claim 1, wherein the conductive material is connected to the substrate electrode and has a predetermined potential. The trench device isolation film of claim 1, wherein the conductive material is connected to a source electrode and a substrate electrode to have a predetermined potential. The trench isolation layer of claim 1, wherein the trench is disposed under a gate electrode positioned in a field region. A method of forming a trench isolation layer for a semiconductor device, the method comprising: forming a trench in an interface between an active region and a field region on an upper surface of a semiconductor substrate, forming a predetermined thickness of an insulating layer on the trench surface, and filling a conductive material on the insulating layer. Forming a gate electrode, a source / drain electrode, and a substrate electrode on the semiconductor substrate; and stacking and patterning an interlayer insulating film on the entire surface of the semiconductor substrate. And forming a connection line in the source electrode, the drain electrode, the substrate electrode, and the conductive material in the trench.