KR0137987B1 - Bit line floating preventing cirucit - Google Patents

Abstract

The present invention has a sense amplifier interposed therebetween to prevent bit line floating conditions caused by sharing one sense amplifier during bit line detection and amplification operation of DRAM (DRAM) devices. Bitline (BL, / BL) and bitline threshold power (PB) that floats the transistor turned on in an operation in which the bitline isolation transistor between the sense amplifier and the memory cell array is turned off when the opposite memory cell array is activated. It relates to a bit line floating prevention circuit implemented between Vblp).

Description

Bitline Floating Prevention Circuit

1 is a conventional cell array block and related circuit diagram,

2 is a cell array block and related circuit diagram of the present invention.

* Explanation of symbols for main parts of the drawings

11: first memory cell array block 12, 15: sense amplifier

13: Bit line precharge circuit 14: Second memory cell array block

16: bit line separation means

The present invention has a sense amplifier interposed therebetween to prevent bit line floating conditions caused by sharing one sense amplifier during bit line detection and amplification operation of DRAM (DRAM) devices. Bitline (BL, / BL) and bitline precharge power (pB) that floats the transistor turned on in an operation in which the bitline isolation transistor between the sense amplifier and the memory cell array is turned off when the opposite memory cell array is activated. It relates to a bit line floating prevention circuit implemented between Vblp).

In general, the process of reading the cell data is as follows.

In a cell array block of a DRAM device, when a specific word line is selected by an address signal transmitted from the outside of the device, data from all cells connected to the word line is transferred to the bit lines BLS and / BLS connected to the respective sense amplifiers. The data transmitted to the bit line (BLS, / BLS) connected to the sense amplifier is sensed and amplified by the sense amplifier and then output to the outside of the device via the data line (DB, / DB) and the data output buffer.

FIG. 1 schematically illustrates a circuit related to a DRAM cell operation of the prior art for explaining an operation of a DRAM. The first memory cell array block 11 in which cells composed of one NMOS transistor and a capacitor are gathered is shown. And pass transistors Q1 and Q2 for transferring data of the bit lines BL and BL of the cell array to bit lines BLS and BLS connected to the sense amplifiers, and bit lines BLS and connected to the sense amplifiers. Bit line sense amplifier 12 for sensing and amplifying data of a cell transmitted to the BLS) and bit lines BL and / BL for transmitting data of a DRAM cell to a precharge voltage Vblp during a standby operation. And a bit line precharge circuit 13 for holding.

Referring to the operation, the sense amplifier 12 operates even when the memory array to which the word line WL1 is input operates and also when the memory array to which the word line WL2 is input operates.

When the memory array to which the word line WL2 is input is operated, the sense amplifiers 12 and 15 operate.

If the word line WL1 is enabled, the control signal bi1 of the pass transistors Q1 and Q2 is kept high to turn on the pass transistors Q1 and Q2 and the word line WL1. The sense amplifier 12 which senses and amplifies data of the bit lines BL and / BL connected to the input memory cell array is driven.

At this time, the control signal bi2 of the pass transistors Q3 and Q4 goes low to turn off the pass transistors Q3 and Q4, thereby transferring the data of the bit lines BL and / BL to the sense amplifier 12. Do not enter.

In this operation, the bit lines BL and / BL are in a floating state.

If the RAS signal is active for a long time or the potential change of the substrate is severe, the data of the cell connected to the bit lines BL and / BL may be destroyed, and the refresh time ( refresh time) may be reduced.

Accordingly, an object of the present invention is to solve a problem of the related art by implementing a circuit for preventing a bit line from floating when sensing and amplifying data of a cell.

In order to achieve the above object, in the present invention, a transistor that is turned on in an operation in which a bit line isolation transistor between the sense amplifier and the memory cell array is turned off when the opposite memory cell array is activated with the sense amplifier interposed therebetween. Is implemented between the floating bit line (BL, / BL) and the bit line precharge potential (Vblp).

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

2 shows a cell array block and associated circuit of the present invention, comprising: first and second memory cell array blocks (11, 14) comprising a plurality of memory cell arrays; Pass transistors Q9 and Q10 which are transmission means for transferring data of the cell to a bit line connected to a sense amplifier; A bit line sense amplifier 12 for sensing and amplifying data of a cell transferred to the bit line; A bit line precharge circuit (13) for maintaining the bit line at a precharge voltage in a standby operation; When the first memory cell array block 11 operates, the precharge potential is supplied to the bit line of the second memory cell array block 14, and when the second memory cell array block 14 operates, the data of the cell is sensed. It consists of a bit line separating means 16 for transferring to the bit line connected to the amplifier 12.

The bit line separation means 16 is connected between a bit line BLS connected to the sense amplifier 12 and a bit line BL connected to a cell array, and an NMOS having a bit line separation signal bi2 connected to a gate thereof. An NMOS transistor Q2 connected between a transistor Q11 and a bit line / BLS connected to the sense amplifier 12 and a bit line / BL connected to a cell array, and having a bit line separation signal bi2 connected to a gate thereof. ); A PMOS transistor Q13 connected between the bit line precharge potential Vblp and the bit line b1 and having a bit line separation signal bi2 connected to a gate thereof; A PMOS transistor Q14 connected between the bit line precharge potential Vblp and a bit line bar blb and having a bit line separation signal bi2 connected to a gate thereof; The PMOS transistor Q15 is connected between the bit line BL and the bit line bar / BL and has a bit line separation signal bi2 connected to a gate.

That is, the PMOS transistors connected between the bit line precharge potential Vblp and the bit lines BL and / BL of the second memory cell array block 14 and whose operation is determined by the bit line separation signal bi2 ( Q13 to Q15) are further configured in the prior art.

In operation, when the first word line WL1 is enabled, data stored in the first memory cell array block 11 connected to the word line is output as a bit line connected to the cell transistor, and thus, between the cell and the bit line. Charge distribution occurs.

At this time, a path that receives data from the bit lines BL and / BL of the first memory cell array block 11 and transmits the data to the bit lines BLS and BLS connected to the sense amplifier 12. Transistors Q9 and Q10 consist of NMOS transistors.

Since the control signal bi1 of the pass transistors Q9 and Q10 is kept high, the pass transistors Q9 and Q10 for driving the sense amplifiers of the cell array block selected by the row address are operated.

Accordingly, the sense amplifier bias potential rto, / s is shifted to the power supply potential Vcc and the ground potential Vss by the operation of the pass transistors Q9 and Q10 as described above, thereby driving the sense amplifier 12. do.

When the PMOS transistors Q13 and Q14 of the bit line separation means 16 are in the precharge state, the bit line separation signal bi2 is made high for the bit line precharge operation, so that the bit line isolation transistors Q11 and Q12 are It is turned on and the PMOS transistors Q13 and Q14 are turned off.

Meanwhile, when the word line WL1 is selected, since the bit line isolation signal bi2 is low, the bit line isolation transistors Q11 and Q12 are turned off, and the PMOS transistors Q13 and Q14 are turned on. do.

On the other hand, when the word line WL2 is selected, since the bit line isolation signal bi2 is high, the bit line isolation transistors Q11 and Q12 are turned on, and the PMOS transistors Q13 and Q14 are turned on. Turn off.

Therefore, when the cell data is sensed and amplified using the bit line floating prevention circuit according to the present invention, the bit line floating phenomenon caused by sharing the sense amplifier can be prevented.

Claims (2)

First and second memory cell array blocks (11, 14) consisting of a plurality of memory cell arrays; Pass transistors Q9 and Q10 which are transmission means for transferring data of the cell to a bit line connected to a sense amplifier; A bit line sense amplifier 12 for sensing and amplifying data of a cell transferred to the bit line; A bit line precharge circuit (13) for maintaining the bit line at a precharge voltage in a standby operation; When the first memory cell array block 11 operates, the precharge potential is supplied to the bit line of the second memory cell array block 14, and when the second memory cell array block 14 operates, the data of the cell is sensed. And a bit line separating means (16) for transferring to a bit line connected to the amplifier (12). The bit line separation unit (16) of claim 1, wherein the bit line separation unit (16) is connected between a bit line (BLS) connected to the sense amplifier (12) and a bit line (BL) connected to a cell array. an NMOS transistor Q11 to which bi2 is connected; An NMOS transistor Q12 connected between a bit line / BLS connected to the sense amplifier 12 and a bit line / BL connected to a cell array, and having a bit line separation signal bi2 connected to a gate thereof; A PMOS transistor Q13 connected between the bit line precharge potential Vblp and the bit line b1 and having a bit line separation signal bi2 connected to a gate thereof; A PMOS transistor Q14 connected between the bit line precharge power Vblp and a bit line bar blb and having a bit line separation signal bi2 connected to a gate thereof; And a PMOS transistor (Q15) connected between the bit line (BL) and the bit line bar (/ BL) and having a bit line separation signal (bi2) connected to a gate.