KR0137982B1 - Input buffer of semiconductor memory - Google Patents

Abstract

The present invention provides a switching point of a signal input device for a change in power supply potential (Vcc) in which noise occurs in a conventional signal input device having an inverted gate structure including a pull-up transistor and a pull-down transistor. The present invention relates to a signal input device implemented by connecting a resistor and a CMOS transistor in series between a pull-up transistor and a power supply potential (Vint) according to a change in power supply potential so that the change of the power supply is minimized.

Description

Signal input buffer of semiconductor memory device

1 is a circuit diagram showing an example of a conventional signal input buffer,

2 is a circuit diagram showing an embodiment of a signal input buffer of the present invention;

3 is a simulation waveform diagram comparing the switching potentials of the conventional and the present invention.

* Explanation of symbols for main parts of the drawings

11: power supply dropping device section 12: signal input buffer section

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal input buffer of a semiconductor device, and more particularly, to a change and minimum switching point of a signal input device with respect to a change in power supply potential (Vcc) in which noise occurs. The present invention relates to a signal input buffer implemented by connecting a resistor and a MOS transistor in series between a pull-up transistor and a power supply potential Vint according to a change in power supply potential.

The signal input buffer is a device that transmits a TTL (Transistor Transistor Logic) level signal input from the outside of the semiconductor device as a Complementary Metal Oxide Semiconductor (CMOS) level signal inside the device. Vin (input high level voltage), which is a signal that is input to the director and shows a high potential, is transferred to the power potential inside the device, and Vil (input low level voltage), a signal that indicates low potential, is input below 0.8V, Will be transferred to the ground potential.

In a typical signal input buffer, since the variation range of the signal input from the outside of the device is small, when noise occurs on the power supply line, the input signal may be mistransmitted into the device, causing a malfunction.

FIG. 1 is a circuit diagram showing an example of a conventional signal input buffer and a peripheral circuit thereof, and is connected between an external power supply voltage Vcc_ext terminal and a ground voltage Vss terminal to drop the external power supply voltage to lower the internal power supply voltage. And a signal input buffer unit 12 connected between the internal power supply voltage Vcc_int terminal and the ground voltage Vss terminal.

The signal input buffer unit 12 is connected between an internal power supply voltage Vcc_int terminal and an output terminal sig_int, and a gate of the pull-up transistor Q5 to which an external input signal IN is applied, and an output terminal sig_int. It is composed of a pull-down transistor Q6 connected between a ground voltage Vss terminal and an external input signal IN applied to a gate.

Looking at the operation, the operation of the signal input buffer unit 12 is the same as the operation of the normal inverting gate.

When the current flowing from the power supply potential to the output terminal sig_int in the operation of the pull-up transistor Q5 using the PMOS transistor is I_pu, the following equation is satisfied in a region where the potential of the output terminal sig_int is not particularly high.

I_pu = Gm × (Vcc-Vin-│Vtpl│) -------------- (1)

{Where Gm is a transconductance constant constant proportional to the width / length of the transistor, Vin is the input potential and Vtp is the threshold voltage of the pull-up transistor.}

If the current flowing from the output sig_int to the ground potential in the operation of the pull-down transistor Q6 using the NMOS transistor is I_pd, the following equation is satisfied in a region where the potential of the output sig_int is not particularly low.

I_pd = Gm × (Vin-Vss-Vtn) ---------------- (2)

{Where Gm is a transconductance constant constant proportional to the width / length of the transistor, Vin is the input potential and Vtp is the threshold voltage of the pull-up transistor.}

Looking at the above equations (1) and (2), the difference between the amount of current flowing through the pull-up transistor Q5 and the amount of current flowing through the pull-down transistor Q6 is caused by the potential of Vin. When the amount of current flowing through Q5 increases, the potential of the output terminal sig_int has a high potential, and when the amount of current flowing through the pull-down transistor Q6 increases, the potential of the output terminal sig_int has a low potential.

In particular, there is a point where the amount of current flowing through the pull-up transistor Q5 and the pull-down transistor Q6 becomes the same for a specific input potential, which is an area where the input potential cannot be determined. This is particularly called a switching point because the state of the potential to be input is determined.

In general, the signal input device does not cause a malfunction even if the change range between the high potential and the low potential of the signal input from the outside of the device is small, but only when the value of the potential is accurately recognized inside the device.

However, as described above, in a conventional signal input device that determines the input potential by comparing the current flowing through the pull-up transistor Q5 and the current flowing through the pull-down transistor Q6, the input potential is constant. Even if the power supply potential is affected, the output potential may be different.

Because the magnitude of the pull-down current flowing through the pull-down transistor Q6 is intrinsic to the power potential, while the pull-up current flowing through the pull-up transistor Q5 increases when the power potential increases. This is because the amount of current increases. That is, when the power supply potential is high, the switching point becomes high. On the contrary, when the power supply potential is lowered, the pullup current is decreased, thereby lowering the switching point.

Therefore, when the power potential is low with respect to the change of the power potential, a margin for noise of the input signal is insufficient when the low potential input signal is input, and when the power potential is high, On the other hand, there is a problem that the margin for the noise of the input signal is insufficient.

Accordingly, an object of the present invention is to provide a signal input buffer of a semiconductor memory device capable of buffering an input signal irrespective of a change in power supply potential.

Another object of the present invention is to provide a signal input buffer of a semiconductor memory device capable of buffering an input signal irrespective of a change in power supply potential while increasing a margin for noise of the input signal.

In order to achieve the above object, the signal input buffer of the semiconductor memory device of the present invention allows the external power potential Vcc_ext to flow through a capacitor to a pull-up transistor of a signal input buffer part for inputting a signal, thereby causing an internal power potential Vcc_int. Is implemented to minimize the change of switching point that changes according to the potential of ground voltage (Vss).

Hereinafter, with reference to the accompanying drawings, the present invention will be described in more detail.

2 is a circuit diagram illustrating an embodiment of a signal input buffer according to the present invention, in which a drain and a source are commonly connected to an external power supply voltage Vcc_ext, and a gate is connected to a node N1, and a PMOS transistor Q9; A resistor R connected between the internal power supply voltage Vcc_int terminal and the node N1, and a pull-up connected between the node N1 and the node N3 and whose gate is connected to the external signal input node N2. a pull-down device connected between a pull-up device Q7 and the node N3 and a ground voltage Vss terminal and whose gate is connected to the external signal input node N2. Q8) is further configured in the prior art.

Here, the gates of the pull-up element Q7 and the pull-down element Q8 are connected to the external signal input node N2 in common.

In addition, the PMOS transistor Q9 has a drain and a source connected to the external power supply voltage Vcc_ext in common, and serves as a capacitor component for voltage dropping the power supply potential.

As the capacitor component, a PMOS transistor having a capacitor structure or an NMOS transistor or capacitor having a capacitor structure is used.

Here, FIG. 3 will be described first in order to add understanding to the operation description of the present invention.

3 is a simulation waveform diagram comparing the switching potentials of the conventional and the present invention, and using the external power supply voltage Vcc_ext, the internal power supply voltage Vcc_int based on the waveform diagram of the noise component represented by the ground voltage Vss and Referring to the waveform diagram of the external power supply voltage Vcc_ext, the waveform of the internal power supply voltage Vcc_int is formed similarly to the waveform of the ground voltage Vss in the noise section, and the waveform of the external power supply voltage Vcc_ext is It can be seen that a waveform opposite to the waveform of the ground voltage Vss is formed.

By using the above principle, in the present invention, the external power supply voltage, which is fluctuated by noise, flows to the pull-up transistor Q7 so that the internal power supply voltage Vcc_int is changed to the ground voltage by the external power supply voltage Vcc_ext. It was stabilized to move according to the potential of Vss).

Referring to the operation, when the external power supply voltage Vcc_ext is increased, a voltage dropped through the PMOS transistor Q9 of the capacitor component flows to the pull-up transistor Q7.

When the external power supply voltage Vcc_ext decreases, the current flowing through the pull-up transistor Q7 discharges through the PMOS transistor Q9 of the capacitor component.

Accordingly, the signal input buffer unit 12 may stably detect the switching potential of the input terminal in.

The MOS transistor Q9 of the capacitor component connected between the external power supply voltage Vcc_ext and the pull-up transistor Q7 serves to stabilize the current flowing through the pull-up transistor Q7.

The MOS transistor Q9 of the capacitor component can be used in place of the capacitor and non-nondiode diode, and its capacity is considered to be 1pf or more.

Instead of the PMOS transistor, the MOS transistor Q9 may use an NMOS transistor having a drain and a source connected in common to a source of the pull-up transistor Q7 and a gate connected to an external power supply voltage Vcc_ext.

In the present invention, the resistor R connected between the internal power supply voltage Vcc_int and the pull-up transistor Q7 to limit the current flowing through the pull-up transistor is preferably 1K ohm or more. Do.

As can be seen from the simulation waveform diagram of FIG. 3, the waveform diagram of (A) shows the switching potential of the conventional signal input device, and it can be seen that the switching potential B according to the present invention is relatively reduced.

As described above, the signal input device of the present invention has a small change in the switching point with respect to the change in the power potential compared to the prior art, so that a large noise margin can be secured despite the change in the power potential, thereby stably detecting the potential of the input terminal. It can work.

Claims (7)

A semiconductor memory device having a voltage dividing means connected between an external power supply voltage terminal and a ground voltage terminal to drop the external power supply voltage to generate a predetermined internal power supply voltage, wherein the semiconductor memory device is connected between the internal power supply voltage terminal and the output terminal and is gated. Is a pull-up transistor controlled by an input potential, a pull-down transistor connected between the output terminal and the ground voltage terminal and whose gate is controlled by an input potential, and between the internal power supply voltage terminal and the pull-up transistor. Current limiting means connected to limit a current flowing through the pull-up transistor and stabilization means connected between the external power supply voltage terminal and the pull-up transistor to stabilize a current flowing through the pull-up transistor. Characterized by a signal input buffer. The signal input buffer according to claim 1, wherein said stabilization means comprises a capacitor. The signal input buffer according to claim 2, wherein the capacitor is 1 pf or more. The signal input buffer according to claim 1, wherein said stabilization means comprises a MOS transistor. The signal input buffer of claim 4, wherein the MOS transistor is a PMOS transistor having a drain and a source connected to an external power supply voltage terminal in common, and a gate connected to a source of the pull-up transistor. The signal input buffer according to claim 1, wherein the stabilization means is composed of a diode. The signal input buffer according to claim 1, wherein said current limiting means is composed of a resistor having a resistance value of 1K ohms or more.