KR0137232B1 - Still digital camera - Google Patents

Abstract

The present invention relates to a still image recording digital camera suitable for an image input means such as a computer, which realizes an image pickup device which obtains a low resolution of a vertical color signal and obtains a high-quality frame still image, and also changes a motion image by switching operations. A light quantity limiting means capable of blocking incident light, an imaging means having a pixel for photoelectrically changing the incident light and outputting a signal of the pixel as a digital video signal, a signal processing circuit for generating a digital video signal of a predetermined format, And a recording means for recording a digital video signal of a still image output from the imaging means or the signal processing circuit.

By using such a digital camera, it is possible to supply an inexpensive video input means, and to realize an image pickup device in which the vertical resolution of a color signal is reduced and a high-quality frame still image is obtained. The effect that a moving image can also be processed is obtained.

Description

Still image recording digital camera

1 is a block diagram showing an embodiment of the present invention;

2 is a configuration diagram of an image pickup device;

3 is a diagram showing a driving pulse of the imaging device and its output;

4 is a diagram showing a driving pulse of the imaging device and its output;

5 is a configuration diagram of a signal processing circuit;

6 shows a specific example of the matrix circuit;

7A, 7B and 7C show concrete examples of signal processing at the time of motion image pickup;

8A, 8B and 8C show concrete examples of signal processing at the time of motion image pickup;

9A, 9B and 9C show concrete examples of signal processing at the time of still image pick-up;

10A, 10B and 10C show specific examples of signal processing at the time of still image pick-up;

11A, 11B and 11C and 11D show specific examples of the sampling circuits,

12 is a block diagram showing another embodiment of the present invention;

13A and 13B are explanatory diagrams of the embodiment shown in FIG. 12;

14 is a block diagram of another embodiment of the present invention;

15 is a block diagram of another embodiment of the present invention;

16 is an explanatory diagram of an interpolation method for generating each complementary color;

17 is a diagram showing one specific example of a color interpolation circuit;

18 is a block diagram of another embodiment of the present invention;

19 is an explanatory diagram of an interpolation method for generating each interpolation color in five vertical lines;

20 is a block diagram of another embodiment of the present invention;

21 is a diagram showing one specific example of an adaptive color processing circuit;

22 is a diagram showing one specific example of a reference signal generation circuit;

23 shows one specific example of the coefficient combining circuit;

24 is a block diagram of another embodiment of the present invention;

25 is a block diagram of another embodiment of the present invention;

FIG. 26 is an explanatory diagram of the embodiment shown in FIG. 31;

27 is a configuration diagram of a white balance circuit;

28A, 28B and 28C show specific examples of signal output;

29A and 29B show specific examples of signal output;

30A and 30B show specific examples of signal output;

31 is a block diagram showing an embodiment of the present invention;

32 is a spatial distribution diagram of a signal according to an embodiment of the present invention;

33 is a timing diagram of an output signal of the image pickup device according to the embodiment of the present invention;

34 is a signal format diagram at the time of independent read according to the embodiment of the present invention;

35 is a view showing nonlinear input / output characteristics according to an embodiment of the present invention;

36 shows non-linear input / output characteristics according to an embodiment of the present invention;

37 is a signal format diagram at the time of pixel mixed read according to the embodiment of the present invention;

38 is a spatial distribution diagram of a signal according to an embodiment of the present invention;

39 is a block diagram showing the construction of an imaging device according to an embodiment of the present invention;

40 is a spatial distribution diagram of a signal according to an embodiment of the present invention;

41 is a block diagram showing the construction of a signal interpolation circuit according to the embodiment of the present invention;

42 is a signal format diagram at the time of pixel mixed read according to the embodiment of the present invention;

43 is a spatial distribution diagram of a signal according to an embodiment of the present invention.

[Purpose of invention]

[Technical Field of the Invention and Prior Art in the Field]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital cameras, and more particularly, to a method of recording and reproducing still images suitable for image input means such as a computer.

A variety of functions have been developed in accordance with digitalization of signal processing, and video cameras are attracting attention as image input means such as computers because they can easily output digital image signals. Although low cost video input means can be supplied to the digital camera as a video input means by using as many parts as are used in the camera unit of the consumer camera integrated VTR as much as possible, at present, special video input means such as line scanners I'm staying in supply.

[Technical problem to be achieved]

There are four items as important tasks for supplying a low cost image input means.

[1] Automatic control system can cope with still image. … In general video cameras, exposure control or white balance control is performed using an image signal. That is, the detector detects the illuminance, the color temperature, and the like separately, and detects the image signal and feeds it back to each control unit. However, even if detected by the video signal of the still picture, the detected still picture cannot be fed back.

[2] A still image of a frame can be generated by using a general image pickup device. … A general image pickup device is a breakdown lead that can read a pixel signal only once, and is a pixel mixing method that mixes and reads signals of two adjacent pixels in the vertical direction. If signal processing is executed while the read method is used, a still image with a resolution corresponding to the number of pixels cannot be generated.

[3] It is possible to use a general-purpose imaging device. … After patching a video signal to a computer, an operation such as rotation may be performed on the graphic on the graphic, and it is necessary to prevent distortion in the image at this time. For this purpose, the imaging subject may be photoelectrically converted to the same spatial sampling pitch in the horizontal and vertical directions. That is, an imaging device having pixels arranged at the same distance in the horizontal and vertical directions may be used. However, in the image pickup device which is generally used in the camera unit of the consumer camera integrated VTR, pixels are arranged at different pitches in the horizontal and vertical directions.

[4] The capacity of the recording means for recording the still image is as small as possible. … When a still image is recorded by an RGB signal, which is a general video signal fetched to a computer, an address is required for each of R, G, and B, thereby increasing the storage capacity.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and to provide a low cost image input means by generating a still image image signal using a general image pickup device without requiring a detector for detecting illuminance or color temperature.

It is another object of the present invention to provide a technique capable of realizing an image pickup device in which the vertical resolution of a color signal is reduced and a frame still image of high quality can be obtained, and also a motion image can be processed by switching the operation.

[Configuration of Invention]

As a means for solving the above problem [1], a detection result at the time of motion image pickup is stored and a still image is generated in accordance with the detection result.

In addition, as a means for solving the above problem [2], when a still image image signal is input to the signal processing circuit by changing the driving method of the image pickup device without mixing the signal of the pixel by changing the driving method of the image pickup element. The contents of the process are switched to still images.

In particular, in still image signal processing, the phase of the sample hold is inverted for each horizontal scan line or the interpolation coefficient for each horizontal scan line is changed for Mg and G signals in which pixel arrays are alternately replaced for each line.

Further, as a means for solving the above problem [3], a signal interpolation circuit for performing interpolation operation is provided, and an image output from an image pickup means having a general image pickup device in which pixels are arranged at different pitches in the horizontal and vertical directions. The interpolation operation is performed on the signals, and video signals having the same spatial sampling pitch are generated in the horizontal and vertical directions.

In addition, as a means for solving the above problem [4], when recording to the recording means, the video signal output from the imaging means is recorded without performing processing such as luminance signal processing or color signal processing. In an image pickup means having a general image pickup device, a so-called complementary image signal is output, so that the image signal output from the recording means is subjected to processing such as luminance signal processing and color signal processing.

EMBODIMENT OF THE INVENTION Hereinafter, this invention is demonstrated using drawing.

1 is a configuration diagram of an image pickup apparatus according to a first embodiment of the present invention. In the same drawing, reference numeral 101 denotes a lens, 102 denotes a shutter, 103 denotes a shutter control circuit, 104 denotes an imaging device, 105 denotes a driving circuit, 106 denotes an amplifier, and 107 denotes A. / D converter, 108 is a memory, 109 is a memory control circuit, 110 is a record / playback control circuit, 111 is a shutter button, 112 is a playback button, 113 is a selection circuit, 114 is a signal processing circuit, 115 is a signal processing control circuit, 116 is a viewfinder, and 117 is a full / economy switching switch, and a specific example of the imaging device 104 is shown in FIG. In FIG. 2, reference numeral 201 denotes a photodiode, reference numeral 202 denotes a vertical CCD, reference numeral 203 denotes a horizontal CCD, and gr, mg, cy, and ye denote color filters disposed on the photodiodes 201, respectively. Green, mg is magenta, cy is cyan, ye is yellow color filter. The photodiode in which the above color filter is arranged is generally called a pixel. In the above configuration, the light input through the lens 101 is input to the image pickup device 104 through the shutter 102 whose aperture value F is controlled by the shutter control circuit 103, The signal charge photoelectrically converted by the photodiode 201 shown in FIG. 2 disposed on the surface is transmitted to the horizontal CCD 203 via the vertical CCD 202 and synchronized with the horizontal scanning pulse supplied from the driving circuit 105. The voltage is converted and output.

First, the operation at the time of motion image photographing is explained. The imaging device 104 reads signals in a so-called pixel mixing method in which two pixel signals adjacent in the vertical direction are mixed and read as described in Japanese Patent Laid-Open No. 63-114487 "Solid Color Camera". . Hereinafter, the pixel mixed lead will be described with reference to FIG. 3.

Fig. 3 is a diagram showing a timing diagram of the transfer of the signal transfer in the vertical transfer pulse and the vertical CCD 202 in the pixel mixed lead. In the same figure, the ternary pulse of the vertical transfer pulse 1 indicated by V1 becomes high level, so that the ternary pulse of the vertical transfer pulse 3 indicated by V3 becomes high level by the photodiode 201 of gr and mg rows. As a result, the ternary pulse of the vertical transfer pulse 3 indicated by V3 at the cy and ye rows becomes high level, so that the photodiodes 201 in the cy and ye rows are moved to the vertical CCD 202, respectively. Signal charge is transmitted. The signal charges transmitted to the vertical CCD 202 are mixed in the vertical CCD 202 and transmitted to the horizontal CCD 203 as shown in FIG. The output signal of the imaging device 104 is amplified by the amplifier 106 and input to the A / D converter 107. The signal input to the A / D converter 107 is sampled by the timing pulse supplied from the drive circuit and converted into a digital signal.

The signal converted into the digital signal by the A / D converter 107 is input into the signal processing circuit 114 by the selection circuit 113. The signal processing circuit 114 performs general signal processing such as gamma correction or white balance correction to generate a luminance signal, a color (RGB) signal, and the like.

Next, the operation of recording still images will be described.

In the above configuration, by pressing the shutter button 111, a control signal of the shutter close is input from the recording / reproduction control circuit 112 to the shutter control circuit 103, and the shutter control circuit 103 controls the shutter 102. ) Is closed after a predetermined time. Light input to the image pickup device 104 until the shutter 102 is in the closed state is photoelectrically converted by the photodiode 201 disposed in the image pickup device 104 so that the vertical CCD is held while the shutter 102 is in the closed state. It is transmitted to the horizontal CCD 203 via 202, and is voltage-transformed in synchronism with the horizontal scanning pulse supplied from the driving circuit 105 to be output. At this time, the image pickup device 104 is a so-called destructive lead in which the signal is not left in the photodiode 201 once the signal is read from the photodiode 201. Therefore, the information of the frame is lost when the pixel mixed lead is performed like the lead of the moving image. do. In order to obtain a still image without lowering the resolution in the vertical direction, the independent read described below is executed.

Fig. 4 is a diagram showing a timing diagram of the transfer of the signal transfer in the vertical transfer pulse and the vertical CCD 202 in the independent read. In the same figure, in the field where the ternary pulses of the vertical transfer pulse 1 and the vertical transfer pulse 3 become high levels, the signal charges are transferred to the vertical CCD 202 only in the photodiodes 201 in the gr and mg rows. In the field, the ternary pulse of the vertical transfer pulse 3 becomes high level, so that signal charge is transmitted to the vertical CCD 202 only in the photodiodes 201 of cy and mg rows. Since the signal charges transmitted to the vertical CCD 202 are all transmitted to the horizontal CCD 203 in one field period, the signal charges of the adjacent photodiodes 201 are not mixed with each other as in the pixel mixed lead method described above. One signal can be obtained for one photodiode. Hereinafter, the signal charge transmitted to the horizontal CCD 203 is output from the imaging device 104 in synchronization with the horizontal scanning pulse supplied from the driving circuit 105.

The signals Gr, Mg, Cy, and Ye read independently in each pixel by the above operation are converted into digital signals by the A / D converter 107 to the memory 108 controlled by the memory control circuit 109. Is recorded. On the other hand, the memory 108 also records information such as the white balance, which was executed by the signal processing circuit 114 at the time of motion image photographing before performing the still image recording. Information such as the white balance may be recorded in other recording means.

Next, the operation of outputting the recorded still image will be described.

When the control button 112 is pressed, the signal recorded in the memory 108 in accordance with the control signal from the recording / reproducing control circuit is selected by the selection circuit 113 and input to the signal processing circuit 114. The signal processing circuit 114 reads information such as white balance and generates a predetermined video signal according to the information. On the other hand, the viewfinder 116 displays the number of still images that can be recorded in the memory 108 by a control signal from the recording / playback control circuit 110, in addition to displaying the subject, or switching between Full / Economy and standby states. Information to be described later is displayed.

Next, the operation of the signal processing circuit 114 will be described.

At the time of moving image capturing, as described above, the pixel mixed lead reads the pixel signal from the image pickup device 104, and converts the signal shown in Fig. 3 into a digital signal by the A / D converter 107. Enter in (114). FIG. 5 shows a specific example of a signal processing circuit 144 that generates a luminance signal and a color difference signal from this input signal. In Fig. 5, reference numeral 211 denotes a sampling circuit for sampling an input signal to generate output signals, S1, S2, S3, and S4, and 212 using a luminance matrix set by the signal processing control circuit 115. A luminance matrix circuit for generating a luminance signal, 213 is a luminance signal processing circuit for performing digital signal processing such as known gamma correction on the luminance signal generated by the luminance matrix 212, and 214 is a signal processing control circuit ( An RGB matrix circuit which generates an RGB signal using the matrix for RGB set by 115, 215 is a white balance circuit, and 216 is a color difference signal using a matrix for color difference signals set by the signal processing control circuit 115. It is a color difference matrix circuit that generates. 6 is a circuit configuration example of the luminance and RGB matrix circuits 212, 214, and 221, 222, 223, and 224 are multipliers for multiplying an input signal with a matrix coefficient, and 225. Is an adder for adding the outputs of the multipliers 221, 222, 223, and 224.

In FIG. 5, the sampling circuit 211 is provided with the signals s1, s2,... Shown in FIG. 7A, 7B, and 7C hold the sample as shown. 7A and 7C are timing diagrams of horizontal periods in which Cy + Gr or Ye + Mg signals are output from the imaging device 104, and FIG. 7B is timing diagrams in horizontal periods in which Cy + Mg or Ye + Gr are output. . Although not shown, the sampling circuit 211 has a line memory, for example, outputs the signals S1 and S2 of the same signal time series as the horizontal period of FIG. 7A in the horizontal period of FIG. 7B, and outputs the horizontal period of FIG. 7C. Even if they are, signals S3 and S4 of the same signal time series as the horizontal period in Fig. 7B are output. The signals Gr + Cy, Mg + Ye, Mg + Cy, and Gr + Ye of this sample hold are raised by the matrix coefficients M1 and M2 shown in Figs. 8A and 8C in the luminance matrix circuit 212 and the RGB matrix circuit 214. The signal is converted into luminance signals Y and RGB signals, G, R, and B. Specific examples of the matrix coefficients M1 and M2 shown in Figs. 8A and 8B will be described next.

[Equation 1]

M ₁₁ = M ₁₂ = M ₁₃ = M ₁₄ = 1

M ₂₁ = -2, M ₂₂ = 2, M ₂₃ = 0, M ₂₄ = 1

M ₃₁ = 1, M ₃₂ = -1, M ₃₃ = 0, M ₃₄ = 2

M ₄₁ = 1, M ₄₂ = 0, M ₄₃ = 2, M ₄₄ = -2

The color difference signals R-Y and B-Y can also be generated similarly by the circuit configuration shown in FIG. 6, and the specific example described below may be used as the matrix coefficient M3 shown in FIG. 8C.

[Equation 2]

M ₅₁ = 0.7, M ₅₂ = -0.59, M ₅₃ = -0.11

M ₆₁ = -0.3, M ₆₂ = -0.59, M ₆₃ = 0.89

The matrix coefficients M1, M2, M3 are set by the signal processing control circuit 115.

Next, signal generation of still images will be described.

When generating a still image, as described above, the signal of each pixel is independently read from the imaging device 104 by an independent lead, and converted into a digital signal by the A / D converter 107 to convert the signal sequence shown in FIG. Write to memory 108.

In the memory 108, the signal of the photodiode 201 in the first row, the signal of the photodiode 201 in the second row,. Are read in order and input to the signal processing circuit 114. As shown in Figs. 9A, 9B, and 9C, the sampling circuit 211 includes Gr, Mg, Gr, Mg,... Alternatively, the signals input in the time series of Cy, Ye, Cy, and Ye are sampled and held in the same manner as in the case of motion image photographing, and the signal processing control circuit 115 converts M2 in the matrix coefficients M1, M2, and M3 to the following matrix value M4. By setting again, luminance signals Y, color signals R, G, B and color difference signals RY, BY at the time of still image shooting shown in Figs. 10A, 10B, and 10C are generated.

[Equation 3]

M ₇₁ = 0, M ₇₂ = 1, M ₇₃ = -1, M ₇₄ = 1

M ₈₁ = -1, M ₈₂ = -1, M ₈₃ = 1, M ₈₄ = 1

M ₉₁ = 0, M ₉₂ = 1, M ₉₃ = 1, M ₉₄ = -1

As shown in Fig. 2, the arrangement of the color filters gr and mg is not more than one row gr, mg, gr,... And the order of, mg, gr, mg,. The sequence of, is repeated. Therefore, as shown in Figs. 9A and 9C, the order of Gr and Mg input to the signal processing circuit 114 is shifted by one pixel. 11A shows a specific example of the sampling circuit 211 for correcting the misalignment. In Fig. 11A, reference numerals 241 and 242 denote sample hold circuits, and A and B denote sample hold pulses of the sample hold circuits 241 and 242, respectively. As shown in Fig. 11B, in the signal processing which is the line N which leads the signal of the N-th photodiode 201, Mg, Gr,... Assuming that signals are input in the order of, the sample hold pulses A and B are supplied as shown in Fig. 11C, and sampled and held in the time series shown in Fig. 11D. Here, the sample hold circuits 241 and 242 pass the input signal when the sample hold pulse is at the high level, and output the signal at the previous high level when the sample hold pulse is at the high level. On the other hand, in the signal processing of the line N + 2 which leads the signal of the photodiode 201 of the N + 2nd line, Gr, Mg,... Since signals are input in the order of, the sample holding pulses A and B are supplied as shown by line N + 2 of FIG. 11C and sampled by the time series shown by line N + 2 of FIG. 11D.

Next, another embodiment of the present invention is shown in FIG. In FIG. 12, 251 is a signal processing circuit, 252 is a camera signal processing circuit, 253 is a signal interpolation circuit, 254 is a memory, and 255 is a signal processing control circuit. The common numbers are given the same number. The difference from the embodiment of FIG. 1 is that the output signal of the signal processing circuit 251 is written to the memory 254. Since the operation at the time of moving image pick-up is the same as the embodiment of Fig. 1, the operation at the time of still image pick-up is described next.

The signal output from the image pickup device 104 by the independent lead is input to the camera signal processing circuit 252 having the signal processing circuit shown in Fig. 5, using either the luminance signal or the color difference signal generation path. Output by passing. For example, the sampling circuit 211 outputs an input signal as S1, and the RGB matrix circuit 212 adds a signal multiplied by 1 to S1 and a signal multiplied by 0 to S2 to S4, and the luminance signal processing circuit. Reference numeral 213 outputs the output signal of the luminance matrix circuit 212 as it is. The signal interpolation circuit 253 performs signal time series conversion shown in Figs. 13A and 13B according to the control signal from the signal processing control circuit 255, and records the signal after the signal time series conversion in the memory 254. 13A and 13B show the spatial distribution of the signal output from the imaging device 104.

After the signals output from the image pickup device 104 are all recorded in the memory 254, the signals recorded in the memory 254 are input to the camera signal processing circuit 252 and controlled from the signal processing control circuit 255. The luminance signal Y and the color difference signals RY and BY are generated by the same signal processing as in the embodiment of FIG. 1 according to the signal. The signal interpolation circuit 253 outputs the luminance signal Y, the color difference signals R-Y, and B-Y as they are in accordance with the control signal from the signal processing control circuit 255.

If the signal interpolation circuit 253 can perform the signal interpolation shown in Figs. 13A and 13B, it is not necessary to perform signal time series conversion by sampling shown in Figs. 11B, 11C and 11D. That is, when signals Mg and Gr are input in the time series represented by the line N in FIG. 11B, the signal interpolation circuit 253 outputs the signals Mg 'and Gr' after interpolation as shown in FIG. When signals Gr and Mg are input in the time series shown by the line N + 2, the signal interpolation circuit 253 places the signal Gr 'after interpolation in two input Gr signals at the position of the input Mg signal as shown in Fig. 13B, Interpolation signal Mg 'after interpolation is generated at two input Mg signals at the position of input Gr signal, and output. Fig. 26 shows a specific example of the signal interpolation circuit 253 which executes the signal interpolation. In Fig. 26, reference numeral 401 denotes a delay circuit, 402, 403 denotes a multiplier, 404 denotes an adder, and K1 and K2 denote coefficients supplied from the signal processing control circuit 255. In FIG. The delay circuit 401 delays the input signal by two pixels, and sets the coefficients K1 to 0 and K2 to 1 for interpolation shown in FIG. 3A, and sets the coefficients K1 and K2 for interpolation shown in FIG. 13B, respectively. Set to 0.5.

Fig. 14 is a block diagram showing another embodiment of the present invention, where 90 is an image pickup device, 91 is a frame memory, 92 is a signal selection circuit, 3 is a color interpolation circuit, and 4 is a block diagram. RGB matrix. The image pickup device 90 is composed of four pixels A, B, C, and D (each pixel signal for explanation is given a number indicating a position) as shown in FIG. The pixels of A and B are alternately arranged every one line so as to generate. In this embodiment, each pixel signal is read as it is without the pixel blending of the image pickup device 90, and each pixel signal is fetched into the frame memory 91. From the signal fetched in the frame memory 91, signals of three adjacent vertical lines are extracted by the signal selection circuit 92 and supplied to the color interpolation circuit 3. Next, the color interpolation circuit 3 interpolates each of the color signals A, B, C, and D from the signals of the three vertical lines, and then outputs them as RGB signals by the RGB matrix circuit 5.

Incidentally, as described above, the color interpolation circuit 3 generates interpolation of each color signal, but this interpolation method will be described. First, since there are no pixels of A and B in the color signal interpolation generation of n2 lines, interpolation is performed by signals of n1 and n3 lines in the vertical direction. Since the positions of the pixels A and B are different in the n1 and n3 lines, it is necessary to change the interpolation coefficient in the horizontal direction. Here, suppose that one pixel of the color signal after interpolation is generated from five horizontal pixels of the signal before interpolation.

A = 1/2 (1 / 2A12 + 1 / 2A14)

+1/2 (1 / 4A31 + 1 / 2A33 + 1 / 4A35)

B = 1/2 (1 / 4B11 + 1 / 2B13 + 1 / 4A15)

+1/2 (1 / 2B32 + 1 / 2B34)

Recognition can be weighted to the center of the horizontal pixel and interpolated. In addition, since C and D exist in the n2 line, interpolation is generated by weighting only the horizontal direction. In other words,

C = 1/2 (1 / 2C21 + C23 + 1 / 2C25)

D = 1/2 (D22 + D24)

It becomes

Next, in the generation of the color signal between one horizontal syringe in n3 lines, since there are no pixels C and D, interpolation is performed at n2 and n4 lines, and A and B are interpolated at n3 lines. In other words,

A = 1/2 (1 / 2A31 + A33 + 1 / 2A35)

B = 1/2 (B32 + B34)

C = 1/2 (1 / 4C21 + 1 / 2C23 + 1 / 4C25)

+1/2 (1 / 4C41 + 1 / 2C43 + 1 / 4C45)

D = 1/2 (21 / D22 + 1 / 2D24)

+1/2 (1 / 2D42 + 1 / 2D44)

It becomes

Hereinafter, considering that pixel arrangements of A and B are alternately replaced for each line, in the n4 line,

A = 1/2 (1 / 4A31 + 1 / 2A33 + 1 / 4A35)

+1/2 (1 / 2A52 + 1 / 2A54)

B = 1/2 (1 / 2B32 + 1 / 2B34)

+1/2 (1 / 4B51 + 1 / 2B53 + 1 / 4B55)

C = 1/2 (1 / 2C41 + C23 + 1 / 2C45)

D = 1/2 (D42 + D24)

on line n5

A = 1/2 (A52 + A54)

B = 1/2 (1 / 2B51 + B53 + 1 / 2B55)

C = 1/2 (1 / 4C41 + 1 / 2C43 + 1 / 4C45)

+1/2 (1 / 4C61 + 1 / 2C63 + 1 / 4C65)

D = 1/2 (1 / 2D42 + 1 / 2D44)

+1/2 (1 / 2D62 + 1 / 2D64)

It becomes Thereafter, the color signal can be generated by sequentially repeating the interpolation coefficients in the n2, n3, n4, and n5 lines.

As described above, according to the present embodiment, color signals can be interpolated in three vertical lines, thereby realizing an image pickup device with less vertical resolution degradation of color signals. In the present embodiment, four color signals are described as A, B, C, and D. For example, four colors of Mg, G, Cy, and Ye are common, but any color can be reproduced in particular. In addition, the interpolation coefficient is only one example. If the coefficient is capable of interpolating color signals in three vertical lines, there is no need to be particularly limited to this coefficient.

Fig. 15 is a block diagram showing an embodiment of the present invention, which is different from the embodiment of Fig. 14 in that the signal selection circuit 92 is constituted by a 1H delay circuit, and the same function and the same operation have the same signal, The same reference numerals are used, and detailed description is omitted.

Here, in the case where the imaging device is a pixel arrangement as shown in Fig. 16, the signal according to the pixel arrangement of the imaging device read from the memory in Fig. 15 is a 1H delay signal delayed by the 1H delay circuits 2 and 3, It is supplied to the color interpolation circuit 3 together with the 2H delay signal, and interpolated to generate Mg, G, Ye and Cy, and then output as R, G and B signals by the R, G and B matrix circuits 4. do. Also in the present embodiment, when the color signal is interpolated similarly to the embodiment of FIG.

Mg = 1/2 (1 / 2Mg12 + 1 / 2Mg14)

+1/2 (1 / 4Mg31 + 1 / 2Mg33 + 1 / 4Mg35)

G = 1/2 (1 / 4G11 + 1 / 2G13 + 1 / 4G15)

+1/2 (1 / 2G32 + 1 / 2G34)

Ye = 1/2 (Ye22 + Ye24)

Cy = 1/2 (1/2 Cy21 + Cy23 + 1/2 Cy25)

In line n3

Mg = 1/2 (1 / 2Mg31 + Mg33 + 1 / 2Mg35)

G = 1/2 (G32 + G34)

Ye = 1/2 (1 / 2Ye22 + 1 / 2Ye24)

+1/2 (1 / 2Ye42 + 1 / 2Ye44)

Cy = 1/2 (1 / 4Cy21 + 1 / 2Cy23 + 1 / 4Cy25)

+1/2 (1 / 4Cy41 + 1 / 2Cy43 + 1 / 4Cy45)

In line n4

Mg = 1/2 (1 / 4Mg31 + 1 / 2Mg33 + 1 / 2Mg35)

+1/2 (1 / 2Mg52 + 1 / 2Mg54)

G = 1/2 (1 / 2G32 + 1 / 2G34)

+1/2 (1 / 4G51 + 1 / 2G53 + 1 / 4G55)

Ye = 1/2 (Ye42 + Ye44)

Cy = 1/2 (1/2 Cy41 + Cy43 + 1/4 Cy45)

on line n5

Mg = 1/2 (Mg52 + Mg54)

G = 1/2 (1 / 2G51 + G53 + 1 / 2G55)

Ye = 1/2 (1 / 2Ye42 + 1 / 2Ye44)

+1/2 (1 / 2Ye62 + 1 / 2Ye64)

Cy = 1/2 (1 / 4Cy41 + 1 / 2Cy43 + 1 / 4Cy45)

+1/2 (1 / 4Cy61 + 1 / 2Cy63 + 1 / 4Cy65)

It becomes

Thereafter, similarly to the embodiment of FIG. 14, the color signal can be generated by sequentially repeating the interpolation coefficients on the n2, n3, n4, and n5 lines.

Next, one specific example of the color interpolation circuit 3 will be described with reference to FIG. (5), (6) and (7) are horizontal interpolation filters, (21) to (24) adders, and (25) to (28) switch circuits. The horizontal interpolation filters 5, 6, and 7 are composed of one pixel delay circuits 8 to 11, counters 12 to 16, 19, 20, and adders 17, ( 18) and outputs 2-tap processing and 3-tap processing. The original signal, the 1H delay signal and the 2H delay signal read out from the memory are supplied to the horizontal interpolation filters 5, 6, and 7, respectively, and the filter processing outputs of the original signal and the 2H delay signal are added to the adders 21 through. After adding the 2-tap output and 3-tap output, respectively, by 24, the filter processing output of the 1H delay signal is directly input to the switch circuits 25 to 28. Here, by supplying a control signal to sequentially switch the switch circuits 25 to 28 at 4H cycles per 1H, each complementary color that satisfies the above interpolation equation can be output.

In addition, although one specific example of this color interpolation circuit is implemented by combining a one-dimensional filter, it is a matter of course that the two-dimensional filter can be realized, for example, regardless of the configuration if the above-described interpolation equation is satisfied.

In the present embodiment, the interpolation is performed using five horizontal pixels. However, interpolation of each of the complementary colors in accordance with the required signal band such as three pixels or seven pixels is no problem.

As described above, according to this embodiment, since the R, G, and B signals can be generated in three vertical lines as in the embodiment of Fig. 14, an image pickup device with less degradation in the vertical resolution of the color signal can be realized.

18 is a block diagram illustrating another embodiment of the present invention. The difference from the embodiment of FIG. 14 of this embodiment is a point configured to generate interpolation colors in signals of five vertical lines. The same function and the same operation are indicated by the same symbols and the same reference numerals, and detailed description thereof will be omitted.

In Fig. 18, the original signal and the 1H delayed signal, 2H delayed signal, 3H delayed signal, and 4H delayed signal delayed by the 1H delay circuits 29 to 32 are input to the color interpolation circuit 33, respectively. , Ye, and Cy are generated, but this operation will be described using FIG. 19.

Fig. 19 is a diagram showing the numbering of each pixel signal arranged on the pixel array of the image pickup device, and illustrates the case where signals between one horizontal syringe are generated at five vertical lines and five horizontal pixels. First, since the pixel signals Cy and Ye do not exist in generating a color signal between one horizontal syringe in n3 lines, Cy and Ye are interpolated in n2 and n4 lines. The weights of Mg and G are centered around the signal of n3 lines, and interpolated between n1 and n5 lines. therefore,

Mg = 1/4 (1 / 2Mg12 + 1 / 2Mg14)

+1/2 (1 / 4Mg31 + 1 / 2Mg33 + 1 / 4Mg35)

+1/4 (1 / 2Mg52 + 1 / 2Mg54)

G = 1/4 (1 / 4G11 + 1 / 2G13 + 1 / 4G15)

+1/2 (1 / 2G32 + 1 / 2G34)

+1/4 (1 / 4G51 + 1 / 2G53 + 1 / 4G55)

Ye = 1/2 (1 / 2Ye22 + 1 / 2Ye24)

+1/2 (1 / 2Ye42 + 1 / 2Ye44)

Cy = 1/2 (1 / 4Cy21 + 1 / 2Cy23 + 1 / 4Cy25)

+1/2 (1 / 4Cy41 + 1 / 2Cy43 + 1 / 4Cy45)

It becomes Next, in the n4 line, Mg and G signals are interpolated in n3 and n5 lines, and the Cy and Ye signals are weighted around the n4 line and interpolated in n2 and n6 lines. therefore,

Mg = 1/2 (1 / 4Mg31 + 1 / 2Mg33 + 1 / 4Mg35)

+1/2 (1 / 2Mg52 + 1 / 2Mg54)

G = 1/2 (1 / 2G32 + 1 / 2G34)

+1/2 (1 / 4G51 + 1 / 2G53 + 1 / 4G55)

Ye = 1/4 (1 / 2Ye22 + 1 / 2Ye24)

+1/2 (1 / 2Ye42 + 1 / 2Ye44)

+1/4 (1 / 2Ye62 + 1 / 2Ye64)

Cy = 1/4 (1 / 4Cy21 + 1 / 2Cy23 + 1 / 4Cy25)

+1/2 (1 / 4Cy41 + 1 / 2Cy43 + 1 / 4Cy45)

+1/4 (1 / 4Cy61 + 1 / 2Cy63 + 1 / 4Cy65)

It becomes Subsequently, as in the embodiment of FIG. 14, in consideration of the fact that the pixel arrangement of Mg and G is replaced for each line, in the n5 line

Mg = 1/4 (1 / 4Mg31 + 1 / 2Mg33 + 1 / 4Mg35)

+1/2 (1 / 2Mg52 + 1 / 2Mg54)

+1/4 (1 / 4Mg71 + 1 / 2Mg73 + 1 / 4Mg75)

G = 1/4 (1 / 2G32 + 1 / 2G34)

+1/2 (1 / 4G51 + 1 / 2G55 + 1 / 4G55)

+1/4 (1 / 2G72 + 1 / 2G74)

Ye = 1/2 (1 / 2Ye42 + 1 / 2Ye44)

+1/2 (1 / 2Ye62 + 1 / 2Ye64)

Cy = 1/2 (1 / 4Cy41 + 1 / 2Cy43 + 1 / 4Cy45)

+1/2 (1 / 4Cy61 + 1 / 2Cy63 + 1 / 4Cy65)

In line n6

Mg = 1/2 (1 / 2Mg52 + 1 / 2Mg54)

+1/2 (1 / 4Mg71 + 1 / 2Mg73 + 1 / 4Mg75)

G = 1/2 (1 / 4G51 + 1 / 2G53 + 1 / 4G55)

+1/2 (1 / 2G72 + 1 / 2G74)

Ye = 1/2 (1 / 2Ye42 + 1 / 2Ye44)

+1/2 (1 / 2Ye62 + 1 / 2Ye64)

+1/4 (1 / 2Ye82 + 1 / 2Ye84)

Cy = 1/4 (1 / 4Cy41 + 1 / 2Cy43 + 1 / 4Cy45)

+1/2 (1 / 4Cy61 + 1 / 2Cy63 + 1 / 4Cy65)

+1/4 (1 / 4Cy81 + 1 / 2Cy83 + 1 / 4Cy85)

It becomes As described in the embodiment of Fig. 14, the interpolation coefficient is changed for every four lines to generate the sequential color signals.

The interpolation coefficient of the above formula is one example of the coefficient for interpolating the color signal in five vertical lines, and is not particularly limited to this coefficient.

As described above, according to the present invention, since the interpolation is generated by weighting each complementary color in five vertical lines, the filter characteristics in the vertical direction also become two-tap and three-tap characteristics as in the horizontal direction, and thus interpolation characteristics in the horizontal and vertical directions. This matched signal processing can be realized.

20 is a block diagram illustrating another embodiment of the present invention. The difference from the first embodiment of this embodiment is that the adaptive color processing circuit is provided and configured to reduce the color moire at the vertical edges. The same functions and the same operations are denoted by the same reference numerals, and detailed description is omitted. do.

In Fig. 20, reference numeral 34 denotes an adaptive color processing circuit in which an original signal, a 1H delay signal, and a 2H delay signal are input, and gains are adjusted to appropriate levels at vertical edges, and then the signals of the three lines are converted into a color interpolation circuit ( 3) to supply. Next, the operation of the adaptive color processing circuit 34 will be described in detail with reference to FIG. In Fig. 21, reference numerals 35 to 37 denote reference signal generating circuits, reference numeral 38 denotes coefficient synthesis circuits, and reference numerals 39 to 41 are multiplication circuits. The reference signal generation circuits 35 to 37 are circuits for detecting the signal level serving as the reference for each line. The reference signal generation circuits 35 to 37 perform the gain adjustment of each line at a ratio corresponding to these reference signals, so that signals having the same composition need to be used. have.

MG + G = R + V + G

Ye + Cy = R + B + 2G

So, double the G of Mg, G line

MG + 2G = R + B + 2G

By using this method, the luminance signal having the same composition is obtained. Here, when the original signal, the 1H delay signal, and the 2H delay signal are S (n), S (n-1), and S (n-2), respectively, the outputs of the reference signal generation circuits 35 to 37 are respectively applied. The reference signals Y (n), Y (n-1), and Y (n-2) of the line are formed. These reference signals Y (n), Y (n-1) and Y (n-2) are supplied to the coefficient synthesizing circuit 38, and the original signals S (n), 1H delay signals S (n-1), 2H Gain coefficients k1, k2, and k3 for delay signal S (n-2) are generated. These coefficients k1, k2, k3, and k4 are multiplied by the original signals S (n), 1H delay signal S (n-1), and 2H delay signal S (n-2) by the multiplication circuits 39 to 41, respectively. do.

In this way, although the gain coefficient of each line is generated, if the level of the interpolated signal is larger than the level of the original signal, the level of the interpolated signal is greater than or equal to the level of the original signal since it causes a decrease in S / N. It is configured to generate coefficients. For example, the coefficients k1, k2, and k3 are set as follows.

k1 = (Yn-1) / MAX (Y (n), Y (n-1))

k2 = {Y (n) MAX (Y (n-1), Y (n) + Y (n-2)

/ MAX (Y (n-1), Y (n-2)} / 2

k3 = Y (n-1) / MAX (Y (n-1), Y (n-2))

Here, when the coefficient is k1, the denominator is MAX (Y (n), Y (n-1), so if Y (n-1) ≤ Y (n), k1 = Y (n-1) / Y (n) It becomes ≤ 1 and even if Y (n-1) Y (n), k1 does not become larger than 1. Therefore, the original signal S (n) is not amplified by interpolation, and the same applies to the coefficient k3. Although k2 does not become larger than 1, in order to obtain accurate color reproduction, S (n-1) is also level corrected so that the levels of S (n) and S (n-2) are the same.

FIG. 22 is a block diagram showing one specific example of the reference signal generating circuit in FIG. 21, wherein (42) to (45) are one pixel delay circuits, (46) to (55) are counting circuits, and (56). ) To 60 are switch circuits, and 61 is an adder. Here, assuming that signals are output by the pixel arrangement of FIG.

S (n) = G + Mg + 2G + Mg + G

= 2R + 2B + 4G

S (N-2) = 1 / 2Mg + 2G + Mg + 2G + 1 / 2Mg

= 2R + 2B + 4G

It becomes In the line S (n-1) where Ye and Cy are outputted,

S (n-1) = 1 / 2Ye + Cy + Ye + Cy + 1 / 2Ye

= 2R + 2B + 4G

The switch circuits 56 to 60 are switched so as to be. In other words, by switching the coefficients every 4H, a reference signal having the same composition of each line can be obtained.

FIG. 23 is a block diagram showing one specific example of the coefficient synthesizing circuit 38 in FIG. 21, wherein (62) and (63) are comparison circuits, (64) to (67) are dividers, and (68). ) Is an adder, and 69 is a counter.

In Fig. 23, the input reference signals Y (n) and Y (n-1) are compared by the comparison circuit 62, and the larger one of the reference signals is selected and output. The output signal of the comparison circuit 62 is supplied to the division circuit 65 to divide the reference signal Y (n-1). The output signal k1 of the division circuit 65 is obtained. Similarly, k3 is generated by the comparison circuit 63 and the division circuit 66 in the input reference signals Y (n-1) and Y (n-2). The output signal of the comparison circuit 62 is supplied to the division circuit 64 to divide the reference signal Y (n), and the output signal of the comparison circuit 63 is supplied to the division circuit 67 to supply the reference signal Y ( divides n-2). The outputs of the division circuits 64 and 67 are added and averaged by the counter 69 to obtain the coefficient k2.

As described above, in the present embodiment, even when there is a vertical edge, the correlation in the vertical direction does not decrease, so that the vertical color muware can be reduced without a decrease in S / N, and the vertical color resolution of the color signal is reduced. The imaging device can be realized.

FIG. 24 is a block diagram showing another embodiment of the present invention, wherein a difference from the above embodiment is that the image signal obtained from the image pickup device is fetched to a computer, processed by software, and then outputted after the same function. The same operation is denoted by the same symbol and the same symbol, and detailed description thereof is omitted.

In Fig. 24, 73 is an interface circuit, 74 is a computer, and 75 is a memory. The signal read out from the image pickup device 90 without pixel mixing is stored in the frame memory 91, and the signal stored in the frame memory is supplied to the computer 74 as image data via the interface circuit 73. Although the computer 74 processes the image data, it is possible, for example, to generate interpolated color signal data by software processing according to the interpolation equation of the embodiment of FIG. In addition, of course, in the other embodiments, software processing can be easily executed for signal processing.

In this way, the color signal data generated by the software is supplied to the memory 75 via the interface circuit 73, and then a signal is output from the memory 75 at a predetermined time to interpolate the color signals of each pixel. can do.

According to this embodiment, since the color signal can be interpolated by software, each process described in another embodiment of the present invention can be easily executed without changing the hardware, and an imaging device having excellent design freedom can be provided according to the required image quality. It can be realized. In addition, although the present embodiment has been described to generate interpolation of each pixel signal, it is also possible to perform generation of RGB signals, color difference signals RY, BY signals by software, and real-time processing and low-speed processing may be appropriately performed according to the processing speed of the computer. Can also be used.

FIG. 25 is a block diagram showing another embodiment of the present invention, in which the color difference signals R-Y and B-Y are generated from the RGB signals generated by the above-described embodiment. In Fig. 25, 76, 77, 78, 79, 80, and 81 are multiplication circuits, and 82 and 83 are addition circuits. The RGB signals are supplied to the multiplication circuits 76, 77, 78 and the multiplication circuits 79, 80, 81, respectively, and in the multiplication circuits 76, 77, 78, The order is 0.7-0.59, -0.11 times, and the multiplication circuits 79, 80, and 81 sequentially output -0.3, -0.59, and 0.89 times. The output signals are added by the addition circuits 82 and 83, respectively, and output. That is, the output of the addition circuit 82

0.7R-0.59G-0.11B

Signal to the output of the addition circuit 83

0.89B-0.59G-0.3R

Is obtained. The signals represented by these two equations are R-Y and B-Y signals, respectively. Further, by setting the multiplication coefficient of the multiplication circuit to 0.3, 0.59 and 0.11, respectively.

0.3R + 0.59G + 0.11B

It goes without saying that the luminance signal Y can be obtained.

As described above, according to this embodiment, not only the RGB signal but also the color difference signal R-Y, B-Y or the luminance signal Y can be generated. In addition, in the present embodiment, as in the fifth embodiment, the image signal can be fetched to the computer and the luminance signal can be generated by software.

The above is an embodiment in which a still image is recorded (called a full mode) without losing the frame information. Next, an embodiment in which a still image is recorded (referred to as an economy mode) with a small memory capacity accompanied by a deterioration in image quality is described. do.

The imaging device 104 outputs a signal by the above-described general pixel mixed lead even in still image pick-up. The signals output from the image pickup device 104 are thinned in the horizontal direction at a ratio of two to one by the memory control circuit 109 in the embodiment of FIG. 1 to be written to the memory 108, and the memory ( The signal read out in step 108 is subjected to the same matrix processing as in motion image pickup to generate a luminance signal and a color difference signal. In the embodiment of Fig. 12, the signal interpolation circuit 253 performs signal interpolation in the horizontal direction at two ratios, and the number of signals is cut in half and written to the memory 254.

By the above operation, since the number of signals in the vertical and horizontal directions can be 1/2, respectively, compared to the full mode, four times the number of still images can be recorded in the memory 108,254. The full mode and the economy mode are switched to the full / economy switching switch 119, and the viewfinder 116 shows how many still images can be recorded in the memory 108 and 254 depending on which mode is present. Mark on. In addition, the viewfinder 116 displays which mode it is in.

27 shows another embodiment of the present invention. 27 is a diagram showing the internal configuration of the white balance circuit 215, where 303 is an R-amp, 304 is a B-amp, 305 is a gain control circuit, 306 is an RY detection circuit, 307 is a BY detection circuit. In the present invention, the white balance control is applied to the white shift information obtained by performing white shift discrimination by the RY detection circuit 306 and the BY detection circuit 307 on the RY and BY color difference signals generated by the color difference matrix circuit 216. Therefore, the gain control circuit 305 executes by controlling the gains of the R-amp 303 and the B-amp 304. When the shutter button 111 is pressed, the image pickup device 104 obtains the gains of the R-amp 303 and the B-amp 304 calculated from the average of one field or a plurality of fields immediately before the shutter is turned on. The data is written to the memory 108 together with the image signal read by. At the time of reproduction, the R-amp 303 and the B-amp 304 are set to the gain recorded in the memory 108 to generate a video signal.

28 to 30 show another embodiment of the present invention. The same figure shows a digital image signal output from the signal processing circuit 114, and FIGS. 28A, 28B and 28C are examples of the case of outputting the luminance signal / color difference signal, and FIGS. 29A and 29B are R. FIG. An example of output as a / G / B signal, FIGS. 30A and 30B are examples of output as a signal corresponding to the color filter of the imaging device 104. Fig. 28A shows a method of extracting a general luminance / color difference signal (4: 2: 2 digital) and outputs Y, R-Y, and B-Y, respectively. FIG. 28B is a view of sequentially outputting the color difference signals of R-Y and B-Y by the sequential circuit 308. FIG. 28C is a diagram in which all signals of Y, R-Y, and B-Y are sequentially outputted. Fig. 29A adds gain information of R, G, and B to output data, whereby white balance control can be executed externally without executing white balance control in the present apparatus. 30A and 30B are similarly outputted without performing signal processing such as white balance control to the complementary color signals of Gr, Mg, Cy, and Ye obtained by the imaging device 104. Although not shown in the figure, parameters such as R and B gains for performing various signal processing are added to the head of the output data. When the R, G, and B signals are sequentially outputted, the matrix coefficient M3 of the color difference matrix circuit 216 is reduced.

[Equation 4]

M ₅₁ = 1, M ₅₂ = 0, M ₅₃ = 0

M ₆₁ = 0, M ₆₂ = 0, M ₆₃ = 0

Outputs the R signal from the R-Y output channel, and then reads the signal from the memory 108 or 254 again and simultaneously sets the matrix coefficient M3 of the color difference matrix circuit 216.

[Equation 5]

M ₅₁ = 0, M ₅₂ = 1, M ₅₃ = 0

M ₆₁ = 0, M ₆₂ = 0, M ₆₃ = 0

Outputs the G signal from the R-Y output channel, and then reads the signal from the memory 108 or 254 again and simultaneously sets the matrix coefficient M3 of the color difference matrix circuit 216.

[Equation 6]

M ₅₁ = 0, M ₅₂ = 0, M ₅₃ = 1

M ₆₁ = 0, M ₆₂ = 0, M ₆₃ = 0

It is also possible to set R-Y to output the B signal from the output channel.

Hereinafter, another Example of this invention is described using drawing.

31 is a configuration diagram of an image pickup apparatus according to another embodiment of the present invention. In Fig. 31, 1901 is a lens, 1902 is a shutter, 1901 is a shutter control circuit, 1904 is an imaging device, 1905 is a driving circuit, 1906 is an amplifier, and 1907 is A /. D converter, 1908 is a memory, 1909 is a buffer memory, 1910 is a main memory, 1911 is a memory control circuit, 1912 is a write / replay control circuit, 1913 is a selector circuit, 1914 ) Is a signal processing circuit, 1915 is a camera signal processing circuit, 1916 is a signal interpolation circuit, 1917 is a signal processing control circuit, 1918 is a shutter button, and 1919 is a full / economy switching switch. 1920 is a display device, and a specific example of the imaging device 1904 is shown in FIG. In FIG. 2, reference numeral 201 denotes a photodiode, reference numeral 202 denotes a vertical CCD, reference numeral 203 denotes a horizontal CCD, and gr, mg, cy, and ye denote color filters disposed on the photodiodes 201, respectively. Green, mg is magenta, cy is cyan, ye is yellow color filter. In the above configuration, the light input through the lens 1901 is input to the imaging device 1904 through the shutter 1902 whose aperture value F is controlled by the shutter control circuit 1903, and the The signal charge photoelectrically converted by the photodiode 201 shown in FIG. 2 disposed on the surface is transmitted to the horizontal CCD 203 via the vertical CCD 202 and synchronized with the horizontal scanning pulse supplied from the driving circuit 1905. The voltage is converted and output.

First, the operation at the time of motion image photographing is explained. The imaging device 1904 reads signals in a so-called pixel mixing method in which two pixel signals adjacent in the vertical direction are mixed and read as described in the above known example.

The output signal of the imaging device 1904 is amplified by the amplifier 1906 and input to the A / D converter 107. The signal input to the A / D converter 107 is sampled by the timing pulse supplied from the driving circuit 1905 and converted into a digital signal. The signal converted into the digital signal by the A / D converter 107 is input into the signal processing circuit 1914 by the selection circuit 1913. The signal processing circuit 1914 performs general signal processing such as gamma correction and white balance correction to generate a luminance signal, a color (RGB) signal, and the like.

Next, the operation of recording still images will be described.

In the above configuration, the control signal of the shutter close is input from the recording / reproduction control circuit 1912 to the shutter control circuit 1903 by pressing the shutter button 1918, and the shutter 1902 is made by the shutter control circuit 1903. ) Is closed after a predetermined time. Light input to the image pickup device 1904 until the shutter 1902 is in the closed state is photoelectrically changed by the photodiode 201 disposed in the image pickup device 1904, and is vertical while the shutter 1902 is in the closed state. It is transmitted to the horizontal CCD 203 via the CCD 202, and is voltage-converted and output in synchronization with the horizontal scanning pulse supplied from the driving circuit 1905. At this time, the image pickup device 1904 is a so-called destructive lead in which the signal is not left in the photodiode 201 once the signal is read from the photodiode 201. Thus, when the pixel mixed lead is performed similarly to the lead of the moving image, the frame information is displayed. It is lost. In order to obtain a still image without lowering the resolution in the vertical direction, the independent read described below is executed.

The signals Gr, Mg, Cy, and Ye read independently in each pixel by the above operation are converted into digital signals by the A / D converter 1907 to the memory 1908 controlled by the memory control circuit 1911. Is recorded. On the other hand, the memory 1908 also records information such as the white balance, which was executed by the signal processing circuit 1914 at the time of motion image photographing before performing the still image recording. Information such as the white balance may be recorded in other recording means.

Next, the operation of outputting the recorded still image will be described.

The signal recorded in the memory 1908 is selected by the selection circuit 1913 and input to the signal processing circuit 1914. The signal processing circuit 1914 reads information such as white balance and generates a predetermined video signal according to the information. By the way, the photodiode 201 which the imaging element 1904 has is arrange | positioned at the space | interval different generally from horizontal perpendicular | vertical. That is, the photodiode 201 is also called a pixel, and the pixel pitches Px and Py shown in FIG. 2 are not the same. Therefore, the sample is not spatially sampled at equal intervals and is not preferable as the image input means as described above. Thus, interpolation is performed by the signal interpolation circuit 1916 to equalize the horizontal and vertical pixel pitches. Next, the interpolation interpolation which makes spatial sampling pitches the same is demonstrated using FIG.26, FIG.32 and FIG.33.

FIG. 26 is a diagram showing a concrete example of the signal interpolation circuit 1916.

In FIG. 32, S ₁ , ₁ , S ₁ , ₂ , S ₁ , ₃ , S ₂ , ₁ , S ₂ , ₂ , S ₂ , and ₃ denoted by 0 are signals input to the signal interpolation circuit 1916. S ₁ , ₁ ′, S ₁ , ₂ ′, S ₁ , ₃ ′, S ₂ , ₁ ′, S ₂ , ₂ ′, S ₂ , ₃ , indicating the spatial distribution of the signal before interpolation Indicates a spatial distribution of the output of the adder 404 (signal after interpolation). When Px is the horizontal pixel pitch and Py is the vertical pixel pitch, the signals before interpolation are separated by integer multiples of Px and Py in the horizontal and vertical directions, respectively, and are here separated by Px and Py for simplicity. _{S 1, 1 S 1, 2} ', S 1, 3' after you have created a signal after the interpolation represented by "S _{1, 1} to the position of the" display the △ interpolated in the horizontal direction from the S _{1, 1} ' Since Py and 2Py may be generated at a distance away, the interpolation operation is obtained as shown in the following equation.

[Equation 7]

S ₁ , _{2 '=} S ₁ , ₁ * (Px-Py) / Px + S ₁ , ₂ * Py / Px

[Equation 8]

S ₁ , ₃ '= S ₁ , ₂ * (2Px-2Py) / Px

+ S ₁ , ₃ * (2Py-Px) / Px

That is, it is good to make M vertical pixels and N horizontal pixels, and generate next N 'horizontal data in the horizontal direction by interpolation interpolation.

[Equation 9]

N '= N * Px / Py

However, the video signal obtained by interpolation by the above method is widened in the horizontal direction. Thus, the imaging device 1904 is supplied with a horizontal scanning pulse which is faster than the horizontal scanning pulse of the frequency derived from the horizontal pixel. Next, a specific method is explained using FIG.

When the image pickup device 1904 uses a general NTSC image pickup device having a horizontal pixel pitch Px of 9.6 mu m, a vertical pixel pitch Py of 7.5 mu m, a horizontal pixel of 510 pixels, and a vertical pixel of 485 pixels, It is: (a horizontal frequency f _H) the frequency of the horizontal scanning pulse to be derived is 610f _H below.

[Equation 10]

510 * 63.56 (63.56-10.5) = 610.9

≒ 611

On the other hand, the number of signals in the horizontal direction generated by interpolation in Equation 9 is as follows.

[Equation 11]

510 * 9.6 / 7.5 = 652.8 ≒ 653

Therefore, using a horizontal scanning pulse of frequency 611f _H does not end the interpolation interpolation within one horizontal period. In order to solve the above problem, the frequency of the horizontal scanning pulse to be used is set to 782f _H as shown below.

[Equation 12]

653 * 63.56 / (63.56-10.5) = 782.2

≒ 782

The output signal 1 in FIG. 33 is a timing diagram when a signal is output from the imaging device using a horizontal scanning pulse of 611f _H , and the output signal 2 is a signal from the imaging device using a horizontal scanning pulse of 782f _H. Is a timing diagram in the case of outputting. In this embodiment, an output signal 2 reduced in the ratio of 510/653 (or 7.5 / 9.6) in the horizontal direction is obtained using a horizontal scanning pulse of 782f _H. Since the output signal 2 is multiplied by 653/510 (or 9.6 / 7.5) in the horizontal direction by the signal interpolation, the aspect ratio of the obtained video signal does not change.

Next, writing of the video signal to the memory 1908 will be described.

In the still picture recording, as described above, the signals of the respective pixels are independently read by the image pickup device 1904 by independent reads, converted into digital signals by the A / D converter 1907, and recorded in the memory 1908. . As shown in Fig. 4, Mg and Gr are sequentially output in the field where the vertical transfer pulse V1 is a ternary pulse, and Cy and Ye are output in the field where V3 is a ternary pulse. It is recorded in the format as shown in 34. When outputting still pictures, the above-described memory 1908 is recorded in the format as shown in FIG. When outputting a still image, the signals recorded in the memory 1098 are sequentially read, and the signal processing circuit 1914 generates a video signal of a predetermined format. For example, in order to generate R, G, and B of the three primary color signals, the matrix operation described below may be performed, and signal interpolation as described above may be performed on each of the signals of R, G, and B.

[Equation 13]

R = Mg-Cy + Ye

G = -Mg + Cy + Ye + Gr

B = Mg + Cy-Ye

At this time, for example, the memory 1908 is arranged at the rear end of the signal processing circuit 1914, and the signal output from the imaging device 1904 is subjected to the arithmetic processing of Equation 13 to generate the R, G, and B signals after interpolation. When the R, G, and B signals are recorded in the memory 1908, the memory capacity required for recording one image signal is

[Equation 14]

485 * 653 * 3 * (RGB) * 9 bit ≒ 8.6 M bit

to be. Here, 485 is the number of lines, 653 is the number of horizontal dots, and the resolution of the A / D converter 1907 is 9 bits. On the other hand, in this embodiment

[Equation 15]

485 * 510 * 3 * 9 bits ≒ 2.2M bits

It becomes the capacity of. In other words, by recording a complementary color signal, data is compressed to about 1/4.

The reason why the resolution of the A / D converter 1907 is 9 bits in Equations 14 and 15 is based on the result of the image quality evaluation that the S / N degradation due to the quantization error at the resolution of 8 bits is more than the allowable amount. However, when the general purpose memory is used as the memory 1908, considering that the bit structure of the general purpose memory is 8 bits in the depth direction, the resolution of the A / D converter 1907 is preferably 8 bits. Thus, the amplifier 1906 has the nonlinear input / output characteristics shown in FIG. 35, and is converted into a digital signal with an 8-bit resolution. In the low luminance region where quantization noise is significant, 9-bit resolution is converted into a digital signal, and in the high luminance region where quantization noise is not significant, the digital signal is compressed and converted to 8-bit or less resolution. The general memory of bits can be used. At this time, linear signal processing can be executed by having the signal processing circuit 1914 have the input / output characteristics shown in FIG. 36 as opposed to the input / output characteristics shown in FIG. The above-described nonlinear input and output characteristics can be easily realized by changing the gain of the amplifier 1906 according to the input signal level. Next, a specific configuration example of the memory 1908 in FIG. 31 will be described.

The internal structure of the memory 1908 is configured using two memories, a main memory 1910 and a buffer memory 1909, as shown in FIG. The memory 1908 needs to input and output the signal at the video rate in order to record the signal output from the A / D converter 1907. In addition, in order to record several still images, a large capacity memory is required. However, such memory is currently very expensive. Therefore, the main memory 1910 uses a large memory capacity but a slow data access speed (e.g., a flash memory, a magnetic disk or an optical disk), and the buffer memory 1909 uses an image memory capable of high speed operation. Use At the time of writing, the signal output from the A / D converter 1907 is written to the buffer memory 1909 which operates as a video lake. The signal for one still image recorded in the buffer memory 1909 is transmitted to the main memory 1910 and recorded according to the operation speed of the main memory 1910.

Next, a method of recording still images with a smaller memory capacity accompanied by a deterioration of image quality is described below.

Hereinafter, the still image recording method will be referred to as Full mode, and the still image recording method described next will be referred to as Economy mode.

The imaging device 1904 outputs a signal by the above-mentioned general pixel mixed lead. The signal output from the image pickup device 1904 is recorded in the main memory 1910 in the format shown in FIG. 37 in the same manner as in full-mode imaging. However, the signal recorded by this method has a different signal format from the Full mode as shown in Fig. 37, and the method of signal processing differs from the Full mode at the time of reproduction. Accordingly, when generating a video signal of a predetermined format, an identification signal indicating whether the signal is recorded in the full mode or the economy mode is required. This identification signal is recorded together with information such as the white balance.

Next, an operation of outputting a signal recorded in the Economy mode will be described.

As in the reproduction of the signal Full mode recorded in the main memory 1910, it is input to the signal processing circuit 1914, and generates a video signal of a predetermined format in accordance with information such as white balance. For example, the matrix equations for generating R, G, and B of the three primary color signals are different from the matrix equations described in Equation 13 described above, and the matrix equations described below are executed, and the respective signals of R, G, and B are executed. The signal interpolation shown in FIG. 38 may be executed.

[Equation 16]

R = 2 (Mg + Ye) + (Gr + Ye) -2 (Gr + Cy)

G =-(Mg + Ye) +2 (Gr + Ye) + (Gr + Cy)

B = 2 (Mg + Cy) -2 (Gr + Ye) + (Gr + Cy)

In FIG. 38, S ₁ , ₁ , S ₁ , ₂ , S ₁ , ₃ , S ₁ , ₄ , S ₁ , ₅ , S ₂ , ₁ , S ₂ , ₂ , S ₂ , ₃ , denoted by 0. S ₂ , ₄ , S ₂ , and ₅ represent a spatial distribution of a signal (a signal before interpolation) input to the signal interpolation circuit 1916, and S ₁ , ₁ ′, S ₁ , ₃ ′, S ₁ denoted by Δ. , ₅ , S ₂ , ₁ ′, S ₂ , ₃ ′, S ₂ , ₅ ′ represent the spatial distribution of the output of the adder 404 (signal after interpolation). At this time, since the signal is read by the pixel mixing method, the signal before interpolation is separated by an integer multiple of Px and 2Py in the horizontal and vertical directions, respectively, when Px is the horizontal pixel pitch and Py is the vertical pixel pitch. It is assumed to be separated by Px and Py. At this time, when the signal in the S horizontal direction is thinned at two ratios, the spatial distribution of the signal is set at an interval of 2 Px in the horizontal direction and 2 Py in the vertical direction. In other words, the signals are separated by integer multiples of Px and Py in the horizontal and vertical directions, respectively, and the spatial distribution of the signals in the horizontal and vertical directions can be equalized by using the signal interpolation method shown in FIG.

Also, the video signal obtained by interpolation by the above method is widened in the horizontal direction. Thus, the aspect change is executed by the method shown in FIG.

At this time, since the image pickup device 1904 outputs signals by the pixel mixing method, the number of signals per still image to be recorded in the memory is 1/2 compared with the above-described full mode recording method. Therefore, twice as many still images can be recorded.

The full / economy switching switch (1919) is used to select the two types of still image recording methods described above in the full mode and the economy mode. The driving method of the image pickup device 1904, the driving method of the memory 1908, and the like are selected according to the mode selected by the Full / Economy switching switch 1919. In addition, according to the operation of the full / economy switching switch (1919), the display device 1920 indicates which recording method is selected, and records still images for the next few images in the currently selected recording method. Show if you can.

Hereinafter, another Example of this invention is described using drawing.

39 is a configuration diagram of an image pickup device according to another embodiment of the present invention. 39, reference numeral 2701 denotes a lens, 2702 a shutter, 2703 a shutter control circuit, 2704 an image pickup device, 2705 a driving circuit, 2706 an amplifier, and 2707 an A / D converter, 2708 is a memory, 2709 is a buffer memory, 2710 is a main memory, 2711 is a memory control circuit, 2712 is a write / replay control circuit, 2713 is a selection circuit, 2714 denotes a signal processing circuit, 2715 denotes a camera signal processing circuit, 2716 denotes a signal interpolation circuit, 2717 denotes a signal processing control circuit, 2718 denotes a shutter battens, and 2719 denotes a full / economy switching switch. 2720 is a display device. In the present embodiment, the configuration and operation have a part in common with the above-described embodiment, and the differences will be described below.

The operation of photographing the moving image is exactly the same as in the above-described embodiment.

Next, the operation in the case of recording the still image in the full mode will be described.

In the same manner as in the above-described embodiment, the image pickup device 2704 outputs signals by independent leads. The signal output from the image pickup device 2704 is converted into a digital signal by the A / D converter 2707 and input to the buffer memory 2709. The buffer memory 2709 writes a signal for one still image and outputs the signal to the signal processing circuit 2714 via the selection circuit 2713. The signal processing circuit 2714 performs the same data compression as the nonlinear data compression performed in the above-described embodiment on the input signal (compression does not need to be performed), and records the signal in the main memory 2710. In addition, similarly to the embodiment described above, information such as white balance is also recorded.

Next, the operation of outputting the recorded still image will be described.

The signal recorded in the memory 1908 is input to the signal processing circuit 2714 via the selection circuit 2713 as in the above-described embodiment. The signal processing circuit 2714 performs reverse data compression as described above if nonlinear data compression is performed at the time of writing, and reads information such as white balance and the like according to the information as in the above-described embodiment. An image signal is generated, and interpolation by signal interpolation is then performed in order to make the pixel pitches in the horizontal and vertical directions the same.

Next, the operation of writing signals to the memory 2708 will be described in detail.

As shown in Fig. 39, the memory 2708 has a configuration of a buffer memory 2709 and a main memory 2710 as in the above-described embodiment. The signal output from the image pickup device 2704 is amplified by the amplifier 2706 having linear input / output characteristics and input to the A / D converter 2707. In this embodiment, for the reason described in the above embodiment, the A / D converter 2707 converts the signal output from the amplifier 2706 into a 9-bit digital signal. The signal converted into the digital signal by the A / D converter 2707 is output to the buffer memory 2709 in the main memory 2708 as in the above-described embodiment. However, since the number of bits of the signal output from the A / D converter 2707 is 9 bits, the buffer memory 2709 needs to have a bit structure of 9 bits in the depth direction. The signal for one still image recorded in the buffer memory 2709 is outputted to the signal processing circuit 2714 via the selection circuit 2713 at a data rate that matches the operation speed of the main memory 2710, and then the signal processing circuit ( 2714 compresses the input 9-bit digital signal into an 8-bit digital signal and converts it into an 8-bit digital signal by conversion equivalent to the data compression by the nonlinear I / O characteristic performed in the above-described embodiment.

In the above embodiment, the analog signal is subjected to data compression by nonlinear processing. However, the method used in the present embodiment can perform data compression by nonlinear processing by digital processing. Therefore, ideal data compression without deviation can be achieved. In addition, since the signal interpolation circuit 2716 does not need to operate at the video rate, there is a time margin for the operation, and thus a simple circuit configuration can be taken.

Next, a method (Economy mode) for recording a still image with a smaller memory capacity but accompanied by a deterioration in image quality will be described below.

The image pickup device 2704 outputs a signal by the above-described general pixel mixed lead. The signal output from the image pickup device 2704 is once written to the buffer memory 2709 and output to the signal processing circuit 2714 in accordance with the operation speed of the main memory 2710 as in full-mode imaging. The signal interpolation circuit 2716 performs signal interpolation in the manner shown in FIG. In this case, since signal components adjacent to each other of the input signals are different, signal interpolation by the above-described method cannot be performed. As a specific configuration example of the signal interpolation circuit 2716 in the embodiment of Fig. 41, reference numeral 2901 denotes a separation circuit, 2902, 2903 a delay circuit, 2904, 2905, 2906, 2907 is a multiplier, 2908, 2909 is an adder, and 2910 is a multiplexer. Gr + Cy, Mg + Ye... Or Mg + Cy, Gr + Ye... The signals input in this order are divided into Gr + Cy and Mg + Ye or Mg + Cy and Gr + Ye by the separating circuit 2901, and each signal is separated by the two-phase interpolation circuit according to the format of FIG. Interpolate

The signal interpolated by the above operation by the signal interpolation circuit 2716 is recorded in the main memory 2710. FIG. 42 shows signal formats in the Economy mode recorded in the main memory 2710. FIG. However, similarly to the above embodiment, the signal recorded in the present invention differs from the Full mode and the signal processing method in reproduction. Therefore, information indicating whether the signal is recorded in the Full mode or the Economy mode is also recorded with information such as the white balance.

Next, an operation of outputting a signal recorded in the Economy mode will be described.

The signal recorded in the main memory 2710 is input to the signal processing circuit 2714 as in the reproduction of the full mode to generate a video signal in a predetermined format.

For example, the matrix arithmetic expression for generating R, G, and B of the three primary color signals executes the matrix arithmetic expression represented by the above expression 15, and interpolates the signal shown in Fig. 43 to each of the signals of the R, G, and B signals. You can run

In FIG. 43, S ₁ , ₁ , S ₁ , ₂ , S ₁ , ₃ , S ₂ , ₁ , S ₂ , ₂ , S ₂ , and ₃ denoted by 0 are signals input to the signal interpolation circuit in FIG. 41. S ₁ , ₁ ′, S ₁ , ₃ ′, S ₁ , ₅ ′, S ₂ , ₁ ′, S ₂ , ₃ ′, S ₂ , ₅ , representing the spatial distribution of the (interpolated signal) Indicates a spatial distribution of the output (signal after interpolation) of the signal interpolation circuit. At this time, the signal is read by the pixel mixing method and the signal interpolation shown in Fig. 40 is executed. As far as it is, let's keep it 2Px, 2Py for the sake of simplicity. In other words, the signals are separated by integer multiples of Px and Py in the horizontal and vertical directions, respectively, and the spatial distribution of the signals in the horizontal and vertical directions can be equalized by using the signal interpolation method shown in FIG.

Also, the video signal obtained by interpolation by the above method is widened in the horizontal direction. Thus, the aspect change is executed by the method shown in FIG.

At this time, since the signal written to the main memory 2710 outputs the signal by the pixel mixing method from the image pickup device 2704, the number of data in the vertical direction is 1/2, and the signal interpolation circuit 2716 is horizontal. Since the number of signals in the direction is 1/2, it is compressed to 1/4 compared with the recording method in the Full mode described above. According to this method, four times as many still images as in full mode recording can be recorded.

The Full / Economy changeover switch 2719 is used to select the Full mode and the Economy mode. One of the above-described recording methods is selected according to the mode selected by the Full / Economy changeover switch 2719. In addition, depending on the operation of the Full / Economy selector switch 2719, the display device 2720 displays which recording method is selected and how many still images can be recorded in the future using the currently selected recording method. Is displayed.

[Effects of the Invention]

According to the above embodiment, since a still image video signal can be generated using a general image pickup device without requiring a detector for detecting illuminance, color temperature, or the like, it is possible to supply an inexpensive video input means.

In addition, the image pickup device which can reduce the vertical resolution of the color signal and obtain a frame still image of high quality can be realized, and the motion image can also be processed by switching the operation.

Claims (15)

Light quantity limiting means capable of blocking incident light, imaging means having a pixel for photoelectric conversion of incident light and outputting a signal of the pixel as a digital video signal, a signal processing circuit for generating a digital video signal of a predetermined format, and the imaging means or signal processing Recording means for recording a digital video signal of a still image output from the circuit, wherein the light quantity limiting means blocks incident light after limiting the amount of incident light to a predetermined amount, and the image pickup means receives the amount of incident light by the light quantity limiting means; Is limited to a predetermined amount, a digital video signal of a moving picture is output, and after blocking, a digital video signal of a still picture is output, and the signal processing circuit outputs the digital video signal of the moving picture and when the digital video signal of the moving picture is supplied. Characterized in that different signal processing is executed when the digital video signal is supplied. The still picture recording digital camera. 2. The signal processing circuit according to claim 1, wherein the signal processing circuit has a matrix circuit for generating a luminance signal or a color signal, and coefficients of the matrix circuit when the digital video signal of the moving picture is supplied and when the digital video signal of a still picture is supplied. Still image recording digital camera, characterized in that for switching. Light quantity limiting means capable of blocking incident light, imaging means having a pixel for photoelectric conversion of incident light and outputting a signal of the pixel as a digital video signal, a signal processing circuit for generating a digital video signal of a predetermined format, and the imaging means or signal processing Recording means for recording a digital video signal of a still image output from the circuit, wherein the light quantity limiting means blocks incident light after limiting the amount of incident light to a predetermined amount, and the image pickup means receives the amount of incident light by the light quantity limiting means; Is limited to a predetermined amount, a digital video signal of a moving picture is output, and after blocking, a digital video signal of a still picture is output, and the signal processing circuit outputs a luminance signal generated from the supplied digital video signal. And a color difference signal or an RGB signal or a digital video signal supplied to the still picture in parallel or A still image recording digital camera, characterized by outputting a serial digital signal. Light quantity limiting means capable of blocking incident light, imaging means having a pixel for photoelectric conversion of incident light and outputting a signal of the pixel as a digital video signal, a signal processing circuit for generating a digital video signal of a predetermined format, and the imaging means or the signal And recording means for recording the digital video signal output from the processing circuit, wherein the image pickup means outputs a digital video signal of a still image after the incident light is blocked by the light quantity limiting means, and the signal processing circuit outputs the digital image signal. Or interpolating and interpolating a digital video signal of a still picture supplied from said recording means. 5. The image pickup means according to claim 4, wherein pixels are arranged at intervals of a horizontal direction Px and a vertical direction Py (Px ≠ Py), and the signal processing circuit interpolates an interpolated digital image signal of a supplied still image in a horizontal direction. And generate approximately N × Px / Py digital video signals from the horizontal N digital video signals. Light-limiting means for blocking incident light, imaging means for outputting a signal of the pixel as a digital video signal having various types of pixels for photoelectric conversion of incident light by any one of various types of spectral characteristics, A signal processing circuit for generating a digital video signal and recording means for recording a digital video signal output from the imaging means or signal processing circuit, wherein the imaging means blocks the incident light amount by the light quantity limiting means and then the pixel; Are output as independent pixel signals, and the independent pixel signals recorded in the recording means are recorded, and the signal processing circuit generates a digital video signal of a predetermined format from the independent pixel signals recorded in the recording means. Still image recording digital camera. Light-limiting means for blocking incident light, imaging means for outputting a signal of the pixel as a digital image signal having various types of pixels for photoelectric conversion of incident light by any one of various types of spectral characteristics, a predetermined format A signal processing circuit for generating a digital video signal of the apparatus, recording means for recording the digital video signal output from the image pickup means or the signal processing circuit, and a recording / playback control circuit, wherein the recording / playback control circuit is operated by the light quantity limiting means. After blocking the incident light, the imaging means controls whether the signal of the pixel is output as an independent pixel signal, or the signal of several pixels is mixed and output as a mixed pixel signal, and the recording means includes the independent pixel signal or the mixed pixel. Record any one of the signals, and the signal processing circuit And a digital image signal of a predetermined format is generated from the independent pixel signal or the mixed pixel signal recorded in the. 8. The still image recording digital camera according to claim 7, wherein an identification signal for identifying which of an independent pixel signal or a mixed pixel signal is recorded is recorded in the recording means. 9. A still image recording digital camera according to claim 7 or 8, comprising display means for indicating which pixel signal of an independent pixel signal or a mixed pixel signal is to be recorded. 8. The still image recording digital camera according to claim 7, comprising display means for displaying the number of still images that can be recorded in said recording means. 7. The still image recording digital camera according to claim 6, wherein a circuit having a nonlinear input / output characteristic is disposed in a signal transmission path from the image pickup means or the image pickup means to the recording means. 8. The still image recording digital camera according to claim 7, wherein a circuit having a nonlinear input / output characteristic is arranged in a signal transmission path from the image pickup means or the image pickup means to the recording means. 5. The recording medium as claimed in claim 4, wherein the recording means has a buffer memory and a main memory, and the signal processing means stops at the buffer memory at an operating frequency lower than an operating frequency of writing a digital video signal of the still image to the buffer memory. And a digital image signal of an image is read and written to the main memory. 7. The recording medium according to claim 6, wherein said recording means has a buffer memory and a main memory, and said signal processing end stops at said buffer memory at an operating frequency lower than an operating frequency of writing a digital video signal of said still image to said buffer memory. And a digital image signal of an image is read and written to the main memory. 8. The recording apparatus according to claim 7, wherein said recording means has a buffer memory and a main memory, and said signal processing means stops at said buffer memory at an operating frequency lower than an operating frequency of writing a digital video signal of said still image to said buffer memory. And a digital image signal of an image is read and written to the main memory.

Images