JPH06189256A - Still image recording digital camera - Google Patents

Abstract

PURPOSE:To generate the video signal of a still image through the use of a general imaging device and to supply an inexpensive video input means by storing a detected result at the time of image-picking-up an animation and generating the still image based on the detected result. CONSTITUTION:Light inputted through a lens 101 is inputted to an imaging device 104 by a shutter control circuit 103 through a shutter 102 whose diaphragm value is controlled and a signal electric charge arranged on the surface of the device 104 is synchronized with a horizontal scanning pulse supplied from a driving circuit 105, voltage-converted and outputted. In this case, the circuit 103 limits incident light quantity to be prescribed quantity and, then, shuts off incident light. When the circuit 103 is limiting incident light quantity to be prescribed quantity, the device 104 outputs the digital video signal of an animation and outputs the digital video signal of a still image after shutting- off. A signal processing circuit 114 executes different signal processings when the digital video signal of the animation is supplied and when the digital video signal of the still image is supplied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital camera, and more particularly to a still image recording / reproducing method suitable for video input means such as a computer.

[0002]

2. Description of the Related Art Video cameras have been developed with various functions accompanying the digitization of signal processing.
Since it can easily output digital video signals, it is gaining attention as a video input means for computers and the like. A digital camera as an image input means can be provided with a low-priced image input means by using as many parts as are used in the camera part of a consumer-use camera-integrated VTR, but at present, a line scanner or the like. No special video input means are provided.

There are the following five items as important problems for supplying low-priced video input means.

(1) To enable an automatic control system to handle still images as well ... In a general video camera, exposure control and white balance control are performed using video signals. That is, a detector for detecting illuminance, color temperature, etc. is not separately provided, but is detected from the video signal and fed back to each control unit. However, even if it is detected from the video signal of a still image, it cannot be fed back to the detected still image.

(2) It is possible to generate a still image of a frame by using a general image pickup device ... A general image pickup device is a destructive read-out in which a pixel signal can be read out only once, and moreover, in the vertical direction. This is a pixel mixing method in which signals of two adjacent pixels are mixed and read out. If signal processing is performed in the above-described reading method, a still image with a resolution matching the number of pixels cannot be generated.

(3) To enable the use of a general-purpose image pickup device ... After the video signal is loaded into the computer, an operation such as rotation may be applied to the image on the graphic, and the image is not distorted at this time. Need to do so. For that purpose, the imaged subject may be photoelectrically converted at the same spatial sampling pitch in the horizontal and vertical directions.
That is, an image sensor having pixels arranged at equal distances in the horizontal and vertical directions may be used. However, in an image sensor generally used in a camera section of a consumer-integrated VTR, pixels are arranged at different pitches in the horizontal and vertical directions.

(4) Minimize the capacity of the recording means for recording a still image ... If a still image is recorded with RGB signals, which are general video signals taken into a computer,
An address is required for each of R, G, and B, which increases the recording capacity.

(5) Image output is a digital RGB signal ... A general video signal format to be taken into a computer is a digital RGB signal. However, a signal output from a general consumer-use VTR for consumer use is a composite or analog signal format of a Y / C signal. In order to obtain a digital RGB signal, the analog signal is converted into a digital RGB signal. A signal conversion circuit for conversion must be newly provided.

[0009]

As a means for solving the above problem (1), a detection result at the time of capturing a moving image is stored, and a still image is generated based on the detection result.

As a means for solving the above problem (2), when a still image is picked up, the driving method of the image pickup device is changed to read out the pixel signals without mixing them, and the still image video signal is sent to the signal processing circuit. When input, the contents of signal processing are switched to those for still images.

As a means for solving the above problem (3), a signal interpolating circuit for performing an interpolating operation is provided, and a general image pickup device in which pixels are arranged at different pitches in the horizontal and vertical directions is provided. The video signal output from the image pickup means is subjected to interpolation calculation to generate a video signal having the same spatial sampling pitch in the horizontal and vertical directions.

As a means for solving the above problem (4), when recording in the recording means, the video signal output from the image pickup means is recorded without being subjected to processing such as luminance signal processing and color signal processing. A so-called complementary color video signal is output from the image pickup means having a general image pickup element, and therefore the video signal outputted from the recording means is subjected to processing such as luminance signal processing and color signal processing.

As a means for solving the above problem (5), the signal output from the image pickup means or the signal processing circuit is recorded in the recording means, and the recording means records the recorded video signal a plurality of times. Then, the signal processing circuit changes the matrix coefficient for the R signal, the G signal, and the B signal in accordance with the signal output from the recording means, and then performs the frame sequential R conversion.
Generate a GB signal.

[0014]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an image pickup apparatus according to a first embodiment of the present invention. In the figure, 101 is a lens, 10
2 is a shutter, 103 is a shutter control circuit, 104 is an image sensor, 105 is a drive circuit, 106 is an amplifier, 107 is an A / D converter, 108 is a memory, 109 is a memory control circuit, 110 is a recording / reproduction control circuit, 111 is a shutter button, 112 is a reproduction button, 113 is a selection circuit, 114
Is a signal processing circuit, 115 is a signal processing control circuit, 116 is a viewfinder, 117 is Full / Economy.
FIG. 2 shows a specific example of the image sensor 104 which is a changeover switch. In FIG. 2, 201 is a photodiode and 20
2 is a vertical CCD, 203 is a horizontal CCD, gr, m
g, cy, and ye are color filters arranged in each of the photodiodes 201, gr is green, mg is magenta,
cy indicates a cyan color filter and ye indicates a yellow color filter. The photodiode in which the color filter as described above is arranged is generally called a pixel. In the above configuration,
Light input through the lens 101 is input to the image sensor 104 through the shutter 102 whose aperture value F is controlled by the shutter control circuit 103, and is photoelectrically converted by the photodiode 201 shown in FIG. 2 arranged on the surface of the image sensor 104. The generated signal charges are transferred to the horizontal CCD 203 via the vertical CCD 202 and voltage-converted and output in synchronization with the horizontal scanning pulse supplied from the drive circuit 105.

First, the operation when shooting a moving image will be described. The image pickup device 104 reads out signals by a so-called pixel mixing method, in which two pixel signals that are vertically adjacent to each other are mixed and read, as described in JP-A-63-114487, "Solid Color Camera". Hereinafter, the pixel mixture reading will be described with reference to FIG.

FIG. 3 is a timing chart showing the vertical transfer pulse and the transfer of the signal charge in the vertical CCD 202 during the pixel mixed read. In the figure, when the ternary pulse of the vertical transfer pulse 1 becomes high level, the ternary pulse of the vertical transfer pulse 3 becomes high level from the photodiodes 201 in the rows gr and mg.
Signal charges are transferred from the photodiodes 201 in the rows y and ye to the vertical CCDs 202, respectively. Vertical CCD 20
2 is transferred to the vertical CC as shown in FIG.
It is mixed in D202 and transferred to the horizontal CCD 203.

The output signal of the image pickup device 104 is supplied to the amplifier 10
The signal is amplified by 6 and input to the A / D converter 107. The signal input to the A / D converter 107 is sampled by the timing pulse supplied from the drive circuit and converted into a digital signal. The signal converted into the digital signal by the A / D converter 107 is the selection circuit 113.
Is input into the signal processing circuit 114. The signal processing circuit 114 performs general signal processing such as gamma correction and white balance correction to generate a luminance signal, a color (RGB) signal, and the like.

Next, the operation of recording a still image will be described.

In the above structure, the shutter button 111
By pressing, a shutter close control signal is input from the recording / reproduction control circuit 112 to the shutter control circuit 103, and the shutter control circuit 103 causes the shutter 102 to be released.
Becomes a closed state after a predetermined time. Shutter 10
The light that has been input to the image pickup element 104 until the second state is closed is obtained by the photodiode 2 arranged in the image pickup element 104.
The photoelectric conversion is performed by 01, and the horizontal CCD 20 passes through the vertical CCD 202 while the shutter 102 is in the closed state.
3, and the voltage is converted and output in synchronization with the horizontal scanning pulse supplied from the drive circuit 105. At this time, when the image sensor 104 reads out a signal from the photodiode 201 once, no signal remains in the photodiode 201,
Since this is so-called destructive reading, if pixel-mixed reading is performed as with moving image reading, frame information will be lost. In order to obtain a still image without deteriorating the vertical resolution, the following independent reading is performed.

FIG. 4 is a timing chart showing the vertical transfer pulse at the time of independent reading and the transfer of the signal charge in the vertical CCD 202. In FIG. 4, the vertical transfer pulse 1 and the vertical transfer pulse 3 have ternary pulses of high level every other field as shown in FIG. Therefore, in the field where the ternary pulse of the vertical transfer pulse 1 becomes high level, the signal charge is transferred to the vertical CCD 202 only from the photodiodes 201 in the rows gr and mg, and in the next one field, the ternary pulse of the vertical transfer pulse 3 is generated. Becomes high level, signal charges are transferred to the vertical CCD 202 only from the photodiodes 201 in the rows cy and mg. Since the signal charges transferred to the vertical CCD 202 are all transferred to the horizontal CCD 203 in one field period, the signal charges of the adjacent photodiodes 201 are not mixed as in the above-mentioned pixel mixing read method. One signal can be obtained for one photodiode. Below, horizontal CCD 20
The signal charge transferred to No. 3 is output from the image sensor 104 in synchronization with the horizontal scanning pulse supplied from the drive circuit 105.

The signals Gr, Mg, Cy and Ye read out independently from the respective pixels by the above operation are A /
It is converted into a digital signal by the D converter 107 and recorded in the memory 108 controlled by the memory control circuit 109. On the other hand, when shooting a movie before recording the still image,
Information such as white balance performed by the signal processing circuit 114 is also recorded in the memory 108. Information such as white balance may be recorded in another recording means.

Next, the operation of outputting the recorded still image will be described.

When the reproduction button 112 is pressed, the signal recorded in the memory 108 is selected by the selection circuit 113 based on the control signal from the recording / reproduction control circuit and input to the signal processing circuit 114. The signal processing circuit 114 reads information such as white balance and generates a predetermined video signal based on the information. On the other hand, in addition to displaying the subject, the viewfinder 116 displays the recording / playback control circuit 1
A control signal from 10 displays the number of still images that can be recorded in the memory 108, full / economy switching, and a standby state, which will be described later.

The operation of the signal processing circuit 114 will be described below.

At the time of shooting a moving image, the pixel signals are read out from the image sensor 104 by the pixel mixture reading as described above.
The digital signal is converted by the A / D converter 107, and then the signal shown in FIG.
The signal shown in is input to the signal processing circuit 114. A signal processing circuit 1 for generating a luminance signal and a color difference signal from this input signal
A specific example of 14 is shown in FIG. In FIG. 5, reference numeral 211 is a sample of the input signal to output the output signals S1, S2, S3, S
4 is a sampling circuit, 212 is a luminance matrix circuit that generates a luminance signal using a luminance matrix set by the signal processing control circuit 115, and 213 is a known gamma correction for the luminance signal generated by the luminance matrix circuit 212. A luminance signal processing circuit for performing digital signal processing such as, an RGB matrix circuit for generating an RGB signal by using an RGB matrix set by the signal processing control circuit 115, a white balance circuit 215, a signal processing control 216 It is a color difference matrix circuit that generates a color difference signal using the matrix for color difference signals set by the circuit 115. FIG. 6 shows a circuit configuration example of the luminance and RGB matrix circuits 212 and 214.
Reference numerals 1, 222, 223 and 224 denote multipliers for multiplying the input signal by matrix coefficients, and 225 denotes multipliers 221, 22.
It is an adder that adds up the outputs of 2, 223 and 224.

The sampling circuit 211 shown in FIG.
The signals s1, s2, ... Shown in FIG. 3 in which the signals are sequentially switched.
Are sample-held as shown in FIG. Figure 7 (a)
And (c) is a timing chart of a horizontal period in which a signal of Cy + Gr or Ye + Mg is output from the image sensor 104, and (b) is Cy + Mg or Ye + Gr.
3 is a timing chart of a horizontal period in which is output. Although not shown, the sampling circuit 211 has a line memory and outputs signals S1 and S2 in the same signal time series as in the horizontal period of (a) in the horizontal period of (b), for example.
In the horizontal period (c), the same signal time series signals S3 and S4 as those in the horizontal period (b) are output. The sampled and held signals Gr + Cy, Mg + Ye, Mg + Cy,
Gr + Ye is a luminance matrix circuit 212 and RGB
In the matrix circuit 214, the matrix coefficient M shown in FIG.
1 and M2 are multiplied to obtain a luminance signal Y and an RGB signal G,
Converted to R and B. The matrix coefficient M1 shown in FIG.
A specific example of M2 is shown below.

M ₁₁ = M ₁₂ = M ₁₃ = M ₁₄ = 1 M ₂₁ = -2, M ₂₂ = 2, M ₂₃ = 0, M ₂₄ = 1 M ₃₁ = 1, M ₃₂ = -1, M ₃₃ = 0, M ₃₄ = 2 (1) M ₄₁ = 1, M ₄₂ = 0, M ₄₃ = 2, M ₄₄ = -2 Color difference signals R-Y and B-Y are similarly generated with the circuit configuration shown in FIG. Therefore, the following specific example may be used as the matrix coefficient M3 shown in FIG.

M ₅₁ = 0.7, M ₅₂ = −0.59, M ₅₃ = −0.11 M ₆₁ = −0.3, M ₆₂ = −0.59, M ₆₃ = 0.89 (2) ) The matrix coefficients M1, M2, M3 are set by the signal processing control circuit 115.

Next, generation of a still image signal will be described.

At the time of generating a still image, the signal of each pixel is independently read from the image pickup element 104 by the independent reading as described above, converted into a digital signal by the A / D converter 107, and the signal train shown in FIG. Is recorded in the memory 108. From the memory 108, the signal of the photodiode 201 in the first row and the signal of the photodiode 201 in the second row shown in FIG.
Are read in this order and input to the signal processing circuit 114. The sampling circuit 211, as shown in FIG.
g, Gr, Mg, ... Or Cy, Ye, Cy, Ye,
10, the signals input in time series are sampled and held, and the signal processing control circuit 115 resets M2 of the matrix coefficients M1, M2, and M3 to the following matrix value M4. The luminance signal Y, the color signals R, G, B and the color difference signals RY, B at the time of shooting the still image shown
-Generate Y.

M ₇₁ = 0, M ₇₂ = 1, M ₇₃ = -1, M ₇₄ = 1 M ₈₁ = 1, M ₈₂ = -1, M ₈₃ = 1, M ₈₄ = 1 (3) M ₉₁ = 0, M ₉₂ = 1, M ₉₃ = 1, M ₉₄ = −1 As shown in FIG. 2, the color filters gr and mg are arranged every other row in the order of gr, mg, gr ,. , G
The sequence of r, mg, ... Is repeated. Therefore, as shown in FIG. 9, the signal processing circuit 114 is used in (a) and (c).
The order of Gr and Mg input to is shifted by one pixel. FIG. 11 shows a specific example of the sampling circuit 211 for correcting the above deviation. In FIG. 9A, reference numerals 241 and 242 are sample and hold circuits, and A and B are sample and hold pulses of the sample and hold circuits 241 and 242, respectively. When signals are input in the order of Mg, Gr, ... In the signal processing of the line N for reading the signal of the photodiode 201 of the Nth row as shown in FIG.
The sample hold pulses A and B are supplied as shown in (c), and sample hold is performed in the time series shown in (d). Here, the sample and hold circuits 241, 242 pass the input signal when the sample and hold pulse is at the high level, and output the signal at the immediately preceding high level when at the low level. On the other hand, in the signal processing of the line N + 2 for reading the signal of the photodiode 201 in the N + 2th row, signals are input in the order of Gr, Mg, ..., Therefore, the sample hold pulses A and B are changed to the line N + 2 of (c). Supply, (d)
Sample hold is performed in the time series indicated by the line N + 2.

Next, another embodiment of the present invention is shown in FIG.
In the figure, 251 is a signal processing circuit, 252 is a camera signal processing circuit, 253 is a signal interpolation circuit, 254 is a memory,
Reference numeral 255 denotes a signal processing control circuit, and those common to the embodiment of FIG. 1 are given the same numbers. The difference from the embodiment of FIG. 1 is that the output signal of the signal processing circuit 251 is recorded in the memory 254. Since the operation at the time of capturing a moving image is the same as that of the embodiment shown in FIG. 1, the operation at the time of capturing a still image will be described below.

The signal output from the image pickup device 104 in the independent reading is input to the camera signal processing circuit 252 having the signal processing circuit shown in FIG. 5, and any one of the luminance signal or the color difference signal generation path is used. It is output through. For example, the sampling circuit 211 outputs the input signal as it is to S1, and the luminance matrix circuit 212 outputs S1.
And a signal obtained by multiplying S2 to S4 by 0 are added, and the luminance signal processing circuit 213 determines the luminance matrix circuit 21.
The output signal of 2 is output as it is. Signal interpolation circuit 253
Performs the signal time series conversion shown in FIG. 13 based on the control signal from the signal processing control circuit 255, and records the signal after the signal time series conversion in the memory 254. Here, FIG.
Reference numeral 3 represents the spatial distribution of the signal output from the image sensor 104.

After the signal output from the image pickup device 104 is completely recorded in the memory 254, the signal recorded in the memory 254 is input to the camera signal processing circuit 252 and is also used as a control signal from the signal processing control circuit 255. The luminance signal Y and the color difference signal R- are processed by the same signal processing as that of the embodiment of FIG.
Y, BY are generated. The signal interpolation circuit 253 outputs the luminance signal Y and the color difference signals RY and BY as they are based on the control signal from the signal processing control circuit 255.

If the signal interpolation circuit 253 performs the signal interpolation shown in FIG. 13, it is not necessary to perform the signal time series conversion by sampling shown in FIG. That is, FIG. 11B
When the signals Mg and Gr are input in the time series indicated by the line N, the signal interpolation circuit 253 outputs the interpolated signals Mg ′ and Gr ′ as they are, as shown in FIG. ) The signals Gr and Mg are chronologically shown on the line N + 2.
13 is input, the signal interpolation circuit 253 displays
As shown in (b), the interpolated signal Gr ′ is generated from the two input Gr signals and the interpolated signal Mg ′ is generated from the two input Mg signals to the input Gr signal position. Output. FIG. 14 shows a concrete example of the signal interpolation circuit 253 for performing the signal interpolation. In FIG. 14, 401 is a delay circuit, 402 and 403 are multipliers, 404 is an adder, and K1 and K2 are coefficients supplied from the signal processing control circuit 255. The delay circuit 401 delays the input signal by two pixels, sets the coefficient K1 to 0 and K2 to 1 in the interpolation shown in FIG. 13A, and sets the coefficients K1 and K2 to the interpolation shown in FIG. 13B. Set each to 0.5.

The above is an embodiment in which a still image is recorded without damaging the frame information (called a full mode). Next, although the image quality is deteriorated, a still image is recorded with a small memory capacity (economic mode). An example will be described below.

The image pickup device 104 outputs a signal by the above-described general pixel mixture reading even when a still image is picked up. In the embodiment of FIG. 1, the signal output from the image sensor 104 is thinned out in the horizontal direction by the memory control circuit 109 at a ratio of one in two, and recorded in the memory 108.
The signals read from the memory 108 are subjected to the same matrix processing as in the case of capturing a moving image to generate a luminance signal and a color difference signal. Further, in the embodiment of FIG. 12, the signal interpolation circuit 25
In 3, the signal is interpolated in the horizontal direction at a rate of one in two, and the number of signals is reduced by half and recorded in the memory 254. With the above operation, the number of signals in the vertical and horizontal directions can be halved compared to the Full mode.
It is possible to record four times as many still images as four. Full / Economy mode is Full / E
The viewfinder 118 displays how many more still images can be recorded in the memories 108 and 254 depending on which mode is selected by the conomy switch 119. The mode in which the viewfinder 118 is set is displayed on the viewfinder 118.

Another embodiment of the present invention will be described below with reference to the drawings.

FIG. 26 is a block diagram of an image pickup apparatus according to another embodiment of the present invention. In the figure, reference numeral 2601 is a lens, 2
602 is a shutter, 2603 is a shutter control circuit, 26
Reference numeral 04 is an image sensor, 2605 is a drive circuit, 2606 is an amplifier, 2607 is an A / D converter, 2608 is a memory, and 26
09 is a buffer memory, 2610 is a main memory, 26
11 is a memory control circuit, 2612 is a recording / reproduction control circuit, 2613 is a selection circuit, 2614 is a signal processing circuit, 2
Reference numeral 615 is a camera signal processing circuit, 2616 is a signal interpolation circuit, 2617 is a signal processing control circuit, 2618 is a shutter button, 2619 is a full / economy changeover switch, 2620 is a display device, and an image sensor 260.
FIG. 27 shows a specific example of No. 4. In FIG. 27, 2701 is a photodiode, 2702 is a vertical CCD, 2703 is a horizontal CCD, gr, mg, cy, and ye are color filters arranged in each photodiode 2701, gr is green, mg is magenta, and cy is cy. Cyan and ye indicate a yellow color filter. In the above structure, the light input through the lens 2601 is input into the image sensor 2604 through the shutter 2602 whose aperture value F is controlled by the shutter control circuit 2603, and the photodiode 2701 shown in FIG. 27 arranged on the surface of the image sensor 2604. The signal charge photoelectrically converted by
The voltage is converted and output in synchronization with the horizontal scanning pulse transferred to the horizontal CCD 2703 via the CD 2702 and supplied from the drive circuit 2605.

First, the operation when shooting a moving image will be described. The image sensor 2604, as described in the above-mentioned known example,
The signals are read by a so-called pixel mixing method, in which two pixel signals that are adjacent in the vertical direction are mixed and read.

Pixel mixture reading will be described below with reference to FIG.

FIG. 3 is a timing chart showing the vertical transfer pulse and the transfer of the signal charge in the vertical CCD 2702 at the time of pixel mixed reading. In the figure, when the ternary pulse of the vertical transfer pulse 1 becomes high level, the photodiode 2701 of the rows gr and mg
When the ternary pulse of the vertical transfer pulse 3 becomes high level, the signal charges are transferred from the photodiodes 2701 in the rows cy and yes to the vertical CCD 2702, respectively. Vertical CC
The signal charges transferred to D2702 are mixed in the vertical CCD 2702 as shown in FIG.
Transferred to.

The output signal of the image pickup device 2604 is supplied to the amplifier 2
The signal is amplified by 606 and input to the A / D converter 2607. The signal input to the A / D converter 2607 is sampled by the timing pulse supplied from the drive circuit 2605 and converted into a digital signal. The signal converted into the digital signal by the A / D converter 2607 is input into the signal processing circuit 2614 by the selection circuit 2613. The signal processing circuit 2614 performs general signal processing such as gamma correction and white balance correction,
A luminance signal, a color (RGB) signal, etc. are generated.

Next, the operation of recording a still image will be described.

In the above structure, the shutter button 261
When 8 is pressed, a shutter close control signal is sent from the recording / reproducing control circuit 2612 to the shutter control circuit 2603.
And the shutter control circuit 2603 causes the shutter 2602 to be closed after a predetermined time. Before the shutter 2602 is closed, the image sensor 2
The light input to 604 is photoelectrically converted by the photodiode 2701 arranged in the image sensor 2604, transferred to the horizontal CCD 2703 via the vertical CCD 2702 while the shutter 2602 is in the closed state, and the drive circuit 260.
5, the voltage is converted and output in synchronization with the horizontal scanning pulse. At this time, the image sensor 2604 is so-called destructive readout in which no signal remains in the photodiode 2701 once the signal is read out from the photodiode 2701, so if the pixel mixed readout is performed similarly to the moving image readout, the frame information is lost. I will be destroyed. In order to obtain a still image without deteriorating the vertical resolution, the following independent reading is performed.

FIG. 4 is a timing chart of vertical transfer pulses during independent reading and transfer of signal charges in the vertical CCD 2702. In FIG. 4, the vertical transfer pulse 1 and the vertical transfer pulse 3 have ternary pulses of high level every other field as shown in FIG. Therefore, in the field in which the ternary pulse of the vertical transfer pulse 1 is at a high level, the signal charge is generated only from the photodiodes 2701 of the rows gr and mg in the vertical CCD 27.
02, and in the next 1 field, the ternary pulse of the vertical transfer pulse 3 becomes high level, so that cy, ye
Vertical CCD 27 only from photodiode 2701 in the row
The signal charge is transferred to 02. The signal charges transferred to the vertical CCD 2702 are all horizontal C in one field period.
Since it is transferred to the CD2703, the adjacent photodiode 270 is used as in the pixel mixed read method described above.
One signal charge is not mixed, and one signal can be obtained for one photodiode. Less than,
The signal charge transferred to the horizontal CCD 2703 is output from the image sensor 2604 in synchronization with the horizontal scanning pulse supplied from the drive circuit 2605.

The signals Gr, Mg, Cy and Ye read out independently from the respective pixels by the above operation are A /
It is converted into a digital signal by the D converter 2607 and recorded in the memory 2608 controlled by the memory control device 2611. On the other hand, the information such as the white balance performed by the signal processing circuit 2614 at the time of shooting the moving image before the still image recording is also recorded in the memory 2608. Information such as white balance may be recorded in another recording means.

Next, the operation of outputting the recorded still image will be described.

The signal recorded in the memory 2608 is selected by the selection circuit 2613 and input to the signal processing circuit 2614. The signal processing circuit 2614 reads information such as white balance and generates a predetermined video signal based on the information. By the way, the photodiodes 2701 included in the image sensor 2604 are generally arranged vertically and horizontally at different intervals. That is, the photodiode 270
1 is also called a pixel, and the pixel pitch P shown in FIG.
x and Py are not equal. Therefore, the optical images are not spatially sampled at equal intervals, which is not preferable as the image input means as described above. Therefore, in order to equalize the horizontal and vertical pixel pitches, interpolation is performed by the signal interpolation circuit 2616. Interpolation interpolation for equalizing spatial sampling pitches will be described below with reference to FIGS. 14, 28, 29, and 30.

FIG. 14 shows a concrete example of the signal interpolation circuit 2616.

In FIG. 28, S _1,1 and S indicated by ◯
_1,2 , S _1,3 , S _2,1 , S _2,2 and S _2,3 represent the spatial distribution of the signal (the signal before the interpolation) input to the signal interpolation circuit 2616, and are indicated by Δ. S _1,1 ', S _1,2 ',
S _1,3 ′, S _2,1 ′, S _2,2 ′, S _2,3 ′ are adders 4
4 shows the spatial distribution of the output of 04 (signal after interpolation).
When Px is a horizontal pixel pitch and Py is a vertical pixel pitch, the signal before interpolation is Px and Py in the horizontal and vertical directions, respectively.
It is assumed that they are separated by an integral multiple of, and here, for the sake of simplicity, they are separated by Px and Py. When generating the signal after the interpolation represented by S _{1, 1} 'to the position of S _{1, 1,} △
The interpolated signals S _1,2 ′ and S _1,3 ′ shown in ## EQU3 ## may be generated at a position separated by Py and 2Py in the horizontal direction from S _1,1 ′. Is calculated by the interpolation calculation of.

S _1,2 ′ = S _1,1 * (Px−Py) / Px + S _1,2 * Py / Px (7) S _1,3 ′ = S _1,2 * (2Px−2Py ) / Px + S _1,3 * (2Py-Px) / Px ... (8) In other words, the number of vertical pixels is M, the number of horizontal pixels is N, and the following N ′ horizontal horizontal The direction data may be generated by interpolation.

N ′ = N * Px / Py (9) However, the video signal obtained by interpolation by the above method is elongated in the horizontal direction. Therefore, the image sensor 2604 is supplied with a horizontal scanning pulse having a higher speed than the horizontal scanning pulse having the frequency derived from the number of horizontal pixels. The specific method will be described below with reference to FIG.

The image pickup element 2604 has a horizontal pixel pitch Px of 9.6 μm and a vertical pixel pitch Py of 7.
5 [mu] m, the horizontal pixel number 510 pixels, when using an imaging device of a general NTSC system of the vertical pixel number 485 pixels, the frequency of the horizontal scan pulses derived from the number of horizontal pixels, the following 610f _H (f _H: Horizontal Frequency ).

510 * 63.56 / (63.56-10.5) = 610.9≈611 (10) On the other hand, from the above equation (9), the number of horizontal signals generated by interpolation is The number is 653 below.

510 * 9.6 / 7.5 = 652.8≈653 (11) Therefore, when the horizontal scanning pulse having the frequency of 611f _H is used, the interpolation is not completed within one horizontal period. Will end up. In order to solve the above problem, the frequency of the horizontal scanning pulse used may be 782f _H below.

653 * 63.56 / (63.56-10.5) = 782.2.apprxeq.782 (12) In FIG. 29, the output signal 1 uses the horizontal scanning pulse of 611f _H as described above. It is a timing chart when a signal is output from the image sensor, and the output signal 2 is 782f.
₆ is a timing chart when a signal is output from the image pickup device using _H horizontal scanning pulses. In this embodiment, the horizontal scanning pulse of 782f _H is used to obtain the output signal 2 which is reduced in the horizontal direction at a rate of 510/653 (or 7.5 / 9.6). The output signal 2 is 653/510 (or 9.
6 / 7.5), the aspect ratio of the obtained video signal does not change.

The above-mentioned interpolation method is shown in the horizontal direction.
This will be described below.

In FIG. 30, S _1,1 and S indicated by ◯
_1,2 , S _2,1 , S _2,2 , S _3,1 , S _3,2 , S _4,1 , S
_{Reference numerals 4 and 2} represent the spatial distribution of the signal (the signal before the interpolation) input to the signal interpolation circuit 2616. Similar to the interpolation described above, 'assuming that generates a signal after interpolation represented by the signal of the interpolated indicated by △ S _2,1' S _1,1 in the position of S _{1, 1,} S _{3, 1} 'is Px vertically from S _1,1 ',
Since it may be generated at a position separated by 2Px, it can be obtained by interpolation calculation of interpolation as in the following equation.

S _2,1 '= S _2,1 * (2Py-Px) / Py + S _3,1 * (Px-Py) / Py ... (13) S _3,1 ' = S _3,1 * ( 3Py-2Px) / Py + S _4,1 * (2Px-2Py) / Py (14) In other words, M'vertical data obtained by the following equation (15) is generated by signal interpolation. .

M ′ = M * Py / Px (15) Next, writing of a video signal in the memory 2608 will be described.

At the time of recording a still image, the signal of each pixel is independently read from the image sensor 2604 by the independent reading as described above, converted into a digital signal by the A / D converter 2607, and recorded in the memory 2608. As shown in FIG. 4, Mg and Gr are sequentially output in a field in which the vertical transfer pulse V1 is a ternary pulse, and Cy and Ye are output in a field in which V3 is a ternary pulse.
Data is recorded in the memory 2608 in the format shown in FIG. When outputting a still image, the above memory 26
The signals recorded in 08 are sequentially read out, and the signal processing circuit 2614 generates a video signal of a predetermined format.
For example, in order to generate R, G, B of three primary color signals,
The matrix calculation shown below may be performed, and the signal interpolation as described above may be performed on each of the R, G, and B signals.

R = Mg−Cy + Ye G = −Mg + Cy + Ye + Gr (16) B = Mg + Cy−Ye At this time, the memory 2608 is provisionally arranged in the subsequent stage of the signal processing circuit 2614, and the signal output from the image sensor 2604 is
When the calculation processing of the equation (16) is performed to generate interpolated R, G, B signals and the R, G, B signals are recorded in the memory 2608, one frame of image signal is recorded. The required memory capacity is 485 * 653 * 3 (RGB) * 9 bit ≈ 8.6 Mbit (17). Here, 485 is the number of lines, 653 is the number of horizontal dots, and the resolution of the A / D converter 2607 is 9 bi.
t. On the other hand, in the present embodiment, the capacity of 485 * 510 * 9 bit≈2.2 Mbit ... (18) is sufficient. In other words, by recording complementary color signals,
This means that the data has been compressed to about 1/4.

The reason why the resolution of the A / D converter 2607 is set to 9 bits in the above equations (17) and (18) is that the resolution is 8
It is based on the image quality evaluation result that the S / N deterioration due to the quantization error at the bit is more than the allowable amount. However, when using general-purpose memory for the memory 2608,
Considering that the bit configuration of the general-purpose memory is 8 bits in the depth direction, the resolution of the A / D converter 2607 is 8 b.
It is desirable to be it. Therefore, the amplifier 2606 is provided with the nonlinear input / output characteristic shown in FIG. 32, and is converted into a digital signal with a resolution of 8 bits. Data is compressed by converting it into a digital signal with a resolution of 9 bits in a low-luminance region where quantization noise is conspicuous and by converting it into a digital signal with a resolution of 8 bits or less in a high-luminance region where quantization noise is not noticeable. Therefore, a general memory of 8 bits can be used. At this time, linear signal processing can be performed by providing the signal processing circuit 2614 with the input / output characteristic shown in FIG. 33, which is the reverse of the input / output characteristic shown in FIG. The above-mentioned nonlinear input / output characteristics are
This can be easily realized by changing the gain of the amplifier 2606 according to the input signal level.

Next, a specific configuration example of the memory 2608 in FIG. 26 will be described.

The internal structure of the memory 2608 is, as shown in FIG. 26, a main memory 2610 and a buffer memory 26.
It is configured to use two memories of 09. Memory 260
In order to record the signal output from the A / D converter 2607, the 8 needs to input and output the signal at the video rate. Moreover, a large-capacity memory is required to record a plurality of still images. However, such memories are currently very expensive. Therefore, a main memory 2610 having a large storage capacity but a low data access speed (for example, a flash memory, a magnetic disk, an optical disk, or the like) is used, and a buffer memory 2609 is an image memory or the like capable of high-speed operation. . At the time of recording, the signal output from the A / D converter 2607 is temporarily recorded in the buffer memory 2609 operating at the video rate. The signal for one still image recorded in the buffer memory 2609 is transferred to and recorded in the main memory 2610 at the operation speed of the main memory 2610.

Next, a method of recording a still image with a smaller memory capacity, which is accompanied by deterioration of image quality, will be described below.

Hereinafter, the still image recording method will be referred to as the full mode, and the still image recording method described below will be referred to as Economy.
Called mode.

The image sensor 2604 outputs a signal by the above-mentioned general pixel mixture reading. Image sensor 2
The signal output from 604 is recorded in the main memory 2610 in the format shown in FIG. 34 in the same manner as in Full mode shooting. However, the signal recorded by this method has a different signal format from the Full mode as shown in FIG. 34, and the signal processing method is different from the Full mode at the time of reproduction. Therefore, when generating a video signal of a predetermined format, an identification signal indicating whether the signal is recorded in the Full mode or the signal recorded in the Economy mode is required. This identification signal is recorded together with information such as white balance.

Next, the operation of outputting the signal recorded in the economy mode will be described.

The signal recorded in the main memory 2610 is processed by the signal processing circuit 2 as in the Full mode reproduction.
The image signal is input to 614 and a video signal of a predetermined format is generated based on information such as white balance. For example, the matrix calculation formula for generating R, G, and B of the three primary color signals is the following matrix calculation different from the matrix calculation formula shown in the above formula (16).
The signal interpolation shown in FIG. 35 may be performed on each of the G and B signals.

R = 2 (Mg + Ye) + (Gr + Ye) -2 (Gr + CY) G =-(Mg + Ye) +2 (Gr + Ye) + (Gr + Cy). (19) B = 2 (Mg + Cy) -2 (Gr + Ye) + ( Gr + Cy) At this time, since the image sensor 2604 outputs signals by the pixel mixing method, the number of signals per still image recorded in the memory is halved as compared with the recording method in the Full mode described above. . Therefore, it is possible to record twice as many still images.

Full mode, Economy described above
For selecting two types of still image recording modes, press the Ful
The l / Economy changeover switch 2619 is used. Full / Economy selector switch 261
9 selects a matrix calculation formula, a method for driving the image sensor 2604, and a memory 260.
8 driving method and the like are selected. Also, Full / Econ
In response to the operation of the omy changeover switch 2619, the display device 2620 displays which recording method is selected and can record the number of still images in the currently selected recording method. Is displayed.

Another embodiment of the present invention will be described below with reference to the drawings.

FIG. 36 is a block diagram of an image pickup apparatus according to another embodiment of the present invention. In the figure, 3601 is a lens, 3
Reference numeral 602 denotes a shutter, 3603 denotes a shutter control circuit, 36
Reference numeral 04 is an image sensor, 3605 is a drive circuit, 3606 is an amplifier, 3607 is an A / D converter, 3608 is a memory, and 36
09 is a buffer memory, 3610 is a main memory, 36
11 is a memory control circuit, 3612 is a recording / reproduction control circuit, 3613 is a selection circuit, 3614 is a signal processing circuit, 3
Reference numeral 615 is a camera signal processing circuit, 3616 is a signal interpolation circuit, 3617 is a signal processing control circuit, 3618 is a shutter button, 3619 is a Full / Economy switch, and 3620 is a display device. The structure and operation of this embodiment are common to those of the above-described embodiments, and the different points will be described below.

The operation of photographing a moving image is exactly the same as that of the above-mentioned embodiment.

Next, the operation when recording a still image in the Full mode will be described.

Similar to the above-described embodiment, the image pickup element 3604 outputs a signal by independent reading. Image sensor 360
The signal output from No. 4 is converted into a digital signal by the A / D converter 3607 and input to the buffer memory 3609. The buffer memory 3609 records a signal for one still image and outputs the signal to the signal processing circuit 3614 through the selection circuit 3613. Signal processing circuit 361
4 applies the same data compression to the input signal as the non-linear data compression performed in the above-described embodiment (it is not necessary to perform the compression), and records the signal in the main memory 3610. In addition, information such as white balance is recorded as in the above-described embodiment.

Next, the operation of outputting the recorded still image will be described.

The signal recorded in the main memory 3610 is transmitted through the selection circuit 3613 in the same manner as in the above-described embodiment.
It is input to the signal processing circuit 3614. Signal processing circuit 36
No. 14, if non-linear data compression is performed at the time of recording,
The reverse data compression as described above is performed, information such as white balance is read in the same manner as in the above-described embodiment, a predetermined video signal is generated based on the information, and the horizontal and vertical pixel pitches are similarly set. In order to make them equal, interpolation by signal interpolation is performed.

Next, the operation of recording a signal in the memory 3608 will be described in detail.

The memory 3608, as shown in FIG.
Similar to the above-described embodiment, the buffer memory 3609 and the main memory 3610 are provided. Image sensor 360
The signal output from No. 4 is amplified by the amplifier 3606 having a linear input / output characteristic and input to the A / D converter 3607. In the present embodiment, the A / D converter 3607 converts the signal output from the amplifier 3606 into a 9-bit digital signal for the reason described in the above embodiments.
The signal converted into a digital signal by the A / D converter 3607 is output to the buffer memory 3609 in the main memory 3608 as in the above-described embodiment. However, A / D
The number of bits of the signal output from the converter 3607 is 9b.
Since it is it, the buffer memory 3609 needs to be a memory whose bit configuration is 9 bits in the depth direction. The signal for one still image recorded in the buffer memory 3609 is output to the signal processing circuit 3614 via the selection circuit 3613 at a data rate matching the operation speed of the main memory 3610, and the signal processing circuit 3614 inputs the signal. The 9-bit digital signal thus generated is compressed into an 8-bit digital signal by conversion equivalent to the data compression based on the nonlinear input / output characteristic performed in the above-described embodiment, and recorded in the main memory 3610.

In the above-mentioned embodiment, the data compression by the non-linear processing is performed on the analog signal, but the method used in this embodiment can perform the data compression by the non-linear processing by the digital processing. Therefore, it is possible to perform ideal data compression without variations. Further, the signal interpolation circuit 3616 does not need to be operated at the video rate, and the operation has a time margin, so that a simple circuit configuration can be employed.

Next, a method (Economy mode) of recording a still image with a smaller memory capacity, although accompanied by deterioration of image quality, will be described below.

The image sensor 3604 outputs a signal by the above-mentioned general pixel mixture reading. Image sensor 3
The signal output from 604 is temporarily recorded in the buffer memory 3609 as in the Full mode shooting, and the signal processing circuit 361 matches the operation speed of the main memory 3610.
4 is output. The signal interpolation circuit 3616 performs signal interpolation by the method shown in FIG. In this case, since the adjacent signal components of the input signal are different, the signal interpolation by the above method cannot be performed. FIG. 38 shows a specific configuration example of the signal interpolation circuit 3616 in this embodiment. 3801 is a separation circuit, 3802 and 3803 are delay circuits, 3804 and 380.
5, 3806, 3807 are multipliers, 3808, 3809
Is an adder and 3810 is a multiplexer. Gr + C
y, Mg + Ye ... or Mg + Cy, Gr + Ye
The signals input in the order of ...
r + Cy and Mg + Ye or Mg + Cy and Gr + Ye
, And each signal is interpolated by the two-system interpolation circuit according to the format of FIG.

The signal interpolated by the above operation by the signal interpolation circuit 3616 is recorded in the main memory 3610. FIG. 39 shows the Ec recorded in the main memory 3610.
6 shows a signal format in the onomy mode. However, the signal recorded by this method as in the above embodiment is different from the above-mentioned Full mode in the signal processing method at the time of reproduction. Therefore, the information indicating whether the signal is recorded in the Full mode or the signal recorded in the Economy mode is also recorded together with the information such as the white balance.

Next, the operation of outputting the signal recorded in the Economy mode will be described.

The signal recorded in the main memory 3610 is processed by the signal processing circuit 3 in the same manner as in the Full mode reproduction.
It is input to 614 and a video signal of a predetermined format is generated.

For example, the matrix calculation equation for generating R, G, B of the three primary color signals is the matrix calculation shown in the above equation (19), and the R, G, B signals are shown in FIG. The signal interpolation shown may be performed.

At this time, since the signal recorded in the main memory 3610 is output from the image pickup element 3604 by the pixel mixing method, the number of data in the vertical direction is halved, and the signal is interpolated by the signal interpolation circuit 3616 in the horizontal direction. Number of signals of 1
Since it is set to / 2, it is compressed to 1/4 as compared with the recording method in the Full mode described above. According to this method, it is possible to record four times as many still images as in Full mode recording.

Full mode, Economy described above
A Full / Economy changeover switch 3619 is used to select the mode. Full / Economy
One of the above-described recording methods is selected according to the mode selected by the changeover switch 3619. In addition, Full / Economy selector switch 361
In accordance with the operation of 9, the display device 3620 displays which recording method is selected, and indicates how many more still images can be recorded with the currently selected recording method. indicate.

Another embodiment of the present invention will be described below with reference to the drawings.

FIG. 41 is a block diagram of an image pickup apparatus according to another embodiment of the present invention. In the figure, 4101 is a lens, 4
102 is a shutter, 4103 is a shutter control circuit, 41
Reference numeral 04 is an image sensor, 4105 is a drive circuit, 4106 is an amplifier, 4107 is an A / D converter, 4108 is a memory, 41
Reference numeral 09 is a memory control circuit, 4110 is a recording / reproduction control circuit, 4111 is a shutter button, 4112 is a reproduction button, 4113 is a selection circuit, 4114 is a signal processing circuit, 4
Reference numeral 115 is a camera signal processing circuit, 4116 is a signal interpolation circuit, 4117 is a signal processing control circuit, 4118 is a viewfinder, 4119 is a Full / Economic switch, and a specific example of the image sensor 4104 is shown in FIG. The photodiode 201 provided with the color filter as shown in FIG. 2 is generally called a pixel. In the above structure, light input through the lens 4101 is input to the image sensor 4104 through the shutter 4102 whose aperture value F is controlled by the shutter control circuit 4103.
The signal charge photoelectrically converted by the photodiode 201 shown in FIG. 2 arranged on the surface of the image pickup device 4104 is transferred to the horizontal CCD 203 via the vertical CCD 202 and is synchronized with the horizontal scanning pulse supplied from the drive circuit 4105 to generate a voltage. Converted and output.

First, the operation when shooting a moving image will be described. The image sensor 4104, as described in the above-mentioned known example,
The signals are read by a so-called pixel mixing method, in which two pixel signals that are adjacent in the vertical direction are mixed and read.

Pixel mixture reading will be described below with reference to FIG.

FIG. 3 is a timing chart showing the vertical transfer pulse and the signal charge transfer in the vertical CCD 202 at the time of pixel mixed read. In the figure, when the ternary pulse of the vertical transfer pulse 1 becomes high level, the ternary pulse of the vertical transfer pulse 3 becomes high level from the photodiode 4401 in the rows gr and mg.
Signal charges are transferred from the photodiodes 201 in the rows y and ye to the vertical CCDs 202, respectively. Vertical CCD 20
2 is transferred to the vertical CC as shown in FIG.
It is mixed in D202 and transferred to the horizontal CCD 203. The output signal of the image sensor 4104 is amplified by the amplifier 4106 and input to the A / D converter 4107.
The signal input to the A / D converter 4107 is sampled by the timing pulse supplied from the drive circuit and converted into a digital signal. The signal converted into the digital signal by the A / D converter 4107 is the selection circuit 411.
3 is input to the signal processing circuit 4114. The signal processing circuit 4114 performs general signal processing such as gamma correction and white balance correction to obtain a luminance signal and a color (RG
B) Generate a signal or the like.

Next, the operation of recording a still image will be described.

In the above structure, the shutter button 411
When 1 is pressed, a shutter close control signal is sent from the recording / reproduction control circuit 4110 to the shutter control circuit 4103.
The shutter control circuit 4103 causes the shutter 4102 to be closed after a predetermined time. By the time the shutter 4102 is closed, the image sensor 4
The light input to 104 is photoelectrically converted by the photodiode 201 arranged in the image sensor 4104, transferred to the horizontal CCD 203 via the vertical CCD 202 while the shutter 4102 is in the closed state, and supplied from the drive circuit 4105. The voltage is converted and output in synchronization with the scanning pulse. At this time, the image sensor 4104 reads the signal once from the photodiode 201,
This is so-called destructive readout, in which no signal remains at 1, so if the pixel-mixed readout is performed as in the case of moving image readout, frame information will be lost. In order to obtain a still image without deteriorating the vertical resolution, the following independent reading is performed.

FIG. 4 is a timing chart showing the vertical transfer pulse at the time of independent reading and the transfer of the signal charge in the vertical CCD 202. In FIG. 4, the vertical transfer pulse 1 and the vertical transfer pulse 3 have ternary pulses of high level every other field as shown in FIG. Therefore, in the field where the ternary pulse of the vertical transfer pulse 1 becomes high level, the signal charge is transferred to the vertical CCD 202 only from the photodiodes 201 in the rows gr and mg, and in the next one field, the ternary pulse of the vertical transfer pulse 3 is generated. Becomes high level, signal charges are transferred to the vertical CCD 202 only from the photodiodes 201 in the rows cy and ye. Since the signal charges transferred to the vertical CCD 202 are all transferred to the horizontal CCD 203 in one field period, the signal charges of the adjacent photodiodes 201 are not mixed as in the above-mentioned pixel mixing read method. One signal can be obtained for one photodiode. Below, horizontal CCD 20
The signal charge transferred to No. 3 is output from the image sensor 4104 in synchronization with the horizontal scanning pulse supplied from the drive circuit 4105.

The signals Gr, Mg, Cy and Ye read out independently from the respective pixels by the above operation are A /
The digital signal is converted by the D converter 4107 and recorded in the memory 4108 controlled by the memory control circuit 4109. On the other hand, information such as white balance performed by the signal processing circuit 4114 at the time of shooting a moving image before performing the still image recording is also recorded in the memory 4108. Further, information such as white balance may be recorded in another recording means.

Next, the operation of outputting the recorded still image will be described.

When the reproduction button 4112 is pressed, the signal recorded in the memory 4108 is selected by the selection circuit 4113 by the control signal from the recording / reproduction control circuit and input to the signal processing circuit 4114. Signal processing circuit 4114
Reads information such as white balance and generates an RGB signal based on the information. On the other hand, in addition to displaying the subject, the viewfinder 4118 displays the number of still images that can be recorded in the memory 4108 and Full / Economy according to a control signal from the recording / reproduction control circuit 4110.
The information described later such as switching is displayed.

The operation of the signal processing circuit 4114 will be described below.

At the time of shooting a moving image, a signal is read from the image pickup device 4104 by the above-mentioned pixel mixture reading, converted into a digital signal by the A / D converter 4107, and the signal shown in FIG. 3 is processed by the camera signal in the signal processing circuit 4114. Circuit 41
Enter in 15. A concrete example of the camera signal processing circuit 4115 for generating a luminance signal and a color difference signal from this input signal is shown in FIG.
2 shows. In the figure, 4201 is a sampling circuit,
Reference numeral 4202 is a luminance matrix circuit, 4203 is a luminance signal processing circuit, 4204 is an RGB matrix circuit, 4205 is a white balance circuit, 4206 is a Yc matrix circuit 4207, and a color difference matrix circuit. FIG. 43 shows a circuit configuration example of the luminance matrix circuit 4202. In FIG. 43, 4301 is an amplifier, 4302 is a matrix circuit, and 43.
Reference numeral 03 is a subtractor for outputting the difference between the signals output from the Yc matrix 4206 and the signal output from the matrix circuit 4302, 4304 is a low-pass filter, and 4305 is an adder. In FIG. 42, the sampling circuit 420
1 are signals s1 and s shown in FIG. 3 in which the signals are sequentially switched.
.. are sample-held as shown in FIG. Figure 7
(A) and (c) are Cy + Gr or Ye + Mg
6B is a timing chart of a horizontal period in which the signal is output from the image sensor 4104, and (b) is a timing chart of a horizontal period in which Cy + Mg or Ye + Gr is output. Although not shown, the sampling circuit 4201
Has a line memory and, for example, in the horizontal period of (b), signals S1 and S of the same signal time series as in the horizontal period of (a)
2 is output, and in the horizontal period (c), the same signal time series signals S3 and S4 as those in the horizontal period (b) are output. The sample-and-hold signals Gr + Cy, Mg + Ye,
Mg + Cy and Gr + Ye are the brightness matrix circuit 420
2 and the RGB matrix circuit 4204.
The signal input to the luminance matrix circuit 4202 is converted into the luminance signal y by the matrix calculation formula shown below.

Y = (Gr + Cy) + (Mg + Ye) + (Mg + Cy) + (Gr + Ye) (20) On the other hand, the signals input to the RGB matrix circuit 4204 are r signals, g Signal, b
Converted to a signal.

R = -2 (Gr + Cy) +2 (Mg + Ye) + (Gr + Ye) g = (Gr + Cy)-(Mg + Ye) +2 (Gr + Ye) ... (21) b = (Gr + Cy) +2 (Mg + Cy) -2 (Gr + Ye) ) The r signal output from the RGB matrix circuit 4204,
The g signal and the b signal are input to the Yc matrix circuit 4206 and converted into the yc signal by the matrix calculation formula shown below.

Yc = 0.30r + 0.59g + 0.11b (22) The yc signal generated by the above method is input to the luminance matrix circuit 4202, and the luminance matrix circuit 4202
Using the y and yc signals, the luminance signal Y is generated according to the following arithmetic expression.

Y = y + (ycl-yl) (23) Here, yl is the low-frequency component of the y signal, and ycl is the low-frequency component of the yc signal, which is band-limited by the low-pass filter 4304. Expression (23) can be expressed as Y = yh + ycl (24) using the high frequency component yh of the y signal, and the low frequency components of the luminance signal Y are r, g, b.
It is generated from the signal. By generating the low-frequency component of the luminance signal Y from the r, g, and b signals, there is no problem that the luminance rises when a red subject is imaged, for example.

The luminance signal Y generated by the above method is
It is input to the luminance signal processing circuit 4203 and subjected to known luminance signal processing such as gamma correction. The signals input to the color difference matrix circuit 4207 are converted into color difference signals R-Y and B-Y by the matrix calculation formula shown below.

R−Y = 0.7r−0.59g−0.11b B−Y = −0.3r−0.59g + 0.89b (25) The matrix coefficient is set by the signal processing control circuit 4117. .

Next, generation of a still image signal will be described.

At the time of generating a still image, the signal of each pixel is independently read from the image sensor 4104 by the independent reading as described above, converted into a digital signal by the A / D converter 4107, and the signal train shown in FIG. 4 is generated. It is recorded in the memory 4108. From the memory 4108, the signals of the photodiodes 201 in the first row and the photodiodes 201 in the second row shown in FIG.
The signals are read out in this order and input to the signal processing circuit 4114. The sampling circuit 4201, as shown in FIG.
Gr, Mg, Gr, Mg, ... Or Cy, Ye, C
The signals input in time series of y and Ye are sampled and held in the same manner as in the case of shooting a moving image. In addition, as shown in FIG.
The color filters gr and mg are arranged every other row gr and m.
The order of g, gr, ... And the order of mg, gr, mg ,. Therefore, as shown in FIG. 9, in (a) and (c), Gr and M input to the signal processing circuit 4114 are input.
The order of g is shifted by one pixel. A specific example of the sampling circuit 4201 for correcting the above deviation is shown in FIG. In FIG. 1A, reference numerals 241 and 242 denote sample and hold circuits, and A and B respectively.
1 and 242 are sample hold pulses. In the signal processing of the line N for reading out the signal of the photodiode 201 in the Nth row, as shown in FIG.
If signals are input in the order of Mg, Gr, ..., Sample-hold pulses A and B are supplied as shown in (c),
Sample holding is performed in time series shown in (d). here,
The sample hold circuits 241 and 242 pass the input signal when the sample hold pulse is at the high level, and output the signal at the immediately preceding high level when the sample hold pulse is at the low level.

On the other hand, the photodiode 201 on the (N + 2) th row
In the signal processing of the line N + 2 for reading the signal of
Since the signals are input in the order of Gr, Mg, ..., Sample-hold pulses A and B are supplied as in line N + 2 of (c), and the sample-hold pulses are arranged in the time series shown in line N + 2 of (d). To do.

Next, the operation for generating the R signal when outputting a still image will be described.

The signal sampled by the above method is input to the luminance matrix circuit 4202 and the RGB matrix circuit 4204. Luminance matrix circuit 42
02 and RGB matrix circuit 4204 The y, r, g, and b signals are generated according to the arithmetic expression. R
The signal generated by the GB matrix circuit 4204 is input to the white balance circuit 4205, subjected to the above white balance correction, and input to the Yc matrix circuit 4206. The Yc matrix circuit 4206 generates the signal yr of only the R signal component by the matrix calculation formula shown below.

Yr = 1 * r + 0 * g + 0 * b (27) From the signal obtained by the above operation, the R signal can be obtained by the following arithmetic expression.

[0118] Here, yrl and rl are low-frequency components of the yr and r signals, respectively.

Next, the operation of generating a G signal when outputting a still image will be described.

The signal sampled by the above method is input to the luminance matrix circuit 4202 and the RGB matrix circuit 4204. Luminance matrix circuit 42
02 and the RGB matrix circuit 4204 generate y, r, g, and b signals according to the arithmetic expression of (26). The signal generated by the RGB matrix circuit 4204 is input to the white balance circuit 4205, subjected to the white balance correction described above, and then the Yc matrix circuit 4205.
It is input to 206. The Yc matrix circuit 4206 is
A signal yg having only the G signal component is generated by the matrix calculation formula shown below.

Yg = 0 * r + 1 * g + 0 * b (29) From the signal obtained by the above operation, the G signal can be obtained by the following arithmetic expression.

[0122] Here, ygl and gl are the low frequency components of the yg and g signals, respectively.

Next, the operation for generating the B signal when outputting a still image will be described.

The signal sampled by the above method is input to the luminance matrix circuit 4202 and the RGB matrix circuit 4204. Luminance matrix circuit 42
02 and the RGB matrix circuit 4204 generate y, r, g, and b signals according to the arithmetic expression of (26). The signal generated by the RGB matrix circuit 4204 is input to the white balance circuit 4205, subjected to the white balance correction described above, and then the Yc matrix circuit 4205.
It is input to 206. The Yc matrix circuit 4206 is
A signal yb having only the B signal component is generated by the matrix calculation formula shown below.

Yb = 0 * r + 0 * g + 1 * b (31) From the signal obtained by the above operation, the B signal can be obtained by the following arithmetic expression.

[0126] Here, ybl and bl are low frequency components of the yb and b signals, respectively.

As described above, the signal processing circuit 4114 is
When generating the RGB signal, the R signal, the G signal, and the B signal must be generated individually. Therefore,
The memory 4108 outputs the same signal three times, and the first time outputs R
Signal generation, G signal generation for the second time, and RGB signals are generated in a frame sequential manner.

The above is an embodiment in which a still image is recorded without damaging the frame information (referred to as Full mode). Next, although the image quality is deteriorated, the still image is recorded with a small memory capacity (Economy). An embodiment will be described below.

The image pickup device 4104 outputs a signal by the above-mentioned general pixel mixture reading. Image sensor 41
The signal shown in FIG. 3 which is output from 04 is the above-mentioned Ful.
It is recorded in the memory 4108 in the same manner as in the 1-mode shooting. However, the signal recorded by this method has a different signal format from that in the full mode. Therefore, RGB
When generating the signal, an identification signal indicating whether the signal is recorded in the Full mode or the Economy mode is necessary. This identification signal is recorded together with information such as white balance.

Next, the operation of outputting the signal recorded in the Economy mode will be described.

The signal recorded in the memory 4108 is Fu
Similarly to the RGB signal output in the 11 mode, the signal processing circuit 41
An RGB signal is generated based on information such as white balance, which is input to 14. However, since the format of the signal is different from that in the Full mode as described above,
It is necessary to change the matrix coefficient of the RGB matrix circuit 4204. Since the signal format at this time is the same as the signal format at the time of moving image, the above (20) (2
1) (25) (26) (27) (28) (29) (3
The R signal, the G signal, and the B signal may be generated by the method described above by the matrix calculation shown in the equation (0). Signal processing circuit 4
The R, G, and B signals generated in 114 are input to the signal interpolation circuit 4116 in each signal processing circuit 4114,
The signal interpolation circuit 4116 interpolates the signals and halves the number of signals in the horizontal direction and outputs.

The signal interpolation will be described below.

FIG. 14 shows a concrete example of the signal interpolation circuit 4116. Since there is no need for signal interpolation during the above-described moving image shooting and Full mode shooting, the interpolation coefficient input K
1 is set to 1 and interpolation coefficient input K2 is set to 0, and the signal is output without performing signal interpolation.

In the above-mentioned Economy mode,
Signal interpolation is performed to reduce the number of horizontal signals to 1/2.

At this time, since the image pickup device 4104 outputs the signal by the pixel mixing method, the still image 1 to be recorded in the memory is different from the recording method in the Full mode described above.
The number of signals per sheet is halved. Therefore, it is possible to record twice as many still images.

Full mode, Economy described above
For selecting two types of still image recording modes, press the Ful
The l / Economy changeover switch 4119 is used. Full / Economy selector switch 411
9 selects the matrix calculation formula, the driving method of the image sensor 4104, and the memory 410.
8 driving method and the like are selected. Also, Full / Econ
In response to the operation of the omy changeover switch 4119, the viewfinder 4118 displays which recording method is selected and can record as many still images as the currently selected recording method. Is displayed.

Another embodiment of the present invention will be described below with reference to the drawings.

FIG. 12 is a block diagram of an image pickup apparatus according to another embodiment of the present invention.

In the figure, the difference from the above-mentioned embodiment is that
That is, the configuration is such that the output signal of the signal processing circuit 251 is recorded in the memory 254. In the present embodiment, the operation of shooting a moving image is exactly the same as that of the above-described embodiment, so the operation when recording a still image in the Full mode will be described.

Similar to the above-mentioned embodiment, the image pickup device 104 outputs a signal by independent reading. Image sensor 104
The signal output from is converted into a digital signal by the A / D converter 107 and input to the memory 254. The memory 254 records a signal for one still image and outputs the signal to the camera signal processing circuit 252 in the signal processing circuit 251 via the selection circuit 113. The camera signal processing circuit 252 outputs the input signal as a through signal by using one of the luminance signal and color difference signal generation paths. For example, the sampling circuit 4201 outputs the input signal as it is to S1, and the luminance matrix circuit 4202 outputs S1.
The signal obtained by multiplying 1 by 1 and the signal obtained by multiplying S2 to S4 by 0 are added, and the luminance signal processing circuit 4203 outputs the output signal of the luminance matrix circuit 4202 as it is. The signal output from the camera signal processing circuit 252 is the signal interpolation circuit 25.
3 is input, but the signal is output without performing the interpolation as described above. The signal output from the signal processing circuit 251 is recorded in the memory 254.

The format of the signal recorded in the memory 254 by the above method is Full in the above-mentioned embodiment.
It is exactly the same as the mode, and the operation when outputting a still image is
This is similar to the above-mentioned embodiment.

Next, a method of recording a still image with a smaller memory capacity (Economy mode), although the image quality is deteriorated, will be described below.

The image pickup device 104 outputs a signal by the above-mentioned general pixel mixture reading. Image sensor 10
The signal output from No. 4 is temporarily recorded in the memory 254 as in Full mode shooting, and the signal is output to the signal processing circuit 251. As for the signal input to the signal processing circuit 251, the input signal is output to the signal interpolation circuit 253 as it is, as in the case of the full mode shooting described above. The signal interpolation circuit 253 performs signal interpolation on the input signal. However, in this case, since the adjacent signal components of the input signal are different, signal interpolation by the method performed in the Economy mode in the above-described embodiment cannot be performed. Figure 38
Is a specific configuration example of the signal interpolation circuit 253 in the present embodiment. Gr + Cy, Mg + Ye ... or M
The signals input in the order of g + Cy, Gr + Ye ...
In the separation circuit 3801 Gr + Cy and Mg + Ye or M
The signals are separated into g + Cy and Gr + Ye, and the respective signals are interpolated by the two-system interpolation circuits. The signal interpolated by the signal interpolation circuit 253 is recorded in the memory 254.

The format of the signal recorded in the memory 254 by the above method is Econ in the above-mentioned embodiment.
The number of data in the horizontal direction at the time of recording in the omy mode is halved. Therefore, as the matrix coefficient for generating the RGB signal, the matrix coefficient used in the Economy mode in the above-described embodiment can be used, and the operation at the time of outputting a still image is similar to that in the Economy mode in the above-described embodiment.

At this time, since the signal recorded in the memory 254 is output from the image pickup device 104 by the pixel mixing method, the number of data in the vertical direction is halved, and the signal interpolation circuit 253 further sets the horizontal signal. Since the number of signals in the direction is halved, it means that the signal has been compressed to 1/4 as compared with the recording method in the Full mode described above. According to this method,
It is possible to record four times as many still images as in Full mode recording.

Full mode, Economy described above
A Full / Economy selector switch 117 is used to select the mode. Either one of the recording methods described above is selected according to the mode selected by the Full / Economy changeover switch 117. In addition, Fu
In response to the operation of the ll / Economy changeover switch 117, the viewfinder 116 displays which recording method is selected, and also records the number of still images remaining in the currently selected recording method. Show what you can do.

The data format for outputting the generated RGB signals will be described below.

In the signal processing circuit shown in the above-mentioned embodiment, as shown in FIG. 44 (a), the R signal, the G signal, and the B signal generated in the frame sequential manner have a data structure of a plurality of bits (in the depth direction). It is output as parallel data of 8 bits, for example. It is also possible to output the signal output as 1-bit serial data as shown in FIG.
This can be realized by outputting the signals recorded in 1 bit by 1 bit and generating the R signal, the G signal, and the B signal by 1 bit.

[0149]

According to the present invention, a detector for detecting illuminance, color temperature, etc. is not required, and a still image video signal can be generated by using a general image pickup device. Can be supplied.

According to the present invention, since a video signal having the same spatial sampling pitch in the horizontal and vertical directions can be generated by using a recording means having a small storage capacity and a general image pickup device, an inexpensive video input means can be provided. can do.

According to the present invention, since a still image RGB signal can be generated by using a recording means such as a memory and a general image pickup device, an inexpensive image input means can be supplied.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of an image sensor.

FIG. 3 is a drive pulse of an image sensor and its output.

FIG. 4 is a drive pulse of an image sensor and its output.

FIG. 5 is a configuration diagram of a signal processing circuit.

FIG. 6 is a specific example of a matrix circuit.

FIG. 7 is a specific example of signal processing when capturing a moving image.

FIG. 8 is a specific example of signal processing when capturing a moving image.

FIG. 9 is a specific example of signal processing when capturing a still image.

FIG. 10 is a specific example of signal processing when capturing a still image.

FIG. 11 is a specific example of a sampling circuit.

FIG. 12 is a block diagram showing another embodiment of the present invention.

13 is an explanatory diagram of the embodiment shown in FIG.

14 is an explanatory diagram of the embodiment shown in FIG.

FIG. 15 is a configuration diagram of a shutter control circuit.

FIG. 16 is a graph showing the exposure amount with respect to the aperture value of the shutter.

FIG. 17 is a graph showing the exposure amount with respect to the aperture value of the shutter.

FIG. 18 is a graph showing the exposure amount with respect to the aperture value of the shutter.

FIG. 19 is a graph showing the exposure amount with respect to the aperture value of the shutter.

FIG. 20 is a graph showing the exposure amount with respect to the aperture value of the shutter.

FIG. 21 is a graph showing the exposure amount with respect to the aperture value of the shutter.

FIG. 22 is a configuration diagram of a white balance circuit.

FIG. 23 is a specific example of signal output.

FIG. 24 is a specific example of signal output.

FIG. 25 is a specific example of signal output.

FIG. 26 is a block diagram showing an embodiment of the present invention.

FIG. 27 is a configuration diagram of an image sensor according to an example of the present invention.

FIG. 28 is a spatial distribution diagram of signals according to the embodiment of the present invention.

FIG. 29 is a timing chart of the output signal of the image sensor according to the example of the present invention.

FIG. 30 is a spatial distribution diagram of signals according to an embodiment of the present invention.

FIG. 31 is a signal format diagram at the time of independent reading according to the embodiment of the present invention.

FIG. 32 is a diagram showing a nonlinear input / output characteristic according to the example of the present invention.

FIG. 33 is a diagram showing a nonlinear input / output characteristic according to the example of the present invention.

FIG. 34 is a signal format diagram at the time of pixel mixture reading according to the embodiment of the present invention.

FIG. 35 is a spatial distribution diagram of signals according to an embodiment of the present invention.

FIG. 36 is a block diagram showing a configuration of an image pickup apparatus according to an embodiment of the present invention.

FIG. 37 is a spatial distribution diagram of signals according to the embodiment of the present invention.

FIG. 38 is a block diagram showing a configuration of a signal interpolation circuit according to the embodiment of the present invention.

FIG. 39 is a signal format diagram at the time of pixel mixture reading according to the embodiment of the present invention.

FIG. 40 is a spatial distribution diagram of signals according to an embodiment of the present invention.

FIG. 41 is a block diagram showing an example of the present invention.

FIG. 42 is a block diagram showing a configuration of a camera signal processing circuit according to an embodiment of the present invention.

FIG. 43 is a block diagram showing a configuration of a luminance matrix circuit according to an example of the present invention.

FIG. 44 is a diagram showing a signal output method according to an embodiment of the present invention.

[Explanation of symbols]

101 ... Lens, 102 ... Shutter, 103 ... Shutter control circuit, 104 ... Image sensor, 105 ... Drive circuit, 106 ... Amplifier, 107 ... A / D converter, 108 ... Memory, 109 ... Memory control circuit, 110 ... Recording / Reproduction control circuit, 111 ... Shutter button, 112 ... Reproduction button, 113 ... Selection circuit, 114 ... Signal processing circuit, 115 ... Signal processing control circuit, 116 ... Viewfinder, 117 ... Full / Economy switch, 201 ... Photodiode, 202 ... Vertical CCD, 203 ... Horizontal CCD, 211 ... Sampling circuit, 212 ... Luminance matrix circuit, 213 ... Luminance signal processing circuit, 214 ... RGB matrix, 215 ... White balance circuit, 216 ... Color difference matrix, 221 ... Multiplier, 222 ... Multiplier, 22 3 ... Multiplier, 224 ... Multiplier, 225 ... Adder, 226 ... Matrix-converted output, 241 ... Sample-hold circuit, 242 ... Sample-hold circuit, 251 ... Signal processing circuit, 252 ... Camera signal processing circuit, 253 ... Signal Interpolation circuit, 401 ... Delay circuit, 402 ... Multiplier, 403 ... Multiplier, 404 ... Adder, 300 ... Detection circuit, 301 ... Arithmetic circuit, 302 ... Shutter drive circuit, 303 ... R-amplifier, 304 ... B-amplifier , 305 ... Gain control circuit, 306 ... RY detection circuit, 307 ... BY detection circuit, 308 ... Sequencing circuit, 2601 ... Lens, 2602 ... Shutter, 2603 ... Shutter control circuit, 2604 ... Imaging element, 2605 ... Drive circuit, 2606 ... Amplifier, 2607 ... A / D converter, 2608 ... Memory, 2609 ... Buff Memory, 2610 ... Main memory, 2611 ... Memory control circuit, 2612 ... Recording / reproduction control circuit, 2613 ... Selection circuit, 2614 ... Signal processing circuit, 2615 ... Camera signal processing circuit, 2616 ... Signal interpolation circuit, 2617 ... Signal processing control Circuit, 2618 ... Shutter button, 2619 ... Full / Economy switching button, 2620 ... Display device, 2701 ... Photodiode, 2702 ... Vertical CCD, 2703 ... Horizontal CCD, 3601 ... Lens, 3602 ... Shutter, 3603 ... Shutter control circuit, 3604 ... Image sensor, 3605 ... Driving circuit, 3606 ... Amplifier, 3607 ... A / D converter, 3608 ... Memory, 3609 ... Buffer memory, 3610 ... Main memory, 3611 ... Memory control circuit, 3612 ... Recording / playback control times Reference numeral 3613 ... Selection circuit, 3614 ... Signal processing circuit, 3615 ... Camera signal processing circuit, 3616 ... Signal interpolation circuit, 3617 ... Signal processing control circuit, 3618 ... Shutter button, 3619 ... Full / Economy switching button, 3620 ... Display device , 3801 ... Separation circuit, 3802 ... Delay circuit, 3803 ... Delay circuit, 3804 ... Multiplier, 3805 ... Multiplier, 3806 ... Multiplier, 3807 ... Multiplier, 3808 ... Adder, 3809 ... Adder, 3810 ... Multiplexer, 4101 ... Lens, 4102 ... Shutter, 4103 ... Shutter control circuit, 4104 ... Image pickup element, 4105 ... Drive circuit, 4106 ... Amplifier, 4107 ... A / D converter, 4108 ... Memory, 4109 ... Memory control circuit, 4110 ... Recording / Reproduction control circuit, 41 1 ... Shutter button, 4112 ... Play button, 4113 ... Selection circuit, 4114 ... Signal processing circuit, 4115 ... Camera signal processing circuit, 4116 ... Signal interpolation circuit, 4117 ... Signal processing control circuit, 4118 ... Viewfinder, 4119 ... Full / Economy changeover switch, 4201 ... Sampling circuit, 4202 ... Luminance matrix circuit, 4203 ... Luminance signal processing circuit, 4204 ... RGB matrix circuit, 4205 ... White balance circuit, 4206 ... Yc matrix circuit, 4207 ... Color difference matrix circuit, 4301 ... Amplifier, 4302 ... Matrix circuit, 4303 ... Subtractor, 4304 ... Low pass filter, 4305 ... Adder.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Uemura Sequentially, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stocks, Institute of Image Media Research, Hitachi, Ltd. (72) Hiroyuki Komatsu 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Hitachi Image Information System Co., Ltd. (72) Inventor Toshiro Kinugasa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock Company Hitachi Media Media Research Laboratories

Claims (21)

[Claims] 1. A light quantity limiting means capable of blocking incident light, a pixel for photoelectrically converting the incident light, an image pickup means for outputting a signal of the pixel as a digital video signal, and a digital video signal of a predetermined format. A signal processing circuit for
A recording means for recording a digital video signal of a still image output from the image pickup means or the signal processing circuit,
The light amount limiting means blocks the incident light after limiting the incident light amount to a predetermined amount, and the image pickup means outputs a digital video signal of a moving image when the incident light amount is limited to the predetermined amount by the light amount limiting means, After shutting off, the still image digital video signal is output, and the signal processing circuit performs different signal processing when the moving image digital video signal is supplied and when the still image digital video signal is supplied. Still image recording digital camera characterized by. 2. The signal processing circuit has a matrix circuit for generating a luminance signal or a chrominance signal, and the signal processing circuit is provided when the digital video signal of the moving image is supplied and when the digital video signal of the still image is supplied. The still image recording digital camera according to claim 1, wherein the coefficients of the matrix circuit are switched. 3. A light amount limiting means capable of limiting an incident light amount, a pixel for photoelectrically converting the incident light for a predetermined exposure time, an image pickup means for outputting a signal of the pixel as a digital video signal, and a predetermined format. It has a signal processing circuit for generating a digital video signal and a recording means for recording a digital video signal of a still image output from the image pickup means or the signal processing circuit, and the light quantity limiting means has a predetermined light quantity. When the image pickup means photoelectrically converts the incident light with a limited exposure time for a predetermined exposure time to output a moving picture digital video signal, and the signal processing circuit performs predetermined signal processing on the moving picture digital video signal. Of the limiting amount, the exposure time, or the signal processing information is recorded in the recording means or a recording means different from the recording means,
The time until the incident light is blocked by the light amount limiting means, or the exposure time of the digital video signal of the still image output from the image pickup means after the incident light is blocked by the light amount limiting means, or the signal processing circuit. A still image recording digital camera, characterized in that signal processing applied to the digital video signal of the still image is controlled by information recorded in the recording means or a recording means different from the recording means. 4. The signal processing circuit has a white balance circuit including a variable gain circuit, and the gain of the variable gain circuit is recorded in the recording means or a recording means different from the recording means. Item 3. A still image recording digital camera according to item 3. 5. A light quantity limiting means capable of blocking incident light, a pixel for photoelectrically converting the incident light, an image pickup means for outputting a signal of the pixel as a digital video signal, and a digital video signal of a predetermined format. A signal processing circuit for
A recording means for recording a digital video signal of a still image output from the image pickup means or the signal processing circuit,
The light amount limiting means blocks the incident light after limiting the incident light amount to a predetermined amount, and the image pickup means outputs a digital video signal of a moving image when the incident light amount is limited to the predetermined amount by the light amount limiting means, After the interruption, a still image digital video signal is output, and the signal processing circuit outputs a luminance signal and a color difference signal generated from the supplied still image digital video signal, or an RGB signal, or the supplied still image signal. A still image recording digital camera characterized by outputting a digital video signal as a parallel or serial digital signal. 6. The light quantity limiting means photoelectrically converts incident light whose light quantity is limited by a predetermined limit quantity for a predetermined exposure time to output a digital video signal of a moving image, and the signal processing circuit After the information on any one of the limit amount, the exposure time, or the signal processing when the digital video signal of the moving image is subjected to the predetermined signal processing falls within a predetermined fluctuation range over a plurality of fields, or 3. The display means for displaying that the still picture digital video signal can be recorded in the recording means after the recording means finishes recording the still picture digital video signal. The still image recording digital camera described in 3, 4, or 5. 7. The light quantity limiting means photoelectrically converts the incident light whose light quantity is limited by a predetermined limit quantity for a predetermined exposure time to output a digital video signal of a moving image, and the signal processing circuit The information of any one of the limit amount, the exposure time, and the signal processing when the digital video signal of the moving image is subjected to the predetermined signal processing is within a predetermined fluctuation range over a plurality of fields, or the recording means. Until you finish recording the digital video signal of the still image,
6. The still image recording digital camera according to claim 1, further comprising display means for displaying in the recording means that a digital video signal of a still image cannot be recorded. 8. A movable part such as a button and a recording / reproducing control circuit, and by moving the movable part, a recording start control signal is output from the recording / reproducing control circuit, and a digital image of a still image is displayed on the recording means. A still image recording digital camera for starting signal recording, wherein the image pickup device photoelectrically converts incident light whose light amount is limited by a predetermined amount by the light amount limiting device for a predetermined exposure time. When a signal is output and the signal processing circuit is performing predetermined signal processing on the digital video signal of the moving image, information on any one of the limiting amount, the exposure time and the signal processing is changed in predetermined over a plurality of fields. 2. The movable amount of the movable part is limited until it falls within the range or until recording of a digital video signal of a still image in the recording means is completed. , Still image recording digital camera according to 3, 4 or 5. 9. A light amount limiting means capable of blocking incident light, a pixel for photoelectrically converting the incident light, an image pickup means for outputting a signal of the pixel as a digital video signal, and a digital video signal of a predetermined format. A signal processing circuit for
Recording means for recording a digital video signal output from the image pickup means or the signal processing circuit, the image pickup means outputs a still image digital video signal after blocking the incident light by the light amount limiting means, A still image recording digital camera, wherein the signal processing circuit interpolates and interpolates a digital image signal of a still image supplied from the image pickup means or the recording means. 10. The image pickup means has pixels arranged at intervals in a horizontal direction Px and a vertical direction Py (Px ≠ Py), and the signal processing circuit horizontally receives the supplied digital video signal of a still image. 10. The still image recording digital camera according to claim 9, wherein the interpolation is performed to generate N * Px / Py digital video signals from N digital video signals in the horizontal direction. 11. The image pickup means has pixels arranged at intervals in a horizontal direction Px and a vertical direction Py (Px ≠ Py), and the signal processing circuit internally receives the supplied digital video signal of a still image in the vertical direction. The still image recording digital camera according to claim 9, wherein the interpolation is performed to generate approximately M × Py / Px digital video signals from M digital video signals in the vertical direction. 12. A light quantity limiting means capable of blocking incident light, and a plurality of types of pixels for photoelectrically converting incident light with any one of a plurality of types of spectral characteristics, and a signal of the pixel is digitally provided. Image pickup means for outputting as a video signal, a signal processing circuit for generating a digital video signal of a predetermined format, and recording means for recording the digital video signal output from the image pickup means or the signal processing circuit are included. The means outputs the signals of the pixels as independent pixel signals after blocking the incident light by the light quantity limiting means, the recording means records the independent pixel signals, and the signal processing circuit causes the recording means to write in the recording means. A still image recording digital camera characterized by generating a digital video signal of a predetermined format from the recorded independent pixel signals. 13. A light quantity limiting means capable of blocking incident light, and a plurality of types of pixels for photoelectrically converting incident light with any one of a plurality of types of spectral characteristics, and a signal of the pixel is digitally converted. Imaging means for outputting as a video signal, a signal processing circuit for generating a digital video signal of a predetermined format, and recording means for recording the digital video signal output from the imaging means or the signal processing circuit,
A recording / reproducing control circuit, which outputs the signals of the pixels from the imaging means as independent pixel signals after blocking the incident light by the light amount limiting means, or It is controlled whether the signals are mixed and output as a mixed pixel signal, the recording means records either the independent pixel signal or the mixed pixel signal, and the signal processing circuit records in the recording means. A still image recording digital camera characterized by generating a digital video signal of a predetermined format from an independent pixel signal or the mixed pixel signal. 14. The still image according to claim 13, wherein an identification signal for identifying whether an independent pixel signal or a mixed pixel signal is recorded is recorded in the recording means. Recording digital camera. 15. The still image recording digital camera according to claim 13 or 14, further comprising display means for displaying which pixel signal, an independent pixel signal or a mixed pixel signal, is to be recorded. 16. A still image recording digital camera according to claim 13, 14 or 15, further comprising display means for displaying the number of still images that can be recorded in said recording means. 17. A circuit having a non-linear input / output characteristic is arranged in the image pickup means or a signal transmission path from the image pickup means to the recording means.
A still image recording digital camera described in 2, 13, 14, 15 or 16. 18. The recording means has a buffer memory and a main memory, and the still picture digital video signal is output from the buffer memory at an operating frequency lower than an operating frequency for writing the still picture digital video signal in the buffer memory. Is read out and written in the main memory.
The still image recording digital camera described in 4, 15, 16 or 17. 19. A light quantity limiting means capable of blocking incident light, an image pickup means having a pixel for photoelectrically converting the incident light, outputting a signal of the pixel as a digital video signal, and generating a digital video signal of a predetermined format. Signal processing circuit and a recording means for recording a digital video signal output from the image pickup means or the signal processing circuit. The image pickup means cuts off incident light by the light amount limiting means and then digitalizes a still image. A still image recording digital camera, which outputs an image signal, and wherein the signal processing circuit generates an RGB signal from a still image digital image signal supplied from the image pickup means or the recording means. 20. A light amount limiting means capable of blocking incident light, an image pickup means having a pixel for photoelectrically converting the incident light, outputting a signal of the pixel as a digital video signal, and generating a digital video signal of a predetermined format. Signal processing circuit and a recording means for recording a digital video signal output from the image pickup means or the signal processing circuit. The image pickup means cuts off incident light by the light amount limiting means and then digitalizes a still image. A still image recording digital camera, which outputs a video signal, and wherein the signal processing circuit generates RGB signals in a frame sequential manner from a digital video signal of a still image supplied a plurality of times from the image pickup means or the recording means. 21. The signal processing circuit comprises a first brightness matrix circuit for generating a brightness signal and an RG for generating an RGB signal.
It has a B matrix circuit and a second brightness matrix circuit for generating a low band brightness signal from the RGB signals output from the RGB matrix circuit, and when the digital video signal recorded in the recording means is supplied, the above described 20. The second luminance matrix circuit outputs any one signal of the R signal, the G signal and the B signal, and combines the signal with the luminance signal output from the first luminance matrix circuit. The still image recording digital camera described in 20.