KR0135895Y1 - Capacitor type package - Google Patents
Capacitor type package Download PDFInfo
- Publication number
- KR0135895Y1 KR0135895Y1 KR2019950004630U KR19950004630U KR0135895Y1 KR 0135895 Y1 KR0135895 Y1 KR 0135895Y1 KR 2019950004630 U KR2019950004630 U KR 2019950004630U KR 19950004630 U KR19950004630 U KR 19950004630U KR 0135895 Y1 KR0135895 Y1 KR 0135895Y1
- Authority
- KR
- South Korea
- Prior art keywords
- capacitor
- package
- chip
- paddle
- insulating layer
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 고안은 반도체 패키지에서, 리드프레임의 패들에 캐패시터 후막 패턴을 적층시키고, 그 위에 칩을 어태치시켜 패키지내에 바이패스 캐패시터가 일체로 내장된 것을 특징으로하는 캐패시터 내장 패키지이며, 패키지내에 칩과 캐패시터가 일체화되어 노이즈 바이패스 기능을 극대화 시킬수 있고, 모듈 조립시에는 별도의 바이패스 캐패시터가 필요치않아 회로설계에 유리하며 생산성을 향상시킨다.The present invention is a package with a capacitor, characterized in that by stacking a capacitor thick film pattern on the paddle of the lead frame in the semiconductor package, by attaching a chip thereon, the bypass capacitor is integrated in the package, the chip and capacitor in the package Is integrated to maximize the noise bypass function, and does not require a separate bypass capacitor when assembling the module, which is advantageous for circuit design and improves productivity.
Description
제1도는 본 고안의 구조도.1 is a structural diagram of the present invention.
제2도는 본 고안의 와이어본딩된 상태를 나타낸 요부확대평면도이다.Figure 2 is an enlarged plan view of the main portion showing a wire bonded state of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 칩 2 : 패들1: chip 2: paddle
10 : 캐패시터부 11 : 절연층10 capacitor portion 11 insulating layer
12 : 전도층 13 : 유전층12 conductive layer 13 dielectric layer
14 : 절연층14: insulation layer
본 고안은 캐패시터 내장 반도체 패키지에 관한 것으로, 특히 리드프레임 패들에 캐패시터를 페턴형성한 상태에서 칩을 어태치시켜 제조한 바이패스캐패시터 내장 패키지에 관한 것이다.The present invention relates to a semiconductor package with a built-in capacitor, and more particularly, to a bypass capacitor built-in package manufactured by attaching a chip in a state in which a capacitor is formed on a lead frame paddle.
일반적으로 반도체 메모리 모듈 및 메모리카드 설계시 시스템 및 회로에서 발생되는 노이즈로 인해 디램 반도체 패키지의 실리콘 정션(silicon junction) 파괴를 방지하고자, 패키지의 전원단(Vcc)과 접지단에 바이패스용 캐패시터를 붙여 사용한다. 예를들면 1메가 x 9비트의 싱글인라인 메모리 모듈(SIMM)인 경우 SOJ(Small Outline J-bend)형의 1 메가 디램 패키지 하단부에 칩캐패시터(보통 0.22μF)를 장착하고, TSOP(Thin Small Outline Package) 중간리드와 리드사이에 장착한다. 따라서 회로의 집적도 및 방법에 따라 캐패시터가 인접 설치할수 없는 경우 노이즈 바이패스 효과가 감소되어 패키지의 특성 유지가 어려운 문제점이 있다.In general, in order to prevent silicon junction breakdown of the DRAM semiconductor package due to noise generated in systems and circuits when designing a semiconductor memory module and a memory card, a bypass capacitor is provided at a power supply terminal (Vcc) and a ground terminal of the package. I put it and use it. For example, a 1 mega x 9 bit single inline memory module (SIMM) is equipped with a chip capacitor (typically 0.22 μF) on the bottom of a small outline J-bend (SOJ) type 1 mega DRAM package, and TSOP (Thin Small Outline). Package) Install between intermediate lead and lead. Therefore, when the capacitors cannot be installed adjacently according to the degree of integration and the method of the circuit, the noise bypass effect is reduced, which makes it difficult to maintain the characteristics of the package.
본 고안은 이를 해결코자 하는것으로, 칩어태치용 리드프레임 패들에 캐패시터용 후막을 일체로 형성하여 별도의 캐패시터가 필요없도록함을 특징으로 한다.The present invention is to solve this problem, it is characterized in that the capacitor is formed on the lead frame paddle for chip attach integrally to form a thick film, so that no separate capacitor is required.
즉, 본 고안은 반도체 패키지에서, 리드프레임의 패들에 캐패시터 후막 패턴을 적층시키고, 그 위에 칩을 어태치시켜 패키지내에 바이패스 캐패시터가 일체로 내장된 것을 특징으로하는 캐패시터 내장 패키지를 제공하려는 것이다.In other words, the present invention is to provide a capacitor-embedded package, characterized in that by stacking a capacitor thick film pattern on the paddle of the lead frame in the semiconductor package, by attaching a chip thereon, the bypass capacitor is integrated in the package.
이하 도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the drawings will be described in detail.
제1도는 본 고안의 단면도이고, 제2도는 본 고안의 요부 평면도로, 칩(1) 어태치용 패들(2)에 후막형 캐피시터부(10)가 일체로 인쇄되고, 캐패시터부(10)와는 절연층(11)을 개재하여 칩(1)이 어태치된다.FIG. 1 is a cross-sectional view of the present invention, and FIG. 2 is a plan view of main parts of the present invention, in which a thick film type capacitor portion 10 is integrally printed on the paddle 2 for attaching the chip 1, and is insulated from the capacitor portion 10. FIG. The chip 1 is attached via the layer 11.
상기 캐패시터부(10)는 패들(2)의 양단에 전도층(12)이, 중앙에는 전도층(12)과 연결되는 유전층(13)이 형성된다.The capacitor part 10 has a conductive layer 12 formed at both ends of the paddle 2 and a dielectric layer 13 connected to the conductive layer 12 at the center thereof.
상기 전도층(12)은 칩(1)의 전원 전도패드와 와이어(3)가 본딩가능토록 패들(2) 모서리에 일부가 노출되도록함이 바람직하다.The conductive layer 12 preferably exposes a part of the power conducting pad and the wire 3 of the chip 1 to the edge of the paddle 2 so that the wire 3 can be bonded.
이와같은 구성의 본 고안을 제조할때에는 리드프레임의 패들(2)에 하이브리드 후막 인쇄기술을 이용하여 절연 페이스트(Insulation Paste)를 도포 및 경화시켜 절연층(14)을 형성한다.In manufacturing the present invention having such a configuration, the insulation layer 14 is formed by applying and curing an insulation paste to the paddle 2 of the lead frame using a hybrid thick film printing technique.
이때의 경화조건은 125℃에서 20분 처리함이 바람직하다.The curing conditions at this time is preferably treated for 20 minutes at 125 ℃.
이어 절연층(14) 위의 양단부에 일정폭의 전도페이스트(Conductor Paste)를 이용하여 캐패시터의 전도층(12)을 이루게 한다.Subsequently, a conductive paste 12 having a predetermined width is used at both ends of the insulating layer 14 to form the conductive layer 12 of the capacitor.
이때 전도페이스트의 경화조건은 대략 125℃에서 20분 처리함이 좋으며, 전도층(12)의 모양 크기 폭 등은 원하는 용량을 수득가능토록 설정하면 된다.In this case, the curing conditions of the conductive paste may be treated at about 125 ° C. for 20 minutes, and the shape, size, width, and the like of the conductive layer 12 may be set to obtain a desired capacity.
이어 유전페이스트(Dielectric Paste)를 상기 전도층(12) 사이에서 끝부분이 겹치도록 도포하여 역시 대략125℃에서 20분 처리하여 유전층(13)을 경화시킨다.Subsequently, a dielectric paste is applied so that the ends overlap between the conductive layers 12, and the dielectric layer 13 is also treated at about 125 ° C. for 20 minutes to cure the dielectric layer 13.
최종적으로 오버코팅용 페이스트를 이용하여 본딩할 부위를 제외하고 절연층(11)을 이루게 하여 캐패시터부(10)의 제조를 완료한다.Finally, the insulating layer 11 is formed except for the portion to be bonded using the overcoating paste to complete the manufacture of the capacitor part 10.
이어 칩(1)을 어태치하고 와이어(3)본딩하는 공정은 동일하므로 이후의 과정은 생략한다.Subsequently, the process of attaching the chip 1 and bonding the wire 3 is the same, and a subsequent process is omitted.
결국 본고안은 패들(2)에 캐패시터부(10)가 일체로 되므로, 칩(1) 어태치 후 칩(1)의 전원 전도패드와 와이어본딩하면, 칩(1)과 최단거리에 바이패스 캐패시터(캐패시터부(10))가 있게되어 노이즈를 제거할수 있게된다.As a result, since the capacitor unit 10 is integrated with the paddle 2, the wire capacitor is bonded to the power conduction pad of the chip 1 after attaching the chip 1. (Capacitor section 10) is provided so that noise can be removed.
이상과 같이 본원고안은 패키지내에 칩과 캐패시터가 일체화되어 노이즈 바이패스 기능을 극대화시킬수 있고, 모듈 조립시에는 별도의 바이패스 캐패시터가 필요치않아 회로설계에 유리하며 생산성을 향상시킨다.As described above, the present application can maximize the noise bypass function by integrating a chip and a capacitor in a package, and does not require a separate bypass capacitor when assembling a module, which is advantageous for circuit design and improves productivity.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019950004630U KR0135895Y1 (en) | 1995-03-16 | 1995-03-16 | Capacitor type package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019950004630U KR0135895Y1 (en) | 1995-03-16 | 1995-03-16 | Capacitor type package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960032762U KR960032762U (en) | 1996-10-24 |
| KR0135895Y1 true KR0135895Y1 (en) | 1999-02-18 |
Family
ID=19409360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019950004630U KR0135895Y1 (en) | 1995-03-16 | 1995-03-16 | Capacitor type package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0135895Y1 (en) |
-
1995
- 1995-03-16 KR KR2019950004630U patent/KR0135895Y1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR960032762U (en) | 1996-10-24 |
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