KR0134288B1 - Apparatus for transmitting data of the aal-3/4 layer - Google Patents

Abstract

The present invention relates to a data transfer device of the AAL-3 / 4 layer, which is suitable for lowering the price of the device for data transfer in the AAL-3 / 4 layer. In the past, the AAL layer applies data on the system bus. First-In First-Out (FIFO) is used for receiving. Such FIFO is expensive and difficult to implement. However, in the present invention, the FIFO is enabled by the chip select signal CS of the address decoder 10. After receiving and storing data from the bus, it is enabled by another chip select signal CS1 of the AAL-3 / 4 layer 40 to the increased address signal of the counter 20 as the read signal RD increases. Accordingly, by using the RAM in the storage unit 30 that outputs the address data, the cost is lowered and can be easily implemented, thereby improving the shortcomings.

Description

AAL-3 / 4 layer data transfer device

Figure is a block diagram showing an embodiment of a data delivery device of the AAL-3 / 4 layer according to the present invention.

* Description of the symbols for the main parts of the drawings *

10: address decoder, 20: counter,

30: storage, 40: AAL-3 / 4 layer

TECHNICAL FIELD The present invention relates to an ATM Adaption Layer (AAL) -3/4 layer, and in particular, an AAL-3 / 4 layer suitable for lowering the price of a device for data delivery in the AAL-3 / 4 layer. To a data transfer device. The AAL layer cuts the Convergence Sublayer (CS) and protocol data units, which make the user service information of the upper layer into Protocol Data Units (PDUs) and transfers and recombines to form user information intervals of ATM cells. Segmentation And Reassembly (SAR) sublayer, which provides Class C and D services from ATM Adaption Layer-Service Access Point (AAL-SAP) to ATM-SAP, Has the ability to deliver in a connected manner.

Here, the definition of each term is briefly described as follows.

Asynchronous Transfer Mode (ATM): A communication method for implementing a broadband integrated information network (BISDN), where asynchronous transfer mode is a special type of packet type using Asynchronous Time Division Multiplexing (ATDM). It is a delivery method.

ATM cell (Asynchronous Transfer Mode cell): In a broadband integrated information network (BISDN), information is transmitted by a continuous flow of packets having a constant size. The fixed size packets are called ATM cells, and the size of the ATM cell is It is 53 bytes, which is divided into a 5-byte header and 48 bytes of payload space.

In this regard, the conventional AAL layer receives data from the system bus by using first-in first-out (FIFO) and writes the data.

However, in this conventional technique, the AAL layer uses a FIFO when data is received from the system bus. Such a FIFO is expensive and difficult to implement.

The present invention has been made to solve the above-mentioned drawbacks, and provides an AAL-3 / 4 layer data delivery device suitable for lowering the cost according to the hardware configuration for data delivery of the AAL-3 / 4 layer. The purpose is.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention for achieving the above object is as follows.

The accompanying drawings are block diagrams illustrating an embodiment of a data transfer device of the AAL-3 / 4 layer of the present invention, which decodes an address from a system bus to signal a chip select signal (CS) and an initial address, and an initial data. An address discoder 10 for outputting a start signal ST, a counter 20 for receiving an address indicating the first address of the address decoder 10 and increasing an address as the read signal RD increases, and an address Enabled by the chip select signal CS of the decoder 10, receives data from the system bus, stores it, and then enables it by another chip select signal CS1, resulting in an increase in the read signal RD. A random access memory (RAM) 30 for outputting corresponding address data according to the increased address signal of 20, a start signal ST for notifying the first data of the address decoder 10, and The read signal RD is applied to the counter 20 by receiving a signal indicating the total data length, and the chip select signal CS1 and the read signal RD are applied to the storage unit 30, and then the signal is stored from the storage unit 30. The AAL-3 / 4 layer 40 receives address data and outputs a signal for forming an AMT cell to the ATM layer.

Referring to the present invention, the address decoder 10 first decodes an address of 28 bits from a 32-bit system bus of a sun workstation to inform the chip select signal CS and the first address, and the first signal. A start signal ST for informing data is output, respectively.

Next, the counter 20 receives a signal indicating the first address of the address decoder 10 and increases the address applied with 16 bits from the system bus as the read signal RD of the AAL-3 / 4 layer 40 increases. The storage unit 30 is enabled by the chip select signal CS of the address decoder 10, receives and stores data in 8 bits from the system bus, and then stores the data in the AAL-3 / 4 layer 40. It is enabled by another chip select signal CS1, and outputs the corresponding address data according to the increased address signal of the counter 20 according to the increase of the read signal RD.

Subsequently, the AAL-3 / 4 layer 40 receives a start signal ST for initial data of the address decoder 10 and a signal for notifying the total data length in 16 bits from the system bus, and then selects a chip in the storage unit 30. The signal CS1 and the read signal RD are applied to receive the address data output of the storage unit 30 with 8 bits, and output a signal for forming an ATM cell to the ATM layer.

That is, the AAL-3 / 4 layer 40 outputs a signal for forming a 52-byte ATM cell from which a 1-byte header error control (HEC) signal is excluded to the ATM layer in 8 bits.

As described above, the AAL layer according to the prior art uses an expensive FIFO when the data is received and output from the system bus, whereas in the present invention, the AAL layer is enabled by the chip select signal CS of the address decoder 10. After receiving and storing data from the system bus, it is enabled by another chip select signal CS1 of the AAL-3 / 4 layer 40, and the increased address signal of the counter 20 as the read signal RD increases. Accordingly, the cost is lowered by using the RAM in the storage unit 30 that outputs the corresponding address data, and thus there is an effect that it can be easily implemented.

Claims (2)

An address decoder 10 for decoding an address from the system bus and outputting a chip select signal CS, a signal for notifying the first address, and a start signal for notifying the first data, respectively; A counter 20 which receives a signal indicating the first address of the address decoder 10 and increases an address according to an increase in a read signal RD; Enabled by the chip select signal CS of the address decoder 10, received and stored data from the system bus, and then enabled by another chip select signal CS1 to increase the read signal RD. A storage unit 30 for outputting data of the corresponding address according to the incremented address signal of the counter 20 according to the present invention; The read signal RD is applied to the counter 20 by receiving the start signal ST indicating the first data of the address decoder 10 and the signal indicating the total data length, and the chip select signal to the storage unit 30. An AAL including an AAL-3 / 4 layer 40 which applies a CS1 and a read signal RD to receive an output of the storage unit 30 and outputs a signal for forming an ATM cell to an ATM layer; -3/4 layer data transfer device. The apparatus of claim 1, wherein the storage unit (30) comprises a RAM.