KR0131194B1 - Method of making semiconductor integrated circuit device having a capacitor with a porous sarface of electrode - Google Patents

Abstract

The capacitors incorporated in the semiconductor integrated circuit device are required to have a large capacity without increasing the occupied area, and among the group consisting of anodizing technology, anodizing, wet etching and dry etching so that the surface of the lower electrode becomes porous 21b. Using the selected roughening technique, the lower electrode 21a has an increased surface area, thereby increasing the capacitance.

Description

Semiconductor integrated circuit device having capacitor with electrode covered with porous surface, and method for manufacturing same

1A-1F are cross-sectional views illustrating the sequence of prior art processes for manufacturing stacked capacitors.

2A to 2D are cross-sectional views showing the sequence of the prior art process for manufacturing a cylindrical multilayer capacitor.

3A-3E are cross-sectional views illustrating various capacitor electrodes pertaining to the present invention.

4a to 4d are cross-sectional views showing the sequence of the first process according to the present invention.

5a to 5b are cross-sectional views showing the sequence of another process according to the present invention.

6a to 6d are cross-sectional views showing the sequence of the second process according to the present invention.

7a to 7f are cross-sectional views showing the sequence of the third process according to the present invention.

8 is a scanning electron micrograph showing the lower electrode before the penetrating step.

9 is a scanning electron micrograph showing the lower electrode after the penetrating step.

10A to 10C are scanning electron micrographs showing the fine grooves of the lower electrode at different magnifications.

11A-11C are scanning electron micrographs showing the surface of polysilicon treated with intentionally undoped phosphoric acid.

12A-12C are scanning electron micrographs showing doped polysilicon surfaces treated with phosphoric acid.

13 is a scanning electron micrograph showing a cross section of a multilevel polysilicon with an etch stopper.

14 is a cross-sectional view showing a composite dielectric layer conformally extending over the fine groove surface.

15A-15C are scanning electron micrographs showing the surface of an ion implanted polysilicon membrane treated with a phosphoric acid solution.

16 is a scanning electron micrograph showing the surface of a silicon film crystallized from amorphous silicon.

FIG. 17 is a scanning electron micrograph showing the surface of a polysilicon film treated with ammonia.

18A to 18H are cross sectional views showing a procedure of a seventh process according to the present invention.

19A is a graph showing leakage current density by applied voltage for polysilicon films with porous surfaces.

19B is a graph showing leakage current density by applied voltage for polysilicon films that do not have a porous surface.

FIG. 20 is a graph showing the percent failure following an electric field.

21A and 21B are cross-sectional views showing essential steps of the sequence of the eighth process according to the present invention.

FIG. 22 is a scanning electron micrograph showing the surface of a doped polysilicon treated with chlorine groups discharged in the presence of ultraviolet light.

23 is a scanning electron micrograph showing a doped polysilicon surface treated with a chlorine group in a parallel plate reactive ion etching system.

24A to 24H are cross-sectional views showing the sequence of the tenth step according to the present invention.

25A to 25D are cross sectional views showing the procedure of the fourteenth process according to the present invention.

Figure 26 is a graph showing the capacitance achieved by the various lower electrodes

27 is a scanning electron micrograph showing the surface of an amorphous silicon film.

* Explanation of symbols for main parts of the drawings

1: silicon substrate 2: silicon oxide film

3: mask film 4, 5, 7: polysilicon film

6: dielectric film 13: silicon nitride film

14 support structure 16a lower electrode

18: upper electrode 34: cathode

The present invention relates to a semiconductor integrated circuit device, in particular to a structure of a capacitor having an electrode covered with a porous surface and a method of manufacturing the same.

A typical example of a stacked capacitor incorporated in a semiconductor integrated circuit device is manufactured through the following process sequence shown in FIGS. 1A-1F. The process sequence begins with the preparation of the silicon substrate 1, wherein the silicon oxide film is grown on the main surface of the silicon substrate 1 so that the capacitor is electrically insulated from other circuit parts. The photoresist solution is spun on the silicon oxide film 2 and the photoresist film is patterned through a lithographic process for patterning the mask film 3 on the silicon oxide film 2 as shown in FIG. 1A.

Using the mask film 3, the silicon oxide film 2 is partially removed using dry etching techniques, and the contact holes 2a expose a portion of the silicon substrate 1. The resulting structure of this step is shown in Figure 1b. The mask film 3 is stripped off and polysilicon is applied over the entire surface of the structure to form the polysilicon film 4 on the silicon oxide film 2. The polysilicon film 4 passes through the contact hole 2a and is kept in contact with the silicon substrate 1. The photoresist solution is spun on polysilicon film 4 and patterned on mask film 5 via a lithographic process. The resulting structure of this step is shown in Figure 1c.

The polysilicon film 5 is partially corroded using the mask film 5, and the lower electrode 4a of the stacked capacitor is formed from the polysilicon 5 as shown in FIG. 1d. The lower electrode 4a forms upper and side surfaces, and the upper and side surfaces are very smooth.

The lower electrode 4a is covered with the dielectric film 6, as shown in FIG. 1E, and the dielectric film 6 is covered with the polysilicon film 6. The polysilicon film 7 serves as an upper electrode, and the lower electrode 4a, the dielectric film 6 and the upper electrode 7 are formed in combination with a stacked capacitor of the prior art.

Prior art stacked capacitors are popular among semiconductor manufacturers and have been incorporated into several semiconductor integrated circuit devices such as dynamic random access memory devices.

However, since semiconductor integrated circuit devices are gradually improving in the integration rate, the area occupied for each circuit component is gradually reduced. Although the footprint is reduced, the capacitor expects to accumulate the same amount of charge. In this situation, various structures have been proposed in the art for increasing the surface area of integrated electrodes, cylindrical integrated electrodes, pin integrated electrodes, and trenched electrodes known to those skilled in the art.

2A to 2D show a prior art process sequence for manufacturing a tubular multilayer capacitor, which process starts with the preparation of the silicon substrate 11. The inter-level dielectric film 12 is grown on the silicon substrate 11 and the silicon nitride film 13 is applied on the inter-level dielectric film 12. The photoresist solution is spun on silicon nitride film 13 and a mask film (not shown) is patterned from the photoresist film. Using the mask film, the silicon nitride film 13 and the inter-level insulating film 12 are continuously etched such that the contact holes 12a expose a portion of the silicon substrate 11.

The mask film is then peeled off.

The polysilicon film and the silicon oxide film are applied continuously over the entire surface of the structure, and a mask film (not shown) is patterned from the photoresist film on the silicon oxide film. The silicon oxide film and the polysilicon film are partially corroded, and the support structure 14 and the silicon oxide film 15 remain on the silicon nitride film 13. The support structure 14 passes through the contact hole 12a and is in contact with and supported by the silicon substrate 11.

Polysilicon film 16 is applied over the entire surface of the structure and the resulting structure of this step is shown in FIG. 2A. The polysilicon film 16 is subjected to reactive ion etching without a mask film, and the ion bombardment is the polysilicon film 16 of the upper surface of the silicon nitride film 15 and the portion of the polysilicon film 16 on the silicon nitride film 13. Remove part of). However, the polysilicon film 16 remains on the side surface of the silicon oxide film 15 and the support structure and acts as the lower electrode 16a. The resulting structure of this step is shown in Figure 2b.

The silicon oxide film 15 is corroded in an etching solution containing hydrofluoric acid, and the lower electrode 16a protrudes upward from the support structure shown in FIG. 2C.

The composite dielectric film structure 17 covers the lower electrode 16a and is composed of a silicon nitride film and a silicon oxide film.

Finally, a polysilicon film is applied over the entire surface of the structure, and the upper electrode 18 is formed from the polysilicon film as shown in FIG. 2d.

The cylindrical multilayer capacitor is manufactured to have an increased surface area because it is opposed through the composite dielectric film structure 17 to the upper electrode 18 on the inner and outer surfaces of the lower electrode 16a.

However, the inner and outer surfaces of the lower electrode 16a are very smooth, similar to the ordinary stacked capacitor shown in FIG. 1f.

For this reason, tubular stacked capacitors are not large enough to form advanced dynamic random access memory cells.

Moreover, other proposed structures, as well as tubular stacked capacitors, are produced through complex process sequences, and complex process sequences exhibit low reproducibility.

The present inventors have studied a solution for solving these defects, and proposed an electrode covered with hemispherical silicon particles in Japanese Patent Application No. 3-2721 65 filed March 20, 1990.

In the proposed process, hemispherical silicon particles are densely grown through low pressure chemical vapor deposition and the hemispherical silicon particle layer is patterned using dry etching techniques to form the lower electrode of the capacitor. Hemispherical silicon particles are expected to increase the surface area of the lower electrode, and the capacity is increased without increasing the footprint of the capacitor.

However, the hemispherical silicon particle layer is subjected to dry etching, the hemispherical particles are also ground, and the hemispherical particle layer becomes smooth. Because of this, the proposed capacitors rarely achieve the expected capacity.

The present inventors also proposed a method of growing a hemispherical silicon particle layer for a capacitor electrode in Japanese Patent Application No. 3-53933 filed on February 26, 1991. Since silicon oxide and carbon particles adhere to the surface of the smooth amorphous silicon layer during the lithographic and etching steps, the silicon oxide and carbon particles are removed from the smooth amorphous silicon layer, and the transparent amorphous silicon layer is heat treated in a vacuum or inert gas atmosphere. do. While the amorphous silicon layer is heated, the surface portion melts and crystallizes, roughening the crystallization surface. The proposed process sequence effectively increases the surface area of the capacitor electrode and the bottom surface is free of etching steps.

However, the process sequence proposed in Japanese Patent Application No. 3-53933 is complicated and expensive. This is because the washing step is necessary before the crystallization step and must be washed in a high temperature atmosphere for crystallization. This means that much effort and time is required for the capacitive electrode, and the proposed process sequence is expensive. Moreover, the bottom surface is twice the smooth surface width and is difficult to apply to advanced dynamic random access memory devices such as 4 Gigabit dynamic random access memory devices.

It is a main object of the present invention to provide a semiconductor device having a capacitor electrode with a multi-process surface for increasing the surface area.

Another main object of the present invention is to provide a method for manufacturing a semiconductor device which is simpler than a conventional process.

In order to achieve the above object, the process of the present invention uses a selective caustic to roughen the surface of the capacitor electrode.

According to one aspect of the present invention, a component element of an electrical circuit having a porous surface manufactured using a roughening technique selected from anodizing technique, anodizing, wet etching, and dry etching method, and having increased surface area to improve electrical characteristics. There is provided a semiconductor device manufactured on a substrate having a substrate.

According to another aspect of the present invention, a porous structure is used for producing a first electrode having a porous surface portion prepared using a roughening technique selected from anodizing technique, anodizing, wet etching, and dry etching methods, and a second micro groove. A semiconductor integrated fabricated on a substrate having a capacitor having a dielectric layer conformally covering the surface of the micro grooves formed in the surface portion and a second electrode opposite the porous surface portion of the first electrode and filling the second micro groove through the dielectric layer. Provide a circuit device.

According to another aspect of the invention, a) preparing a substrate for an integrated circuit having a capacitor, b) forming a semiconductor block for the capacitor lower electrode, and c) the anode so that a predetermined surface portion of the semiconductor block is porous Penetrating a predetermined surface portion of the semiconductor block using a roughening technique selected from two groups consisting of an oxidation technique, anodizing wet etching and a dry etching method, and d) forming a dielectric layer at an angle corresponding to at least a predetermined source portion of the semiconductor block. And a step of forming the upper electrode so as to face the predetermined surface portion of the semiconductor block through the dielectric layer.

Advantages and features of the semiconductor device according to the present invention and a method of manufacturing the same will be described in detail below with reference to the accompanying drawings.

Referring to FIGS. 3A-3E, various capacitor electrodes are constructed on or in the single crystal silicon substrates 21, 22, 23, 24, 25, and the present invention relates to the capacitor electrodes. Of course, such a capacitor electrode is shown by way of example, and the invention is applicable to any other capacitor now known or proposed in the future. Although only capacitor electrodes are shown in FIGS. 3A-3E. The capacitor electrodes are each covered with a dielectric layer in contact with the top electrode. The dielectric layer is realized by a single or composite dielectric film structure, and the upper electrode is formed of a semiconductor or metal material. As described below, the capacitor electrode is formed of monocrystalline, polycrystalline or amorphous silicon, and the term silicon in the following description does not mean only monocrystalline silicon. In defining crystals, the term silicon includes monocrystalline, polycrystalline, and amorphous.

The capacitor electrode of silicon shown in FIG. 3A typically serves as the lower electrode 21a of the stacked capacitor, and the surface of the capacitor electrode is finely penetrated to form the porous silicon film 21b.

The capacitor electrode of silicon shown in FIG. 3B acts as the lower electrode 22a of the cylinder multilayer capacitor, and the inner and outer surfaces of the lower electrode 22a are finely penetrated so that the porous silicon film 22b covers the inner and outer surfaces. .

The capacitor electrode of silicon shown in FIG. 3C serves as the lower electrode 23a of the pin-shaped multilayer capacitor, and has a stem portion 23b and pin portions 23c and 23d radially protruding from the stem portion 23b.

Not only the exposed surface of the stem portion 23b but also the surfaces of the fin portions 23c and 23d are finely penetrated, so that the lower electrode 23a is covered with the porous silicon film 23e.

3d illustrates a bottom electrode of the stacked trench capacitor, partially shows the bottom electrode in the silicon substrate 24, finely penetrates the surface of the bottom electrode 24a, and the porous silicon film 24b is formed of the bottom electrode (the bottom electrode). Cover 24a).

Finally, Figure 3e typically shows the bottom electrode 25a of the trench capacitor, and the silicon substrate 25 acts as the bottom electrode 25a. The lower electrode 25a is exposed to the trench 25b, and the surface of the lower electrode 25a is finely penetrated so that the trench 25b is defined by the porous silicon film 25c.

[First Embodiment]

4A to 4D, the first process sequence for implementing the present invention begins with preparing the single crystal silicon substrate 31. As shown in FIG. The field oxide film 32 is selectively grown on the main surface of the single crystal silicon substrate 31 through a selective oxidation process such as a LOCOS process. Polycrystalline silicon is deposited on the entire surface of the structure through low pressure chemical vapor deposition to form a polycrystalline silicon film 33, and the polycrystalline silicon film 33 is doped with impurities without a mask layer. The doped polycrystalline silicon 33 is anodized, and the surface portion of the doped polycrystalline silicon film 33 becomes porous as shown in FIG. 4A. In FIG. 4A, the root-shaped pattern shows micro grooves formed in the surface portion.

The anodizing process starts with preparing a platinum cathode 34, an aqueous solution of hydrofluoric acid and a suitable power source 35, with hydrofluoric acid in the range of 5% to 40% by volume. The doped polycrystalline silicon film 33 and the platinum cathode 34 are placed in an aqueous solution and connected to the power source 35. Direct current flows from a few milli-amps / cm 2 to several hundred milli-amps / cm 2 between the doped polycrystalline silicon film 33 or the anode and the platinum cathode 34. Then, the doped polycrystalline silicon film 33 is penetrated and made porous.

While the doped polycrystalline silicon film 33 is penetrated, visible to ultraviolet rays 36 may be emitted to the doped polycrystalline film 33.

Visible to ultraviolet 36 generate holes and promote chemical reactions for micro grooves.

The micro grooves generated as described above are in the range of 2 to 10 nanometers, and the bulk density of the porous silicon is in the range of 20% to 80% of the bulk density of the doped polycrystalline silicon film 33. If the diameter of the micro grooves is smaller than 2 nanometers, the dielectric layer attempts to deposit the micro grooves and cannot extend uniformly over the surface. In order to expand the micro grooves, the porous polycrystalline silicon is heat-treated at 800 ° C to 900 ° C. The heat treatment extends the micro grooves to tens of nanometers as shown in FIG. 4B. When the porous silicon is heat treated, oxygen reacts with the silicon, and undesirable silicon oxide covers the surface of the porous silicon. Silicon oxide restricts the movement of silicon atoms and insufficiently expands the micro grooves. In order to prevent porous silicon from undesirable silicon oxide, the partial pressure of oxygen should be less than or equal to 10-6 torr in high temperature environment. The heat treatment is more effective for the internal stress produced in the anodizing step.

The photosensitive corrosion resistant film is patterned through a lithographic process to form a mask layer (not shown) on the porous polycrystalline silicon film 33. Using the mask layer, the porous polycrystalline silicon film 33 is partially etched away, and the lower electrode 33a is formed on the silicon substrate 31. Silicon nitride films are deposited from 8 to 15 nanometers over the entire surface of the structure via low pressure chemical vapor deposition, and low pressure chemical vapor deposition is SiH ₂ Cl ₂ gas adjusted to 0.2 to 0.4 torr at a temperature of 600 ° C. to 700 ° C. And NH ₃ gas. The reason why the deposition is carried out at low temperatures is that the deposition rate is controlled by chemical reactions on and around the newly formed surface. For this reason, the silicon nitride film is uniformly deposited on the inner surface of the micro grooves and does not fill the micro grooves. The silicon nitride film is then oxidized in a vapor-containing atmosphere at 850 ° C. for 10 minutes, and the silicon oxide film is formed into a thin plate on the silicon nitride film. The silicon nitride film and the silicon oxide film are combined to form the composite dielectric layer 37. Oxidation in a vapor-containing atmosphere is preferred for electrical insulation between the lower electrode 33a and the upper electrode described below, because silicon oxide grows on the pinholes in the porous polycrystalline silicon and on the weak points on the porous polycrystalline silicon.

Thus, polycrystalline silicon is deposited on the entire surface of the structure through low pressure chemical vapor deposition to form a polycrystalline silicon film, and the structure produced in this step is shown in FIG. 4C.

The photosensitive anticorrosive solution is sprinkled onto the polycrystalline silicon film 38 and patterned into a mask layer (not shown) via a lithographic process. Using the mask layer, the polycrystalline silicon film 38 is partially etched away, and the upper electrode 38a remains on the composite dielectric layer 37 as shown in FIG. 4D.

Dry etching processes are available for penetration. That is, the mask layer 39 is patterned from the photosensitive corrosion resistant film through a lithographic process as shown in FIG. 5A, and the doped polycrystalline silicon film 32 is subjected to ion bombardment in dry etching. As a result, fine grooves are formed in the polycrystalline silicon film 33 as shown in FIG. 5B, and the process sequence returns to the steps described with respect to FIG. 4B.

As can be seen from the above description, the anodization step according to the present invention forms micro grooves in the polycrystalline silicon film 33, and the micro grooves effectively increase the surface area of the lower electrode 33a.

Second Embodiment

6A to 6D, the second process sequence for implementing the present invention begins with the preparation of the single crystal silicon substrate 41. As shown in FIG. The second process sequence is used to process the trench capacitors. The photoresist solution is sprinkled onto the main surface of the silicon substrate 41 and patterned through a lithographic process for the mask layer 42. The silicon substrate 41 partially covered with the mask layer 42 is immersed in the electrolyte, and anodic oxidation is performed in the electrolyte. Then, the exposed silicon substrate 41 penetrates as shown in FIG. 6A, and the root-shaped pattern represents the porous silicon portion. Several micro grooves are created in the porous silicon portion, and the micro grooves increase the surface area of the exposed silicon substrate 41.

The mask layer 42 is peeled off, and the silicon substrate 41 is heat-treated in a non-oxidation environment similar to that of the first embodiment. As a result, the micro grooves are expanded as shown in FIG. 6B.

The silicon nitride film is deposited on the entire surface of the structure through vapor low pressure chemical vapor deposition, and the silicon nitride film extends uniformly along the inner surface of the micro grooves. The silicon nitride film is partially oxidized in the containing atmosphere, and the silicon nitride film and the silicon oxide film are combined to form the composite dielectric layer 43 as shown in FIG. 6C. In FIG. 6C some rings are floating on the composite dielectric layer 43 and the floating ring represents the composite dielectric layer 43 so as not to fill the micro grooves.

Polycrystalline silicon low pressure chemical vapor deposition is deposited on the entire surface of the structure, and the polycrystalline silicon film is doped with impurities.

The photosensitive anticorrosive solution is sprinkled onto the entire surface of the polycrystalline silicon film and patterned into a mask layer (not shown) through a lithographic process. Using the mask layer, the doped silicon film is partially etched away and the upper electrode 44 remains on the composite dielectric layer 43. As shown in FIG. 6D, the polycrystalline silicon fills the secondary micro grooves defined by the composite dielectric layer 43, and the surface area is effectively increased.

Thus, the porous silicon portion is produced from single crystal silicon, and for this reason, the present invention is applicable to trench capacitors and stacked trench capacitors. Trench capacitors and stacked trench capacitors are preferred for forming flexible surfaces, and the wiring strips over the trench capacitors and stacked trench capacitors are less likely to be disconnected.

Third Embodiment

Referring to FIGS. 7A-7F, the third process sequence begins with preparing the single crystal silicon substrate 51.

The silicon oxide film 52 is grown on the main surface of the silicon substrate 51 for electrical insulation, and the photoresist solution is spun onto the silicon oxide film 52 in rotation. The photosensitive corrosion resistant film is patterned into the mask layer 53 through a lithographic process, and the structure created in this step is shown in FIG. 7A.

Using the mask layer 53, the silicon oxide film 52 is partially removed using dry etching, and the contact holes 52a are formed in the silicon oxide film 52 as shown in FIG. 7B.

Polycrystalline silicon is deposited on the entire surface of the structure through low pressure chemical vapor deposition at 600 ° C., and the polycrystalline silicon film 54 is kept in contact with the silicon substrate 51 through the contact hole 52a.

The polycrystalline silicon film 54 is exposed to POCl ₃ gas at 800 ° C. for 30 minutes, and phosphorus atoms are introduced into the polycrystalline silicon film 54. These atoms are about to separate around the boundaries and dislocations of the silicon particles of the polycrystalline silicon film 54. The photosensitive anticorrosive solution is sprinkled onto the doped polycrystalline silicon film 54 and patterned into the mask film 55 through a lithographic process as shown in FIG. 7C.

Using the mask film 55, the doped polycrystalline silicon film 54 is partially removed through reactive ion etching, and the lower electrode 54a is left on the silicon oxide film 52 as shown in FIG. 8 is a scanning electron micrograph taken in half when the ion etching is completed, the magnification of the photographic image is 60,000.

The surface of the doped polycrystalline silicon was relatively soft.

Thus, the lower electrode 54a is immersed in the caustic-containing phosphoric acid (H ₃ PO ₄ ). In detail, the caustic is heated to 140 ° C. and the lower electrode 54a is immersed in the caustic for 90 minutes. As described so far, phosphorus atoms separate along the grain boundaries and around the dislocations, and the corrosion proceeds faster in the heavily doped polycrystalline silicon than in the lightly doped polycrystalline silicon.

For this reason, the heavily doped portions around the grain boundaries and the dislocations are selectively etched for phosphoric acid, and the surface of the lower electrode 54a is penetrated through the phosphoric acid treatment as shown in FIG.

9 is a scanning electron micrograph taken at the completion of the phosphoric acid treatment, wherein the magnification of the photographic image is also 60,000. Comparing the photographic image of FIG. 8 and the photographic image of FIG. 9, it can be seen that micro grooves are generated on the surface of the lower electrode 54a by phosphoric acid treatment. Micro recesses were observed in scanning electron micrographs of FIGS. 10a, 10b and 10c, and the photographic images of FIGS. 10a to 10c were magnified at 100, 100, 200,000 and 400,000 magnifications, respectively.

The micro grooves range in size from several nanometers to several tens of nanometers.

Phosphoric acid selectively etches heavily doped silicon, and this phenomenon is evident from FIGS. 11A-11C and 12A-12C. When the intentionally undoped polycrystalline silicon film is phosphated for 10, 30, and 90 minutes, the surface of the undoped polycrystalline silicon film is significantly affected by phosphoric acid as shown in Figs. 11A to 11C. However, after the polycrystalline silicon film is placed in POCl ₃ gas at 800 ° C. for 30 minutes, the doped polycrystalline silicon film is phosphated and the surface of the doped polycrystalline silicon becomes rough as shown in FIGS. 12A to 12C. The photographic image shows rough surfaces phosphated for 10, 30 and 90 minutes respectively. Although the photographic images shown in FIGS. 11A-11C have not changed, the micro grooves of the doped polycrystalline silicon film are gradually formed in the doped polycrystalline silicon, and FIGS. 12A-12C illustrate the formation of the micro grooves.

In a modified process, the caustic or aqueous phosphoric acid solution is evaporated and the evaporated caustic is blown onto the phosphorus doped polysilicon film.

The porous portion is adjustable as the growth conditions of the polysilicon, the doping conditions of the impurities, the heat treatment conditions, and the phosphate concentration, duration and temperature, and is highly reproducible. For example, the thickness of the porous portion can be altered by changing the duration of treatment with phosphoric acid.

However, when a silicon oxide film is inserted into polysilicon, the silicon film acts as an etching stopper so that the thickness of the porous portion is precisely controlled. Of course, it is expected that the silicon oxide film will not degrade the electrical properties of the polysilicon electrode. For example, polysilicon is deposited up to 300 nanometers, but two silicon oxide films, each 2 nanometers thick, are inserted into the polysilicon film, after which the polysilicon film is 30 minutes at a temperature of 800 ° C. from POCl ₃ gas. Phosphorus is doped. The multi-leuel structure realized by the polysilicon film and the silicon oxide film is immersed for 60 minutes at a temperature of 140 ° C. in phosphoric acid containing caustic. The top doped polysilicon film is penetrated, so micro grooves are generated in the top doped polysilicon. However, the silicon oxide film shields the polysilicon below it from the caustic so that the thickness of the porous silicon is precisely controlled through the insertion of the silicon oxide film. 13 is a scanning electron micrograph showing a multi-level structure, it can be understood that the silicon oxide film effectively blocks the underlying silicon film from the caustic. Silicon oxide films embedded in polysilicon have increased micro grooves on the sides of the multilevel structure. This is because of the fact that the polysilicon crystals and grain boundaries grown in the vertical direction on the side thereof are less than those on the top surface of the multilevel structure. However, the silicon oxide film splits column-like polysilicon crystals to allow the corrosive to form micro grooves at the interface between the polysilicon film and the silicon oxide film.

After the micro grooves are formed in the lower electrode 54a, a composite dielectric layer 55 is formed on the entire surface of the lower electrode 54a and realized by the silicon nitride film 55a and the silicon oxide film 55b. First, 5 to 10 nanometers are deposited through low pressure chemical vapor deposition to form a silicon nitride film 55a and cover the silicon nitride film 55a.

Dielectric and ferroelectric materials having a large dielectric constant, such as, for example, Ta ₂ O ₅ , may be used as the dielectric layer 55.

Finally, phosphorus doped polysilicon is deposited on the entire surface of the structure and the phosphorus doped polysilicon film is patterned into the upper electrode 56 through a lithographic process leading to reactive ion etching. The resulting structure of this step is shown in Figure 7f. Because the micro grooves are large enough to allow the composite dielectric layer 55 to spread appropriately over its entire surface, the additional micro holes formed by the phosphorus doped silicon composite dielectric layer 55 as shown in FIG. By filling the grooves, the surface area of the capacitor is certainly increased.

As described above, the polysilicon film 14 is patterned into the lower electrode 54a before the micro grooves are formed, and for this reason, the micro grooves are not ground by the caustic.

However, even if the polysilicon film 54 is patterned after the micro grooves are formed, the surface area of the capacitor is significantly increased.

Fourth Embodiment

The process sequence for carrying out the fourth embodiment is similar to the third embodiment except for the transition doping step in which the micro grooves are formed, and for this reason, the film and parts of the fourth embodiment are similar to those of the third embodiment. It is shown by the same reference numerals as the corresponding films and parts. That is, after deposition of the polysilicon film 54, ions are implanted into the polysilicon film in a phosphorous atom of 1x10 ¹⁶ cm ^-2 under an acceleration energy of 70 eV. Thereafter, the doped polysilicon 54 is annealed at 900 ° C. for 30 minutes and immersed in a corrosion solution containing phosphoric acid at 140 ° C. 15A-15C are scanning electron micrographs showing the rugged surface of an ion implanted polysilicon film treated with 10 minutes, 20 minutes, and 60 minutes, respectively, with corrosion. These micrographs show that the phosphorus atoms ion implanted into the polysilicon film allow the corrosion solution to form fine grooves on the order of 5 nanometers.

The ion implanted phosphorus atoms gather along the grain boundaries and around the dislocations to allow the corrosive to selectively corrode the ion implanted polysilicon. However, any impurities gathered along the grain boundaries and around the dislocations may be used for ion implantation, and boron atoms, non-arsenic atoms, and antimony atoms are used in modifying the process sequence for carrying out the fourth embodiment.

[Example 5]

One of the features of the fifth process sequence embodying the present invention is in situ doping. During deposition of silicon via low pressure chemical vapor deposition in a 0.6 Torr SiH ₄ and PH ₃ gaseous mixture, phosphorus atoms are doped into the silicon film, and the doped silicon is treated with a phosphoric acid solution at 140 ° C.

When performing low pressure chemical vapor deposition at 630 ° C., doped polysilicon is deposited and phosphorus atoms collect along grain boundaries and around dislocations. For this reason, a phosphoric acid solution is applied directly to the doped polysilicon film.

However, when low pressure chemical vapor deposition is performed at 550 ° C., amorphous silicon is deposited, and amorphous silicon is annealed at 900 ° C. for 30 bones to grow large sized silicon grains.

Phosphorus collects along the grain boundaries and around the dislocations, and the phosphoric acid solution forms micro grooves of larger diameter than those formed in the polysilicon film. FIG. 16 is a scanning electron micrograph showing the rough surface of a silicon film crystallized from amorphous silicon. A 400 nanometer thick silicon film was treated with a phosphoric acid solution for 90 minutes. The micrograph shows micro grooves with larger dimensions.

Sixth Embodiment

The sixth process sequence embodying the present invention is similar to the third embodiment except for the formation of micro grooves, wherein the films and parts of the sixth embodiment have the same reference numerals as the corresponding films and parts of the third embodiment. Shown. After impurity atoms are injected into the polysilicon film 54, the doped polysilicon film 54 is exposed to an aqueous solution of NH ₃ at 60 ° C. The aqueous NH ₃ solution corrodes the doped polysilicon 54 5 nanometers per minute, resulting in deep micro grooves in the doped polysilicon film 54. FIG. 17 is a scanning electron micrograph showing the rugged surface of a doped polysilicon membrane treated with aqueous ammonia (NH ₃ ) solution. The micro grooves are about 5 nanometers, and the rugged surface treated with ammonia is black.

The doped polysilicon film 54 may be exposed to an aqueous solution of evaporated ammonia, containing a corrosive solution containing hydrofluoric acid (HF) and nitric acid (NH ₃ ), and a hydrofluoric acid and hydrogen peroxide (H ₂ O ₂ ). Corrosion solutions can be used for silicon films doped with phosphorus atoms, arsenic atoms, boron atoms and antimony atoms, respectively.

[Example 7]

As mentioned above, the doped silicon is penetrated using phosphoric acid or ammonia. However, the sides of the polysilicon film are not bumpy enough to increase the surface area.

The seventh process sequence may increase the surface area of the polysilicon electrode. The ninth process sequence begins with the formation of the single crystal silicon substrate 61, and the silicon oxide film 62 is grown on the main surface of the silicon substrate 61. A photoresist solution is spun onto the silicon oxide film 62, the photoresist film being a mask layer 63 that partially covers the silicon oxide film 62 as shown in FIG. 18A. Is patterned.

As a result, since the mask layer 63 is used, the silicon oxide film 62 is partially etched by using a dry etching technique, and holes 62a are formed in the silicon oxide film 62 as shown in FIG. 18B. do.

Since the mask layer 63 is peeled off and polysilicon is deposited on the entire surface of the structure through low pressure chemical vapor deposition, the polysilicon film 64 remains in contact with the silicon substrate 61 through the contact hole 62a. Is formed. Chemical vapor deposition is carried out at 600 ° C. in a gaseous mixture of SiH ₄ and H ₂ , SiH ₄ and He are adjusted to 20% and 80% and the gaseous mixture is adjusted to 1 torr. Phosphorus atoms or arsenic atoms are injected into the polysilicon film 64.

A photoresist solution is spun onto the polysilicon film 64 and patterned into the mask layer 65 via a lithographic process as shown in FIG. 18C, and the polysilicon film 64 is partially subjected to dry etching techniques. Is removed. The patterned polysilicon film 64a acts as part of the lower electrode 64a of the stacked capacitor, and the resulting structure of this step is shown in FIG. 18D.

The mask layer 65 is stripped and a polysilicon film 66 is deposited to a thickness of 150 nanometers over the entire surface of the structure using low pressure chemical vapor deposition under the same conditions as the polysilicon film 64.

The polysilicon film 66 is doped with phosphorus in a gaseous mixture containing POCl ₃ at 800 ° C. for 30 minutes. The resulting structure of this step is shown in FIG. 18E.

Thereafter, the doped polysilicon film 66 is uniformly etched using reactive ion etching without any mask, and the polysilicon film 66a remains on the side of the polysilicon film 64a.

The polysilicon films 64a and 66a form the lower electrodes of the capacitors stacked together, the resulting structure of which is shown in Figure 18f.

Although the polysilicon film 64a has columnar silicon grains in which the silicon substrate 61 extends in the vertical direction with respect to the main surface, the columnar silicon grains are in the horizontal direction with respect to the main surface of the silicon substrate 61. Extend. For this reason, a large amount of grain boundaries are exposed not only on the upper surface of the lower electrode but also on the side surface of the lower electrode.

The bottom electrode thus constructed is cleaned in a mixture of hydrochloric acid and hydrogen peroxide and exposed in an aqueous solution of H ₃ PO ₄ at 140 ° C. for 60 minutes. As a result, the entire surface of the lower cathode is penetrated by H ₃ PO ₄ and becomes rugged as shown in FIG. 18g. A large number of micro grooves are exposed on the entire surface of the lower electrode, and the porous silicon membrane is shown at 67.

Finally, a composite dielectric layer 68 is formed on the entire surface of the lower electrode and covered by the polysilicon film 69 doped with phosphorus atoms. The polysilicon film 69 is patterned with the upper electrode of the multilayer capacitor. Although the composite dielectric layer 68 is grown over the micro grooves of the porous silicon film 67, the hatched layer 68 merely indicates the presence of the composite dielectric layer. In an actual product, the composite dielectric layer 68 covers the surface forming the micro grooves and spreads properly so as not to cover the micro grooves at all.

For this reason, the lower electrode formed by the polysilicon films 64a and 66a has twice the surface area as in the third embodiment.

The lower electrode of the seventh embodiment is excellent in electrical characteristics. For example, the leakage current is as small as that of the polysilicon film without any porous surface portion as shown in FIGS. 19A and 19B. FIG. 19A is a graph showing leakage current density versus voltage applied to a polysilicon film having a porous surface, and FIG. 19B is a graph showing leakage current density versus voltage applied to a polysilicon film having no porous surface. Comparing FIG. 19A and FIG. 19B, the leakage current of the lower electrode realizing the seventh embodiment is as small as that of ordinary polysilicon electrodes.

FIG. 20 shows the breakdown characteristics of a polysilicon film having a porous surface, the discharge characteristics of which are not deteriorated by the porous surface portion.

[Example 8]

Turning to FIGS. 21A and 21B, a seventh process sequence embodying the present invention begins with the manufacture of the polycrystalline silicon substrate 71, through a lithographic process that involves etching a 200 nanometer thick polysilicon film. The lower electrode 72 is patterned. The polysilicon bottom electrode was exposed to POCl ₃ gas at a temperature of 800 ° C. for 30 minutes to inject phosphorus atoms as shown in FIG. 21A. Phosphorus atoms gather along the grain boundaries of the polysilicon bottom electrode 72 and around the dislocations.

The substrate 71 is placed in a chamber 73 filled with chlorine gas Cl ₂ of the tor, and emits ultraviolet light from the low-pressure mercury lamp 74, where the chlorine is present in the presence of ultraviolet light. Chlorine radicals are produced. The chlorine groups hit the polysilicon doped with phosphorus atoms and selectively corrode the heavily doped polysilicon. In this embodiment, the lower electrode is exposed to chlorine for 5 minutes, and the heavily doped grain boundaries corrode 5 to 100 times faster than the rest of the slightly doped polysilicon.

As a result, as shown in FIG. 21B, the lower electrode 72 of polysilicon penetrates and is covered with the rugged surface portion 72a. 22 is a scanning electron micrograph showing the surface of the lower electrode exposed to the chlorine group in the eighth process sequence.

In the eighth embodiment, chlorine groups are used as caustic agents. However, other halogen groups such as bromine or iodine can also be used. Moreover, halogen groups can be generated through photo-presence phenomena, and microwaves, high frequency electromagnetic waves, and plasma generated with electron guns can also be used to generate halogen groups.

[Example 9]

The ninth process sequence is similar to the third embodiment of polysilicon deposition for the lower electrode. The 200 nanometer thick polysilicon film is doped with phosphorus atoms in a POCl ₃ gas atmosphere at 800 ° C. for 30 minutes, and the phosphorous atoms gather along grain boundaries and around the dislocations.

The mask layer is patterned onto polysilicon doped as a phosphorus atom through a lithographic process. Thus doped polysilicon partially covered with a mask layer is placed in a parallel plate reactive ion etching system, and the caustic containing chlorine (Cl ₂ ) is controlled up to 20 Pa in the reaction chamber. Chlorine groups are bombarded with the doped polysilicon film, and the doped polysilicon exposed to the caustic is anisotropically corroded. While the caustic is anisotropically patterned anisotropically doped polysilicon, heavily doped portions around the grain potential are etched by chlorine despite the mask layer, and micro grooves are anisotropic at the surface of the doped polysilicon film. Occurs as an enemy. 23 is a scanning electron micrograph showing the surface of doped polysilicon treated with chlorine groups.

Thus, the ninth process allows the chlorine group to simultaneously achieve the patterning and formation of the micro grooves in the lower electrode, which process is relatively simple.

In this case, a parallel plate reactive ion etching system is used to make chlorine groups for use in anisotropic patterning and penetration.

However, reactive ion etching systems and helicon-etching systems reinforced with ECR and magnetron can be used to make the chlorine group.

In addition, another halogen group, such as a fluorine group, bromine group or iodine group, simultaneously patterns and penetrates the doped polysilicon film.

[Example 10]

24A to 24H, the tenth process starts with the preparation of the single crystal silicon 18. As shown in FIG. The silicon oxide film 82 is grown on the main surface of the silicon substrate 81 for electrical insulation, and the silicon nitride film 83 is deposited on the silicon oxide film 82 through low pressure chemical vapor deposition deposition. The silicon nitride film 83 aims to protect the silicon oxide film 82 from the hydrofluoric acid used in the later step. The photoresist resist is rotated in the silicon nitride film 83 and patterned on the mask layer 84 through a lithographic process as shown in FIG. 24A.

Using the mask layer 84, the silicon nitride film 83 and the silicon oxide film 82 are partially etched to form the contact holes 85, and the mask layer 82 is peeled off.

The amorphous silicon film is then deposited on the entire surface of the structure through low pressure chemical vapor deposition deposition at 0.6 Torr in a gas mixture of SiH ₄ and PH ₃ , and the gas mixture is controlled at 550 ° C.

The amorphous silicon film is annealed at 800 ° C. for 120 minutes to convert the amorphous silicon into a polysilicon film 86. As mentioned above, the crystallized polysilicon is of relatively large granule size. The photoresist solution is rotated over the entire surface of the polysilicon film 86, and the photoresist is patterned on the mask layer 87 through a lithographic process. The structure made through this step is shown in FIG. 24C.

Using the mask layer 87, the polysilicon film 86 is partially etched to form the lower electrode 86a, after which the mask layer 87 is stripped off. The structure made at this stage is shown in Figure 24d.

The structure shown in FIG. 24d is immersed in a hydrofluoric acid containing electrolyte solution between 5 and 40 vol%, and the lower electrode 86a is opposite to the platinum cathode (not shown). Since the direct current flows as a few hundred milliamperes / cm ₂ between the lower electrode 86a serving as the anode and the platinum cathode, the lower electrode 86a is penetrated by the anodization phenomenon.

Anodization can benefit from light from visible to ultraviolet light. Micro grooves are formed in the surface portion of the lower electrode 86a, and the diameter ranges from 2 nanometers to 10 nanometers. The volume density of the porous silicon is controlled from 20% to 80%. The porous silicon 86b covers the entire surface, that is, the top and side surfaces of the lower electrode 86a as shown in FIG. 24E.

If the micro grooves are few nanometers smaller, the dielectric film deposited in the later stages is much easier to fill the micro grooves, and the micro grooves are expanded as shown in Figure 24f. The extension technique will be described with reference to the thirteenth embodiment.

Then, a composite dielectric layer 88 is smoothly formed on the rough side of the porous silicon as shown in FIG. 24G, and doped polysilicon is deposited over the surface of the sphere. The doped polysilicon film is panned into the top electrode as shown in FIG. 24h.

Porous silicon 86b treated with hydrofluoric acid has a tenfold increase in surface area than conventional electrodes. In this case, the composite dielectric layer 88 extends partially in the silicon nitride film 83 and smoothly in the porous silicon 86. However, the silicon nitride film 83 can be removed before the composite dielectric layer 88 is formed.

The formation of porous silicon through anodization is well known in the art, but porous silicon is isolated between circuit components, the formation of silicon-on-insulators, the formation of silicide wirings and the formation of light emitters. It is applied to the application field.

However, porous silicon formed through anodization is never applied to the increase in accumulated charge, and the inventors believe that the present invention is novel and advanced.

[Example 11]

As mentioned above, if the micro grooves are too small, the dielectric layer tends to fill the micro grooves and cannot extend smoothly throughout the surface of the porous silicon. When the dielectric layer fills the micro grooves, the surface area of the capacitor cannot be increased, and the present invention cannot achieve a large amount of accumulated charge without increasing any footprint. For this reason, it is necessary to insert a lancet step between the formation of the micro grooves and the formation of the dielectric layer.

In this case, after the formation of the micro grooves, the porous silicon is exposed to an anodizing environment of 700 ° C. and 1 Torr to grow a silicon oxide film of 20 to 30 nanometers. The micro grooves are expanded because the silicon oxide film is removed from the hydrofluoric acid. The other process sequence of the eleventh embodiment is similar to that described above, and therefore will not be described any further. The porous silicon surface can be quickly oxidized, after which the silicon oxide film is removed.

In order to precisely control the size of the micro grooves, the porous silicon is immersed in an aqueous solution containing hydrogen peroxide or nitric acid, and silicon oxide is removed using hydrofluoric acid.

Since silicon oxide grows from 1 to 2 nanometers in all oxidation steps, the micro grooves extend by 1 to 2 nanometers. Repeated oxidation and removal causes the micro grooves to expand in stages.

[Twelfth Example]

In the twelfth embodiment, the micro grooves are expanded as follows. The porous silicon surface is nitrided in an ammonia environment at 800 ° C. for 60 minutes, so silicon nitride grows from 1.5 nanometers to 2 nanometers. Thereafter, the silicon nitride film is etched in the H ₃ OP ₄ solution, and nitriding and removal are repeated according to a predetermined time.

[Thirteenth Embodiment]

Porous silicon is quickly oxidized or cut and small micro grooves can be filled with silicon oxide or nitride.

In addition, the silicon width would have to be at least twice that of the depletion layer to serve as an electrode. Therefore, in the thirteenth embodiment, the porous silicon is annealed to recrystallize the silicon in a non-oxidizing environment, a vacuum environment or a reducing environment, and the recrystallized silicon particles are larger than the predetermined porous silicon particles. Although the diameter of the micro grooves is only a few nanometers in diameter, the porous silicon treated for 5 minutes at 1000 ° C. in a hydrogen environment is recured to have micro grooves that extend as large as 10 nanometers.

The recrystallization is published by J. Electrohem, Soc, SOLID-STATE SCIENCE AND TECHNOLOGY, August 1978, Vol. 125, No. 8, page 1339, by Seki Takagashi and Masahiro Seki as the structure and heat treatment effect of the porous silicon layer.

[Example 14]

25A to 25D, a fourteenth process using the present invention begins by preparing a single crystal silicon substrate 91 partially covered with a silicon oxide film 92. Deposited to a thickness of 200 nanometers through low pressure chemical vapor deposition deposition at 500 DEG C of amorphous silicon, and the amorphous silicon film is patterned on the lower electrode 93 using lithographic technique with dry etching shown in FIG. 25A.

The silicon substrate 91 is heated to 750 ° C., and the lower electrode 93 of amorphous silicon is annealed in vacuo in accordance with Japanese Patent Application No. 3-53933 described above. At that time, hemispherical particles grow to cover the surface of the lower electrode 93 as shown in FIG. 25B.

The resulting structure is placed in a high temperature environment of 800 ° C. and accepts phosphorus atoms in POCl ₃ for 30 minutes at the lower electrode 93.

Phosphorus atoms segregate around the displacements along the grain boundaries, and the lower electrode 93 is immersed in the phosphoric acid solution at 140 ° C. for 60 minutes. Therefore, the lower electrode treated with phosphoric acid is covered with the porous silicon film 93a having hemispherical particles as well as the micro grooves smaller in size than the hemispherical particles shown in FIG. 25C, and the surface area of the porous silicon film 93a is only hemispherical particles. Twice as large as the covered bottom electrode and four times as large as the normal polysilicon surface shown in FIG. In FIG. 26, plots PL1, PL2, PL3 and PL4 are each untreated normal stacked bottom electrode, stacked bottom electrode with micro grooves, stacked bottom electrode with hemispherical particles, and stacked bottom electrode with micro grooves of hemispherical particles, respectively. Point to.

Finally, the composite dielectric layer 94 covers the porous silicon film 93a, and the upper electrode 95 is patterned from the doped polysilicon film as shown in FIG. 25d. While the composite composite dielectric layer forms an upper surface over the rough surface in FIG. 25d, the composite polysilicon layer 94 smoothly extends to form secondary micro grooves, and the doped polysilicon fills the auxiliary micro grooves.

In this case, phosphorus atoms are accepted through diffusion. However, impurity atoms can be implanted into ions within the hemispherical particles, or they can be used in phosphorus silicon films despite doping techniques. In addition, an arsenic atom may be taken in place of a phosphorus atom.

[Example 15]

Although the lower electrode is formed of amorphous silicon, phosphoric acid penetrates through the lower electrode. For example, a doped amorphous silicon film is deposited to a thickness of 200 nanometers through in-site low pressure chemical vapor deposition deposition, and phosphorus atoms are excessively doped at 1 × 10 ²¹ cm ⁻³ . The doped amorphous silicon film is patterned through a lithographic process involving dry etching. The lower electrode is immersed in the phosphoric acid solution at 140 ° C. for 60 minutes, and micro grooves are formed in the surface portion of the lower electrode. 27 is a scanning electron micrograph showing the micro grooves in the surface portion formed in the 15th process sequence.

The composite dielectric layer and the upper electrode are successfully applied to the porous surface of the lower electrode, and the capacitor performing the sixteenth embodiment is completed.

The surface area of the lower electrode thus assembled is twice as large as the smooth surface of the lower electrode having the smooth surface.

In this case, phosphorus atoms are accepted through intra-regional doping. However, without any sidewalk doping, the uncorrected silicon film can be penetrated. In addition, when silicon atoms are ion implanted into a polysilicon film doped with phosphorus atoms, the doped polysilicon film is converted to an amorphous silicon film.

[Example 16]

In a sixteenth process using the present invention, an amorphous silicon film is deposited using a diffusion technique. That is, the silicon substrate is placed in the diffusion system and heated to 100 ° C. The silicon substrate is on the opposite side of the target, and the argon gas in the diffusion chamber is regulated to 6 × 10 ⁻² Torr. Amorphous silicon is diffused and deposited to a thickness of 300 nanometers. Due to the inclined shadow effect, the deposited silicon film has a column structure, and voids are formed between the columns.

Phosphorus atoms diffuse and crystallize into silicon films deposited from POCl ₃ at 800 ° C. for 20 minutes. The silicon oxide film is undesirably grown in the diffusion step and is removed by exposure to hydrofluoric acid. The porous surface is then complete.

As the silicon target doped with phosphorus or boron diffuses, a porous amorphous silicon film is deposited and annealed for recrystallization.

In addition, if the silicon target is diffused in the source gas containing PH ₃ B ₂ H ₆ , the diffusion process takes place and the deposited film is annealed for recrystallization.

The formation of amorphous silicon through diffusion has been described by Kiyoshi Takahashi and Magato Konagai in the amorphous silicon handbook published by the Science Forum in 1983.

[Example 17]

Porous silicon membranes are made through lithographic processes. That is, the doped polysilicon is deposited to a thickness of 500 nanometers, and the target of silicon oxide diffuses into the 50 nanometer doped polysilicon film as a gas mixture of argon and oxygen at 6 ^{× 10 −2 '} tor. The silicon oxide film thus diffused is composed of several columns each having a width of 10 nanometers, and is exposed to a caustic containing a few percent of the silicon oxide hydrofluoric acid. At that time, the gap between columns extends to 20 nanometers. The structure is placed in a parallel plate reaction etch system and the doped polysilicon is etched in a gaseous caustic containing chlorine at 20 Pa. The doped polysilicon film is exposed to the caustic through the gap of the silicon oxide film and is anisotropically etched. As a result, several doped polysilicon columns remain, thereby forming micro grooves in the doped polysilicon film. The doped polysilicon columns are separated from each other by 10 nanometers.

If the diffusion state changes, an island-like or mesh mask layer is obtained and can be used to pattern the doped polysilicon film.

In this case, the mask layer is formed from the silicon oxide film. However, any material may be used, as long as it selects a possible caustic agent between the doped polysilicon and the material.

Also, an electron cyclotron reactive etch system, a magnetron reinforced reactive ion etch system and a helicon etch system can be used in place of the parallel plate reactive etch system.

While particular embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. For example, if the circuit component is improved in characteristics by increasing the surface area, the present invention can be applied to the circuit component. In addition, the upper electrode may be formed of another semiconductor material or a conductive metal.

Claims (20)

Providing a substrate for an integrated circuit having a capacitor; Stacking a doped polysilicon film on a substrate for the lower electrode of the capacitor; Penetrating the surface portion of the doped polysilicon film using an anodization technique so that the surface portion of the doped polysilicon film has a porosity, wherein the anodization treatment technique is performed in an aqueous solution of 5 to 40 vol% hydrofluoric acid, Direct current flows between a few milli-amps / cm ² and several hundred milli-amps / cm ² under light radiation on the doped polysilicon film between the doped polysilicon film and the platinum or cathode, the light corresponding to the ultraviolet rays from visible light. Having a wavelength range to make; Conformally covering at least a portion of the doped polysilicon film with a dielectric layer; Forming an upper electrode in a manner opposed to the surface portion of the polysilicon film doped through the dielectric layer. Providing a substrate for an integrated circuit having a capacitor; Forming an in-doped polysilicon film for the lower electrode of the capacitor; The surface portion of the semiconductor block is etched in a corrosion solution containing phosphoric acid so as to be porous, thereby penetrating the surface portion of the phosphorus-doped polysilicon film having grooves along the grain boundaries of the phosphorus-doped polysilicon film, wherein the periphery of the displacement along the grain boundary Introducing an impurity atom into the semiconductor block to separate impurity atoms into the semiconductor block; and a corrosion solution having an etching ratio that varies with the concentration of the impurity atoms to selectively remove the concentrated doped portions around the grain boundary and the displacement. Processing the semiconductor block and consequently forming a micro recess in a predetermined surface portion of the semiconductor block; Conformally covering at least the surface portion of the semiconductor block with a dielectric layer; Forming an electrode on the dielectric layer in a manner opposite to the surface portion of the semiconductor block. The method of claim 2, wherein the semiconductor block is made of polysilicon, and the impurity atoms and the corrosion solution are phosphorus and phosphoric acid containing vapors. Providing a substrate for an integrated circuit having a capacitor; Forming a semiconductor block for the lower electrode of the capacitor, wherein laminating a semiconductor material that can be etched by the corrosive, laminating a material substantially etched by the corrosive on the film of the semiconductor material, and Laminating a semiconductor material to a thickness over a film of material, the film further comprising combining the film of semiconductor material with the film of substantially etched material to form a semiconductor block; Penetrating the surface portion of the semiconductor block using etching so that the surface portion of the semiconductor block is porous-introducing a doped atom atom near the displacement along the grain boundary, between the heavily doped and the shallowly doped portion; Selectively etching the heavily doped portion around the grain boundary and the displacement using a corrosion solution having a selectivity, wherein: conformally covering at least the surface portion of the semiconductor block with a dielectric layer; Forming a top electrode through the dielectric layer in a manner opposed to a surface portion of the semiconductor block. 5. The method of claim 4, further comprising the steps of: laminating a material substantially etched by the corrosive liquid on the film of semiconductor material and laminating a semiconductor material to a certain thickness on the film of the material, wherein the film of the semiconductor material and the nearly etched material are bonded. Forming the semiconductor block is repeated after laminating a semiconductor material that can be etched by the corrosion solution. Installing a substrate for an integrated circuit having a capacitor; forming a semiconductor block for the lower electrode of the capacitor; penetrating the surface portion of the semiconductor block using etching to make the surface portion of the semiconductor block porous; Ion implanting phosphorus atoms into the semiconductor block, annealing the semiconductor block to coalesce phosphorus atoms along the grain boundary around the displacement, and selectively depositing concentrated doped regions around the grain boundary and the displacement. Treating the semiconductor block with an isotropic corrosion solution having an etch rate that varies with the concentration of the phosphorus atoms to remove and consequently forming a micro recess in a predetermined surface portion of the semiconductor block; Conformally covering at least the surface portion of the semiconductor block with a dielectric layer; Forming a top electrode through the dielectric layer in a manner opposed to a surface portion of the semiconductor block. Providing a substrate for an integrated circuit having a capacitor; Forming a semiconductor block for the lower electrode of the capacitor, whereby depositing amorphous silicon doped with phosphorus atoms acting as a semiconductor block, and causing phosphorus atoms to coalesce around the displacement along the boundary between the large silicon particles; Annealing the amorphous silicon; Penetrating the surface portion of the semiconductor block using etching through treatment with a climbing etching solution containing phosphoric acid such that the surface portion of the semiconductor block is porous; Conformally covering at least the surface portion of the semiconductor block with a dielectric layer; Forming a top electrode through the dielectric layer in a manner opposed to a surface portion of the semiconductor block. Providing a substrate for an integrated circuit having a capacitor; Forming a doped polysilicon block for the lower electrode of the capacitor; The surface of the doped polysilicon block using etching in an aqueous ammonia solution and one of ammonia vapors, a mixture of hydrofluoric acid and nitric acid, and a mixture of hydrofluoric acid and hydrogen peroxide, such that the surface portion of the doped polysilicon block is porous Burrowing through; Conformally covering at least the surface portion of the doped polysilicon block with a dielectric layer; Forming an upper electrode in a manner opposed to a surface portion of the polysilicon block doped through the dielectric layer. Providing a substrate for an integrated circuit having a capacitor; Forming a semiconductor block for the lower electrode of the capacitor, wherein the polysilicon is laminated on the main surface of the substrate to form a first polysilicon film having columnar particles perpendicular to the main surface, and the first polysilicon; Patterning the first polysilicon film to form a sub-block, and a second polysilicon covering the side of the first polysilicon block with a portion of the second polysilicon film having columnar particles generally parallel to the major surface; Stacking polysilicon over the entire surface to form a film, and the second polysilicon sub-block is left on the side of the first polysilicon sub-block, and the first and second polysilicon sub-blocks And uniformly etching the second polysilicon film without any mask to be formed by bonding— and ; Introducing impurity atoms in the semiconductor block to penetrate the surface portion of the semiconductor block using a roughness technique selected such that the surface portion of the semiconductor block is porous, wherein the impurity atoms are dispersed around the displacement along the grain boundaries; In order to selectively remove the heavily doped portions and the grain boundary, the semiconductor block doped with the impurity atoms is exposed to a corrosion solution having an etching ratio that varies with the concentration of the impurity atoms, thereby miniaturizing the small surface portions of the semiconductor blocks. Further comprising forming a set; Conformally covering at least the surface portion of the semiconductor block with a dielectric layer; Forming a top electrode through the dielectric layer in a manner opposed to a surface portion of the semiconductor block. Providing a substrate for an integrated circuit having a capacitor; Forming a semiconductor block for the lower electrode of the capacitor; Penetrating the surface portion of the semiconductor block by using dry etching such that the surface portion of the semiconductor block is porous, wherein the phosphorus atom is introduced into the semiconductor block so as to break around the displacement along the particle boundary, and Exposing the semiconductor block doped with phosphorus atoms with a halogen ratio having an etching ratio that varies with the concentration of the impurity atoms to selectively remove concentrated doped sites, resulting in a micro recess in a predetermined surface portion of the semiconductor block. Further comprising the step of forming; Conformally covering at least the surface portion of the semiconductor block with a dielectric layer; Forming an upper electrode in a manner against the surface portion over the semiconductor block through the dielectric layer. The method of claim 10, wherein the halogen group is generated from halogen atoms under one of light emission phenomena, radiation of ultra-small waves, radiation of high frequency electromagnetic waves, and plasma furnace generated by an electron gun. Providing a substrate for an integrated circuit having a capacitor; Stacking a doped polysilicon film on the substrate; Patterning and penetrating the doped polysilicon film for the lower electrode of the capacitor using dry etching such that the surface portion of the lower electrode is porous, wherein the dry etching is provided by a parallel plate reaction etching system, electron cyclotron resonance Performing using a halogen group generated from one of an ion etching system, a magnetron reactive ion etching system and a helicon etching system; Conformally covering at least the surface portion of the semiconductor block with a dielectric layer; Forming a top electrode through the dielectric layer in a manner opposed to a surface portion of the semiconductor block. Providing a substrate for an integrated circuit having a capacitor; Forming a semiconductor block for the lower electrode of the capacitor; Penetrating the surface portion of the semiconductor block using an anodizing technique so that the surface portion of the semiconductor block is porous, wherein the electrolyte comprises 5 to 40% by volume of fluorine, hydrogen acid, and an anode; Causing the semiconductor block to oppose the cathode of the electrolyte, and flowing a direct current between the semiconductor block and the cathode for generating the micro recess; Conformally covering at least the surface portion of the semiconductor block with a dielectric layer; Forming a top electrode through the dielectric layer in a manner opposed to a surface portion of the semiconductor block. Providing a substrate for an integrated circuit having a capacitor; Depositing a silicon film on a substrate for the lower electrode of the capacitor; Penetrating the surface portion of the silicon film using an anodizing technique so that the surface portion of the silicon film is porous, wherein the anodizing technique is performed in an aqueous solution of hydrofluoric acid of 5 to 40% by volume, and the direct current is the silicon film. Flowing between a few milli-amps / cm ² to several hundred milli-amps / cm ² between the platinum and the cathode; To expand the smallest recesses generated in the surface portion of the silicon film, where: a) immersing the surface portion of the silicon film in an aqueous solution containing one of hydrogen peroxide and nitric acid to grow a thin oxide film between 1 and 2 nanometers. And (b) exposing the oxide film in hydrofluoric acid to remove the thin oxide film and repeating steps a) and b); Conformally covering at least the surface portion of the silicon film with a dielectric layer; Forming an upper electrode through the dielectric layer in a manner opposed to the surface portion of the silicon film. Providing a substrate for an integrated circuit having a capacitor; Depositing a silicon film on a substrate for the lower electrode of the capacitor; Penetrating the surface portion of the silicon film using an anodizing technique so that the surface portion of the silicon film is porous, wherein the anodizing technique is performed in an aqueous solution of hydrofluoric acid of 5 to 40% by volume, and the direct current is the silicon film. Flowing between a few milli-amps / cm ² to several hundred milli-amps / cm ² between the platinum and the cathode; Exposing a predetermined surface portion to a solution containing ammonia to expand the smallest recess generated in the surface portion of the silicon film, wherein: (a) growing the silicon nitride film from 1.5 nanometers to 2.0 nanometers; Removing the silicon nitride film from the solution containing ₃ PO ₄ and _c ) repeating steps a) and b): conformally covering at least the surface of the silicon film with a dielectric layer. Step and; Forming an upper electrode through the dielectric layer in a manner opposed to the surface portion of the silicon film. Providing a substrate for an integrated circuit having a capacitor; Depositing a silicon film on a substrate for the lower electrode of the capacitor; Penetrating the surface portion of the silicon film using an anodizing technique so that the surface portion of the silicon film is porous, wherein the anodizing technique is performed in an aqueous solution of hydrofluoric acid of 5 to 40% by volume, and the direct current is the silicon film. Flowing between a few milli-amps / cm ² and watermelon milli-amps / cm ² between the platinum and the cathode and expanding the smallest recesses occurring in the surface portion of the silicon film, wherein the non-oxidizing atmosphere, the vacuum atmosphere and Generating a hot annealing atmosphere from one of the diminishing atmospheres and recrystallizing a predetermined surface portion in said hot annealing atmosphere to enlarge the micro recess; Conformally covering at least the surface portion of the silicon film with a dielectric layer; Forming an upper electrode through the dielectric layer in a manner opposed to the surface portion of the silicon film. 17. The method of claim 16, wherein the high temperature annealing atmosphere comprises hydrogen. Installing a substrate for an integrated circuit having a capacitor; Forming a semiconductor block for the lower electrode of the capacitor, wherein: depositing an amorphous silicon film on the substrate; patterning the amorphous silicon film in a lower electrode serving as the semiconductor block; and on the surface of the lower electrode. Further comprising annealing the lower electrode in vacuum by heating the substrate to form hemispherical particles; Penetrating the surface portion of the semiconductor block using a roughness treatment technique such that the surface portion of the semiconductor block is porous, wherein the impurity atoms are introduced into the lower electrode such that the impurity atoms are dispersed near the displacement along the particle boundary; Exposing the lower electrode to a corrosion solution containing phosphoric acid to penetrate the; Conformally covering at least the surface portion of the semiconductor block with a dielectric layer; Forming a top electrode through the dielectric layer in a manner opposed to the surface portion of the semiconductor block. Providing a substrate for an integrated circuit having a capacitor; Forming a semiconductor block for the lower electrode of the capacitor, wherein forming a doped amorphous silicon film through a vapor phase reaction method, and patterning the doped amorphous silicon film in a lower electrode serving as a semiconductor block Additionally comprising; Penetrating the surface portion of the semiconductor block by etching the semiconductor block in an etching solution containing phosphoric acid such that the surface portion of the semiconductor block is porous; Conformally covering at least the surface portion of the semiconductor block with a dielectric layer; Forming a top electrode through the dielectric layer in a manner opposed to a surface portion of the semiconductor block. The method of claim 2, wherein the corrosion solution comprising phosphoric acid is heated to about 140 ° C. to penetrate the surface.