KR0130172B1 - Formation method of transistor of semiconductor device - Google Patents
Formation method of transistor of semiconductor deviceInfo
- Publication number
- KR0130172B1 KR0130172B1 KR1019940015436A KR19940015436A KR0130172B1 KR 0130172 B1 KR0130172 B1 KR 0130172B1 KR 1019940015436 A KR1019940015436 A KR 1019940015436A KR 19940015436 A KR19940015436 A KR 19940015436A KR 0130172 B1 KR0130172 B1 KR 0130172B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- gate electrode
- transition metal
- forming
- oxide film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims description 17
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 239000012535 impurity Substances 0.000 claims abstract description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 229910052723 transition metal Inorganic materials 0.000 claims abstract description 25
- 150000003624 transition metals Chemical class 0.000 claims abstract description 25
- 150000002500 ions Chemical class 0.000 claims abstract description 15
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 13
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 61
- 239000010936 titanium Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910008486 TiSix Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910003849 O-Si Inorganic materials 0.000 description 1
- 229910003872 O—Si Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
제1도는 종래기술에 의해 형성된 반도체소자의 트랜지스터를 도시한 단면도.1 is a cross-sectional view showing a transistor of a semiconductor device formed by the prior art.
제2A도 내지 제2D도는 본 발명의 제1실시예에 의한 반도체소자의 트랜지스터 형성공정을 도시한 단면도.2A to 2D are sectional views showing the transistor forming process of the semiconductor device according to the first embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1,11 : 반도체기판 2,13 : 게이트산화막1,11 semiconductor substrate 2,13 gate oxide film
3 : 게이트전극 4,16 : 전이금속막3: gate electrode 4, 16: transition metal film
5,17 : 저농도의 불순물영역 6,18 : 산화막 스페이서5,17: low concentration impurity region 6,18 oxide film spacer
7,19 : 고농도의 불순물영역 12 : 열 산화막7,19: high concentration impurity region 12: thermal oxide film
14 : 게이트전극용 다결정실리콘막 15 : 진성 다결정실리콘막,14 polycrystalline silicon film for the gate electrode 15 intrinsic polysilicon film,
15' : 비정질 다결정실리콘막 20 : 제1불순물15 ': amorphous polysilicon film 20: first impurity
30 : 제1불순물.30: 1st impurity.
본 발명은 반도체소자의 트랜지스터 형성방법에 관한 것으로써, 특히 자기정렬된 실리사이드(Silicide)구조를 갖는 게이트전극 형성시에 반도체기판에 트렌치를 형성하고 소정의 불순물이 도핑된 다결정실리콘막을 증착한 후 그 상부에 진성 다결정실리콘막 및 전이금속막을 순차적으로 증착하고 신화막 스페이서를 형성하고 전이금속막을 고온열처리 공정으로 산화시켜 실리사이드로 변환시킴으로써 게이트산화막의 막질을 향상시켜 반도체소자의 신뢰성을 향상시킬 수 있는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a transistor of a semiconductor device, and in particular, in forming a gate electrode having a self-aligned silicide structure, forming a trench in a semiconductor substrate and depositing a polysilicon film doped with a predetermined impurity. A technology capable of improving the reliability of semiconductor devices by depositing an intrinsic polysilicon film and a transition metal film on top of one another, forming a thin film spacer, oxidizing the transition metal film to a silicide by converting it to silicide, and improving the film quality of the gate oxide film. to be.
최근의 반도체 기억소자가 초고집적화 됨에 따라 상대적으로 저항이 작은 게이트 전극용 물질이 필요하게 되었다.Recently, as semiconductor memory devices have been highly integrated, materials for gate electrodes having a relatively low resistance are needed.
제1도는 종래 기술에 의한 게이트전극을 도시한 단면도로서, 반도체기판(1)상에 소정 패턴의 게이트산화막(2) 및 불순물이 도핑된 다결정 실리콘막, 즉 게이트전극(3)을 형성하고 상기 게이트전극(3)의 상부에만 선택적으로 전이금속막(4)을 증착한 다음, 저농도의 불순물이온을 주입하여 저농도의 불순물영역(5)을 형성하고 상기 게이트전극(3)의 측벽에 산화막 스페이서(6)을 형성한 다음, 고농도의 불순물 이온을 주입하여 고농도의 불순물영역(7)을 형성하고 고온열공정으로 상기 전이금속막(4)을 실리사이드로 변화시킨 엘.디.디(LDD:Lightly Doped Drain, 이하에서 LDD라 함)구조의 트랜지스터를 도시한 것을 도시한 단면도로서, 상기 저농도의 불순물이온인 인(P)을 사용하고 상기 고농도의 불순물이온은 비소(As)를 사용한 것이다. 여기서, 상기 전이금속막은 티타늄으로 형성한 것이며, 전이금속막이 실리사이드(7)로 변환되는 과정에서 상기 전이금속막을 구성하는 티타늄이 상기 게이트전극(3)의 실리콘과 반응하여 형성된 TiSix 화합물이 상기 게이트산화막(2)으로 침투하여 게이트산화막(2)의 막질(Film Quality)을 저하시킴으로써 반도체소자의 신뢰성을 저하시킨다.1 is a cross-sectional view showing a gate electrode according to the prior art, in which a gate oxide film 2 having a predetermined pattern and a polycrystalline silicon film doped with impurities, that is, a gate electrode 3, are formed on a semiconductor substrate 1, and the gate After selectively depositing the transition metal film 4 only on the electrode 3, a low concentration of impurity ions are implanted to form a low concentration of impurity region 5 and an oxide spacer 6 on the sidewall of the gate electrode 3. ), And then implanting a high concentration of impurity ions to form a high concentration of impurity region (7) and to convert the transition metal film (4) to silicide by high temperature heat process (LDD: Lightly Doped Drain) The following figure shows a transistor having an LDD structure, in which phosphorus (P), which is a low concentration of impurity ions, is used, and arsenic (As), which is used for the high concentration of impurity ions. Here, the transition metal film is formed of titanium, and the TiSix compound formed by reacting the silicon of the gate electrode 3 with titanium constituting the transition metal film in the process of converting the transition metal film into silicide (7) is the gate oxide film. It penetrates into (2) and lowers the film quality of the gate oxide film 2, thereby reducing the reliability of the semiconductor device.
따라서, 본 발명은 종래의 문제점을 해결하기 위하여, 게이트전극과 실리사이드 사이에 진성 다결정 실리콘막을 일정두께 증착하여 게이트전극을 형성하는 반도체소자의 트랜지스터 형성방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a transistor of a semiconductor device in which a gate electrode is formed by depositing a thickness of an intrinsic polycrystalline silicon film between a gate electrode and a silicide at a predetermined thickness.
이상의 목적을 달성하기 위한 본 발명의 특징은, 반도체기판의 예정된 부위를 식각하여 트렌치를 형성하고 전체구조상부에 열산화막을 형성한 다음, 제1불순물이온을 주입하는 공정과, 상기 열산화막을 습식방법으로 제거하고 게이트산화막을 증착한 다음, 그 상부에 게이트전극용 다결정실리콘막과 진성 다결정실리콘막 및 전이금속막을 순차적으로 증착하는공정과, 게이트전극 마스크를 이용하여 상기 전이금속막, 진성 다결정실리콘막 및 게이트전극용 다결정실리콘막을 순차적으로 식각함으로써 게이트전극을 형성하고 저농도의 불순물이온을 주입하여 저농도의 불순물영역을 형성하는 공정과, 상기 게이트전극의 측벽과 상기 트렌치 내부의 전이금속막 측벽에 산화막 스페이서를 형성하고 고농도의 불순물이온을 주입하여 고농도의 불순물영역을 형성하는 공정과, 고온 열처리공정을 실시하여 상기 전이금속막을 실리사이드로 변화시켜 트랜지스터를 형성하는 공정을 포함하는데 있다.A feature of the present invention for achieving the above object is a step of etching a predetermined portion of the semiconductor substrate to form a trench, forming a thermal oxide film on the entire structure, and then injecting a first impurity ion, and wet the thermal oxide film And then depositing a gate oxide film, and sequentially depositing a polycrystalline silicon film, an intrinsic polysilicon film, and a transition metal film for the gate electrode thereon, and using the gate electrode mask to form the transition metal film and the intrinsic polycrystalline silicon. Sequentially etching the film and the polysilicon film for the gate electrode to form a gate electrode and injecting a low concentration of impurity ions to form a low concentration of impurity region; and an oxide film on the sidewall of the gate electrode and the sidewall of the transition metal film inside the trench. By forming a spacer and injecting high concentration of impurity ions, To the transition metal in the silicide film is changed by performing the step of high temperature heat treatment step of forming a can comprises the step of forming the transistor.
이하, 첨부된 도면을 참고로하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제 2A도 내지 제 2D도는 본 발명의 제 1실시예로서 반도체소자의 트랜지스터 형성공정을 도시한 단면도이다.2A to 2D are cross-sectional views showing a transistor forming process of a semiconductor device as a first embodiment of the present invention.
제2A도는 반도체기판(11)의 예정된 부위를 식각하여 트렌치(20)을 형성한 다음, 전체구조상부에 열산화막(12)을 성장시킨 다음, 문턱진압(threshold voltage, VT) 조절용 제1불순물(20)을 소정농도로 이온주입한 것을 도시한 단면도로서, 상기 열산화막(12)은 불순물이온 주입시 상기 반도체기판(11)을 보호하기 위한 것이며 상기 제1불순물(20)은 붕소(B)를 사용한 것이다.FIG. 2A illustrates a trench 20 by etching a predetermined portion of the semiconductor substrate 11, growing a thermal oxide film 12 over the entire structure, and then adjusting the threshold voltage (V T ). A cross sectional view showing ion implantation at a predetermined concentration, wherein the thermal oxide film 12 is for protecting the semiconductor substrate 11 during impurity ion implantation and the first impurity 20 is boron (B). Is used.
제2B도는 상기 열산화막(12)을 습식식각으로 제거한 후, 소정두께의 게이트산화막(13)을 형성하고 상기 게이트산화막(13) 상부에 저압 화학기상증착(LPCVD:Low Pressure CVD, 이하에서 LPCVD라함)방법으로 불순물이 도핑된 게이트전극용 다결정실리콘막(14), 진성 다결정실리콘막(15) 및 전이금속막(16)을 소정두께 순차적으로 증착하고 한 것을 도시한 단면도로서, 상기 습식식각은 HF 또는 완충 산화막 식각용액을 사용한 것이다. 여기서, 상기 전이금속막(16)은 Ti, W, Mo 및 Ta으로 형성할 수 있다.FIG. 2B is a view showing that the thermal oxide film 12 is wet-etched, and then a gate oxide film 13 having a predetermined thickness is formed and low pressure chemical vapor deposition (LPCVD) is formed on the gate oxide film 13. Is a cross-sectional view of sequentially depositing a polysilicon film 14, an intrinsic polysilicon film 15, and a transition metal film 16 for a gate electrode doped with impurities by a predetermined thickness, wherein the wet etching is HF. Or a buffer oxide etching solution. Here, the transition metal film 16 may be formed of Ti, W, Mo, and Ta.
제2C도는 게이트전극 마스크(도시안됨)를 이용하여 게이트전극(14,15,16)을 형성한 다음, 저농도의 불순물이온을 주입하여 저농도의 불순물영역(17)을 형성한 것을 도시한 단면도로서, 상기 진성 다결정실리콘막(15)은 이온주입에 의한 손상때문에 비정질 다결정실리콘막(15')으로 변화한다. 여기서, 상기 게이트전극(14,15,16)은 상기 게이트전극용 다결정실리콘막(14)과 진성 다결정실리콘막(15) 그리고 전이금속막(16)으로 형성한 것이며 상기 저농도의 불순물이온은 인(P)을 사용한 것이다.2C is a cross-sectional view of the gate electrodes 14, 15, and 16 formed using a gate electrode mask (not shown), followed by implantation of low concentration of impurity ions to form a low concentration of impurity region 17. The intrinsic polysilicon film 15 is changed to an amorphous polysilicon film 15 'due to damage by ion implantation. Here, the gate electrodes 14, 15, and 16 are formed of the polysilicon film 14, the intrinsic polysilicon film 15, and the transition metal film 16 for the gate electrode, and the low concentration impurity ions are formed of phosphorus ( P) is used.
제2D도는 상기 게이트전극(14,15,16)의 측벽에 산화막 스페이서(18)를 형성한 다음, 상기 산화막 스페이서(18)를 마스크로 하여 고농도의 불순물인 비소(As)를 소정농도로 이온주입하여 고농도의 불순물영역(19)을 형성한 것을 도시한 단면도로서, 상기 산화막 스페이서(18)는 대신에 질화막 스페이서를 사용하여도 동이한 효과를 얻는다. 여기서, 산화가스를 이용한 고온 열처리공정으로 사기 전이금속막(16)을 실리사이드로 변환시킨다. 이때, 고온 열처리에 사용되는 산소가 실리사이드와 비정질 다결정실리콘막(25')의 계면에 유입되어 Ti-O-Si 형태의 TiSix 침투 방지용 경계막을 형성하여 막질 특성 저하를 방지한다.In FIG. 2D, an oxide spacer 18 is formed on the sidewalls of the gate electrodes 14, 15, and 16, and ion implantation is performed at a predetermined concentration using arsenic As as a high concentration of impurities using the oxide spacer 18 as a mask. As a cross-sectional view showing the formation of a high concentration impurity region 19, the oxide film spacer 18 can obtain the same effect even if a nitride film spacer is used instead. Here, the frying transition metal film 16 is converted into silicide by a high temperature heat treatment process using an oxidizing gas. At this time, oxygen used in the high temperature heat treatment flows into the interface between the silicide and the amorphous polysilicon film 25 'to form a Ti-O-Si type TiSix penetration preventing boundary film to prevent degradation of the film quality.
상기한 본 발명에 의하면, 종래에 게이트산화막의 막질 저하로 발생되는 문제점을 해결하기 위하여 진성 다결정실리콘막을 사용함으로써 게이트산화막의 막질 저하를 방지하여 반도체소자의 전기적 특성 및 신뢰성을 향상시킬 수 있다.According to the present invention described above, in order to solve the problems caused by the conventional film quality reduction of the gate oxide film, by using the intrinsic polysilicon film, the film quality of the gate oxide film can be prevented from being lowered, thereby improving the electrical characteristics and reliability of the semiconductor device.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940015436A KR0130172B1 (en) | 1994-06-30 | 1994-06-30 | Formation method of transistor of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940015436A KR0130172B1 (en) | 1994-06-30 | 1994-06-30 | Formation method of transistor of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960002697A KR960002697A (en) | 1996-01-26 |
| KR0130172B1 true KR0130172B1 (en) | 1998-04-06 |
Family
ID=19386829
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940015436A KR0130172B1 (en) | 1994-06-30 | 1994-06-30 | Formation method of transistor of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0130172B1 (en) |
-
1994
- 1994-06-30 KR KR1019940015436A patent/KR0130172B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR960002697A (en) | 1996-01-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR970002266B1 (en) | Semiconductor devices and integrated circuits using sidewall spacer technology | |
| US5920783A (en) | Method of fabricating a self-aligned silicide MOSFET | |
| KR100225409B1 (en) | Trench dmos and method of manufacturing the same | |
| KR100440840B1 (en) | Method of manufacturing semiconductor device and semiconductor device | |
| KR100332106B1 (en) | Method of manufacturing a transistor in a semiconductor device | |
| US7485516B2 (en) | Method of ion implantation of nitrogen into semiconductor substrate prior to oxidation for offset spacer formation | |
| US6245639B1 (en) | Method to reduce a reverse narrow channel effect for MOSFET devices | |
| JPH04225529A (en) | Improved method for manufacture of integrated-circuit structure body provided with lightly doped drain (ldd) | |
| KR100344375B1 (en) | Semiconductor device manufacturing method | |
| US6677212B1 (en) | Elevated source/drain field effect transistor and method for making the same | |
| JP3657915B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| US6180543B1 (en) | Method of generating two nitrogen concentration peak profiles in gate oxide | |
| US6281085B1 (en) | Method of manufacturing a semiconductor device | |
| KR0130172B1 (en) | Formation method of transistor of semiconductor device | |
| KR100223736B1 (en) | Method of manufacturing semiconductor device | |
| KR100192537B1 (en) | Method of manufacturing semiconductor device | |
| KR100734259B1 (en) | Method for fabricating semiconductor devices | |
| KR0146242B1 (en) | Forming method for transistor of semiconductor device | |
| KR0137538B1 (en) | Transistor fabrication method of semiconductor device | |
| KR100607793B1 (en) | Ion implantion method of poly silicon gate electrode | |
| KR100756766B1 (en) | Method for manufacturing a semiconductor device | |
| KR100268865B1 (en) | Method for fabricating semiconductor device | |
| KR100235943B1 (en) | Method of manufacturing tansistor of semiconductor device | |
| KR20010098183A (en) | Method of forming oxide film for semiconductor device | |
| JPH03188637A (en) | Manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20091028 Year of fee payment: 13 |
|
| LAPS | Lapse due to unpaid annual fee |