KR0128223Y1 - Soe rel time generation circuit - Google Patents

Abstract

The present invention relates to a real-time generation circuit of SOE. In the past, when the central processing unit informs the central processor that a SOE (ie, an interrupt) has been generated, the central processing unit processes the current task and then interrupts the interrupt. Interrupts are performed after the preprocessing is performed both in the case of processing and in the case of stopping work, which causes a difference between the time when SOS occurred and the time given to the central processing unit.

Therefore, in order to solve the conventional problems, the present invention reads the time of the moment when the SOE occurs in the timer according to the interrupt signal output by the comparator and stores it in the RAM and then receives the interrupt signal in the central processing unit. By reading the time stored in the RAM, it is effective to know the exact time.

Description

Soi real time generation circuit

1 is a conventional SOE real-time generation circuit diagram.

2 is a schematic diagram of a real time generation (SOE) of the present invention.

* Explanation of symbols for main parts of the drawings

DESCRIPTION OF SYMBOLS 1: Field insulation part 2, 3, 5: 1st-3rd latch

4: comparator 6: divider

7: address / clock generator 8: multiplexer

9: timer 10: buffer

11: RAM BUS: Control Bus

The present invention is to generate a time when a sequence of event (SOE) occurs, in particular to a real time generating circuit (SOE) for generating a time exactly coinciding with the occurrence of SOE (SOE) It is about.

As shown in FIG. 1, a conventional SOE real time generation circuit includes a field insulator 1 for isolating an input field and outputting the same to the first latch 2, and the first latch 2; The second latch 3 temporarily storing the output of the < RTI ID = 0.0 > and < / RTI > and the output data of the first and second latches 2 and 3 respectively. The comparator 4 and the comparison result of the comparator 4, if the two data are different, an interrupt is generated to the central processing unit, and the output of the first latch 2 is temporarily latched and output through the control bus. And a third latch 5, and a divider 6 for dividing and outputting an input clock.

In the conventional technology configured as described above, when a field is input, the field insulator 1 is insulated and input to the first latch 2, and then the latch is temporarily latched by the first latch 2, and then the comparator 4 ).

At this time, when the output of the first latch 2 is also received by the second latch 3 and stored in the comparator 4, the comparator 4 compares the two input values and controls the bus. And output to the central processing unit through the third latch (5).

For example, when the two values compared by the comparator 4 are different from each other, the comparator 4 generates an interrupt INT in a high state and outputs the interrupt INT to the central processing unit.

At the same time, the third latch 5 receives and latches the output data of the first latch 2 when the interrupt occurs.

The central processing unit that recognizes the interrupt reads and processes the data CDAT stored in the third latch 5 using the control bus BUS.

However, in this conventional technique, when the central processing unit is notified that the interrupt signal INT, that is, the SOE has been generated, the central processing unit processes the interrupt after processing the current work. Both the case and the case where the work is being done are suspended, and after performing the preprocessing to handle the interrupt, SOE reads the generated data, finds the occurrence point, and gives the time. There was a problem with the time and the time given by the central processing unit.

Therefore, in order to solve the conventional problem, the present invention reads the year, month, date, hour, minute, second, etc. of the timer at the moment when the SOE is generated and stores them in RAM according to the interrupt signal by the comparator. After the central processing unit that received the interrupt signal reads the time stored in the RAM and processes the work quickly, the SOE real-time generation circuit is devised. When described in detail as follows.

FIG. 2 is a schematic diagram of a SOE real-time generation circuit of the present invention. As shown in FIG. The comparator 4 and the comparator 4 generating an interrupt signal when the second latch 2 and the output value of the first latch 2 and the second latch 3 are different from each other. The third latch 5 latching the field data newly input by the first latch 2 according to the comparison output and the year, month, day, and the like are enabled according to the comparison output signal of the comparator 4. Timer 9 for reading hours, minutes and seconds, address / clock generator 7 for generating address and clock data (LADD) according to the input clock, and selection input via the control bus (SEL Signal and lead / light (R / A multiplexer 8 which selects and outputs data generated from the address / clock generator 7 and the central processor according to the signal, and a read / write input via the control bus. RAM 11 for storing the data RDAT read by the timer 9 according to the signal and buffering the input data according to the output enable OE1 input through the control bus. It consists of a buffer 10 to be output.

Referring to the operation and effects of the present invention configured as described above in detail.

First, when the system is initialized, the central processing unit outputs and drives the output enable (OE1) signal to the buffer 10 through the control bus, and inputs data (CDAT) to buffer the data (CDAT). (RDAT) is output to the timer 9. At the same time, when the central processing unit outputs the select signal SEL through the control bus BUS to the multiplexer 8 so that the multiplexer 8 operates, the data processing unit CADD and the address / clock generating unit ( 7) The multiplexer 8 receives the data LADD generated from the multiplexer and multiplexes the data LADD and outputs the random data MADD. Light (CR / Signal) and outputs the same to the timer (9).

The timer 9 then receives data MADD and read / write CR / which are input from the multiplexer 8. ) And the data RDAT input from the buffer 10. The current year, month, day, hour, minute, second and 1/100 second are recorded.

In this initialized state, when n inputs are input to the field insulator 1, the inputs are insulated and input to the first latch 2, and are latched. When the first clock CLK is input to the clock terminal, the input is latched. Output data (NDAT). The output data NDAT is inputted to the comparator 4 and inputted to the second latch 3 and latched. The latched data outputs the data latched by the second clock CLK. The output data of the first latch 2 and the second latch 3 are input to the comparator 4 and compared with each other.

In the comparator 4 receiving and comparing the data output by the first latch 2 and the second latch 3, an interrupt (INT) signal is generated when the compared data is different from each other. BUS) is known to the central processing unit and is applied to the third latch 5 at the same time. Accordingly, the third latch 5 latches the data NDAT output through the first latch 2. At this time, the data NDAT latched in the first latch 2 becomes new field input data. In addition, the interrupt (INT) signal is input to the timer 9 to make the enable state.

Then, the output data LADD of the address / clock generator 7 and the output data MADD of the multiplexer 8 (CR / ), The timer 9 reads the current year, month, day, hour, minute, second, 1/100 second, and the like, and stores them in the RAM 11. At this time, the central processing unit stops the current work by interrupt (INT) and sends data (CADD) signal and read / write (R /) to RAM 11. ) To generate a signal and store the year, month, day, etc. stored in the RAM 11. Etc. are read through the data CDAT, and the output enable OE2 is output to the third latch 5 to be driven, and the current data is read from the field data stored therein.

As described in detail above, the present invention reads the time immediately after SOE occurs and stores it in RAM, and then reads the time stored in the RAM by the central processing unit receiving the interrupt signal to generate the correct time. One effect is to make it work.

Claims (1)

The first latch 2 which latches the data insulated through the field insulation unit 1 and outputs it by the clock CLK, and receives and latches the output of the first latch 2 according to the clock CLK. Comparing the second latch 3 to be output, the output data of the first latch 2 and the second latch 3 and the comparator 4 for outputting the compared data and the comparator 4 A third latch 5 latching new field data latched to the first latch 2 in accordance with the output INP, an address / clock generator 7 for generating an address and a clock in accordance with the clock, Select (SEL) signal and lead / light (R /) input via the control bus (BUS) A multiplexer 8 which selects and outputs data generated from the address / clock generator 7 and the central processor according to the signal, and a read / write input via the control bus. RAM 11 for storing the data RDAT read by the timer 9 according to the signal and buffering the input data according to the output enable OE1 input through the control bus. SOE real-time generation circuit consisting of a buffer (10) to output.