KR0127688B1 - Forming method of charge storage electrode - Google Patents

Abstract

The method is for fabricating a capacitor without increasing pin numbers. The method includes: forming a contact hole for the capacitor at an intermediate insulating layer deposited on a semiconductor substrate; alternatively depositing an impurity-doped amorphous silicon layer and non-doped amorphous silicon layer in the named order a few times; selectively etching the impurity-doped amorphous silicon layer and the underlying non-doped amorphous silicon layer to define a storage electrode of the capacitor; polycrystallizing the impurity-doped amorphous silicon layer and the underlying non-doped amorphous silicon layer remaining after the etching step and diffusing impurities of the impurity-doped amorphous silicon layer into the underlying non-doped amorphous silicon layer through a thermal anneal; and removing the polycrystallized impurity-doped amorphous silicon layer and an impurity diffused region of the non-doped amorphous silicon layer.

Description

How to Form Charge Storage Electrode

1 is a partial cross-sectional view of a typical DRAM cell.

2 is a cross-sectional view of a charge storage electrode forming process according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

10, 12, 14: doped amorphous silicon film 11, 13: undoped amorphous silicon film

100: charge storage electrode

TECHNICAL FIELD The present invention relates to the field of semiconductor manufacturing, and more particularly, to a process of forming a charge storage electrode, which is a lower electrode of a cell capacitor of a DRAM, which is a semiconductor memory device.

As DRAMs are highly integrated, the cell area is drastically reduced, and despite the reduction in cell area, there is a difficulty in securing capacitance over a certain capacity per cell required for device operation.

In particular, in the highly integrated semiconductor device, a soft error caused by alpha (α) particles increases due to a decrease in the capacitance of the capacitor.

Accordingly, the development of advanced process technology and securing the reliability of the device for securing a certain level of charge storage capacity is an urgent solution.

Among the various three-dimensional charge storage electrode structures developed in response to the above demands, the fin structure has been widely used because of its relatively simple manufacturing process, but the number of fins is increased to secure a constant capacitor capacity as the cell area is reduced. As the number of pins increases, the chemical vapor deposition-type oxide film and polysilicon film must be alternately formed to form multiple layers, thereby increasing the cost of increasing the number of processes and causing particles and defects due to frequent chemical vapor deposition processes. There is a problem such as a decrease in yield due to (defect) increase.

Accordingly, an object of the present invention is to provide a method for forming a charge storage electrode capable of increasing capacitance without increasing the number of fins and adding a separate process step. .

In order to achieve the above object, the method of forming a charge storage electrode according to the present invention includes forming a charge storage electrode contact hole by forming an interlayer insulating film on a semiconductor substrate having a predetermined lower layer and selectively etching the same; A second step of alternately depositing an amorphous silicon film doped with impurities and an amorphous silicon film not doped with impurities on the entire structure; A third step of selectively etching the amorphous silicon film doped with the impurity and the amorphous silicon film not doped with the impurity by using an etching mask for defining a charge storage electrode; Performing a predetermined heat treatment to polycrystallize the amorphous silicon film doped with the impurity and the amorphous silicon film not doped with the impurity, and allow the impurity to penetrate a portion of the amorphous silicon film not doped with the impurity; And a fifth step of removing the impurity diffusion portion of the amorphous silicon film doped with the impurity and the polycrystalline crystallized impurity.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

First, in FIG. 1, in forming a general DRAM cell, a field oxide film 2, a word line 4, a source / drain region 5, and a bit line (not shown) are formed at a predetermined portion on a silicon substrate. A cross-sectional view of a state in which a contact hole for forming a charge storage electrode is formed on a planarized surface and an amorphous silicon film (hereinafter, referred to as a doped amorphous silicon film) doped with impurities is formed. Reference numeral 3 denotes a gate oxide film, 6 an oxide spacer, and 7 an interlayer insulating film.

The structure shown in FIG. 1 can be achieved through a conventional process, and with this structure formed, an embodiment of the present invention will be described in detail with reference to FIGS. 2A through 2D.

First, FIG. 2A shows a gas such as Si ₂ H ₆ or SiH ₄ as the main reaction gas at a temperature of 480 to 550 ° C. using one process tube, that is, using an in-situ method. and after the formation of the first-degree doped amorphous silicon film 10 it is not doped with impurities to a thickness of about 1000 to 2000Å on the upper amorphous silicon film (11, hereinafter referred to as a non-doped amorphous silicon film), PH ₃ gas again By adding and depositing to form a phosphorous (doped) ion-doped amorphous silicon (12) film 12 to a thickness of 1/3 to 1/2 of the undoped amorphous silicon film (11), but the concentration of phosphorus doped It is so large that it completely supersaturates phosphorus. Subsequently, the same process as in the formation of the undoped amorphous silicon film 11 is performed to form the undoped amorphous silicon film 13, and the dope amorphous silicon film 14 is formed thereon. Subsequently, a photoresist pattern 15 is formed on the doped amorphous silicon film 14 to define the line width of the charge storage electrode.

In the exemplary embodiment of the present invention, as shown in FIG. 2A, only two layers of the undoped amorphous silicon films 11 and 13 are formed, that is, a charge storage electrode forming process having two fins will be described as an example.

Next, as shown in FIG. 2B, the doped amorphous silicon film 10 is selectively etched using the photoresist pattern 15 as an etching barrier.

Subsequently, FIG. 2C shows a state in which heat treatment is performed for 30 to 60 minutes in an inert gas atmosphere at a temperature of 650 to 750 ° C., where the doped amorphous silicon films 10 ', 12', and 14 'are crystallized into a polysilicon film. In the process of transition of solid crystal growth, impurities such as phosphorus contained in the doped amorphous silicon films 10 ', 12', and 14 'are in a fully activated form, and the excess impurities are in the upper or lower ratio. It diffuses into the doped amorphous silicon films 11 ', 13'. The non-doped amorphous silicon films 11 'and 13' are crystallized into a polysilicon film during the heat treatment process, and the crystal grain size at this time is formed to a size of about 200 to 500 microns. Impurities supersaturated in the doped amorphous silicon film 10 ', 12', 14 'are first introduced into the grain boundary region between the crystal grains and the particles of the polycrystalline non-doped amorphous silicon film 11', 13 '. Diffusion is then diffused into the crystal, and by using the impurity diffusion characteristic in the polycrystalline polysilicon film, a charge storage electrode having a hemispherical curve as shown in the figure can be formed. At this time, the process conditions should be adjusted so that the impurities diffused to the grain boundary do not penetrate too much into the crystal.

Next, as shown in FIG. 2D, wet etching is performed using a polysilicon film etchant mixed with nitric acid, acetic acid, hydrofluoric acid, and pure water. At this time, the polycrystallized doped amorphous silicon film 10 ', 12', 14 'including the impurity diffusion region formed by the heat treatment has a much higher etching rate than the polycrystalline non-doped amorphous silicon film 11', 13 '. By wet etching for a predetermined time using a fast etching characteristic, the charge storage electrode 100 having a hemispherical surface structure can be formed.

The present invention made as described above can significantly reduce the manufacturing cost compared to the conventional manufacturing process by using a single process tube, the yield by eliminating the cause of the yield decrease due to the increase of particles and defects due to the increase in chemical vapor deposition process A large capacity capacitor can be secured in a narrow cell area by manufacturing a charge storage electrode having a hemispherical surface, which can greatly improve the operation characteristics of the device.

Claims (3)

A first step of forming an interlayer insulating film on a semiconductor substrate on which a predetermined lower layer is formed and selectively etching the interlayer insulating film to form a charge storage electrode contact hole; A second step of alternately depositing an amorphous silicon film doped with impurities and an amorphous silicon film not doped with impurities on the entire structure; A third step of selectively etching the amorphous silicon film doped with the impurity and the amorphous silicon film not doped with the impurity by using an etching mask for defining a charge storage electrode; Performing a predetermined heat treatment to polycrystallize the amorphous silicon film doped with the impurity and the amorphous silicon film not doped with the impurity, and allow the impurity to penetrate a portion of the amorphous silicon film not doped with the impurity; And a fifth step of removing an impurity diffusion portion of the amorphous silicon film doped with the impurity and the amorphous silicon film doped with the impurity. The method of claim 1, wherein the heat treatment is performed at a temperature of 650 ° C. to 750 ° C. for 30 minutes to 60 minutes. The method of claim 1, wherein the fifth step is performed using a wet etchant mixed with nitric acid, acetic acid, hydrofluoric acid, and pure water.