KR0127214B1 - Power saving circuti of a monitor - Google Patents

Abstract

A circuit for saving a monitor power is disclosed. The circuit comprises a horizontal frequency detector(203) for determining whether the frequency of the horizontal frequency signal inputted from a horizontal deriving/deflecting unit(201) of a monitor through a signal cable connected to a computer main body, is lower than a predetermined frequency; a vertical frequency detector(204) for determining whether the frequency of the vertical frequency signal inputted from a vertical deriving/deflecting unit(202) of the monitor through the signal cable connected to the computer main body, is lower than a predetermined frequency; and a saving signal generator(205) generating a standby signal or a monitor power cutoff signal according to the determination results from the horizontal deriving/deflecting unit(201) and the vertical frequency detector(204), a signal cable connecting state signal, and a BNC/DSUB connecter state signal.

Description

Power saving circuit of monitor

1 is a block diagram of a horizontal and vertical drive / deflection of a conventional monitor.

2 is a partial block diagram of a monitor employing a power saving circuit of the monitor of the present invention.

3 is a detailed circuit diagram of the horizontal frequency detector of FIG.

4 is an angular waveform diagram of FIG.

FIG. 5 is a detailed circuit diagram of the power saving signal generator of FIG.

6 is an input / output relationship table of FIG.

* Explanation of symbols for main parts of the drawings

201: horizontal drive / deflection part 202: vertical drive / deflection part

203: Horizontal frequency detector 203-1: Count period setting / count value loading unit

203-2: counter overflow clear unit

203-3: Input frequency count / comparison output section

204: vertical frequency detector 205: power saving signal generator

The present invention relates to a technique for preventing power wastage in a monitor, and in particular, even if there is no horizontal or vertical frequency signal input to the horizontal and vertical driving / deflection units of the monitor, the horizontal and vertical driving / deflection units are driven when the frequency is less than a predetermined frequency. The present invention relates to a power saving circuit of a monitor, which can prevent power waste by preventing the waste.

1 is a block diagram of a horizontal drive / deflection unit 101 and a vertical drive / deflection unit 102 of a conventional monitor, and the horizontal drive / deflection unit 101 is a horizontal drive and deflection operation by inputting a horizontal frequency signal. In addition, the vertical drive / deflection unit 102 is configured to perform vertical drive and deflection by inputting a vertical frequency signal.

The problem with a conventional monitor having such a horizontal and vertical drive / deflection is that the signal cable is disconnected between the computer body and the monitor so that there is no horizontal or vertical frequency signal inputted to the horizontal and vertical drive / deflection of the monitor. Despite the fact that the number of horizontal and vertical frequency signals is less than a certain frequency, free oscillation occurs and the horizontal and vertical driving / deflection parts are driven, thereby wasting power.

The present invention has been devised in view of such problems in the conventional monitor.

Accordingly, it is an object of the present invention to provide a power saving circuit of a monitor which can prevent power waste by preventing the horizontal and vertical driving / deflection portions of the monitor from being driven when the signal cable is separated from the monitor.

The objective of the present invention is that the horizontal and vertical drive / deflection parts are not driven even when the signal cable is separated from the monitor even when the frequency of the horizontal and vertical frequency signals input to the horizontal and vertical drive / deflection parts of the monitor is low. It is to provide a power saving circuit of the monitor that can prevent power waste.

The power saving circuit of the monitor according to the above objects comprises a horizontal frequency detection unit for determining whether a frequency of a horizontal frequency signal input from the computer main body via a signal cable to the horizontal drive / deflection unit of the monitor is less than a predetermined frequency; A vertical frequency detector for judging whether the frequency of the vertical frequency signal inputted from the computer main body via the signal cable to the vertical drive / deflection portion of the monitor is less than a predetermined frequency; and the determination result of the horizontal frequency detector and the vertical frequency detector and the monitor. It consists of power saving signal generator that generates standby signal or power orf signal depending on whether or not signal cable is connected to computer main body and whether BNDDSUBn (Binary Number Code / D-type SUBmail) connector is used. do.

The overall operation and effect of the present invention will be described in detail with reference to FIGS. 2 to 6 showing one preferred embodiment of the power saving circuit of the present invention monitor configured as described above.

In the present preferred embodiment, the power saving circuit of the monitor of the present invention inputs the horizontal frequency signal Hs input to the horizontal drive / deflection portion 201 of the monitor, as indicated by reference numeral 200 in FIG. A horizontal frequency detection unit 203 for outputting a high or low horizontal frequency detection signal hsdet; A vertical frequency detector 204 for outputting a 'high' or 'low vertical frequency detection signal vsdet' by inputting a vertical frequency signal Vs input to the monitor's vertical drive / deflection unit 202; The horizontal and vertical frequency detection signals (hsdet) (vsdet), the signal cable connection signal (STn) and the connector connection signal (BNC / DSUBn) of the horizontal and vertical frequency detection units 203 and 204 are input as standby signals or And a power saving signal generator 205 for generating a power off signal.

In this configuration, the horizontal and vertical frequency detectors 203 and 204 have constant frequency of horizontal and vertical frequency signals inputted to the horizontal and vertical drive / deflection units 201 and 202 of the monitor via a signal cable from the computer main body. If the frequency (eg, 10 [Hz]) or more, a high and horizontal horizontal and vertical frequency detection signal (hsdet) (vsdet) is outputted to the power saving signal generation unit 205.

However, when the frequency of the horizontal and vertical frequency signals inputted to the horizontal and vertical driving / deflection units 201 and 202 is less than the predetermined frequency, the horizontal and vertical frequency detection signals hsdet vsst are given. The output signal is input to the power saving signal generator 205.

In addition, a high horizontal and vertical frequency detection signal (hsdet) (vsdet) is output to the power saving signal generator 205 in a heat run condition during production. Here, the heat run means preheating each part for a predetermined time (for example, one hour) prior to various adjustments.

The power saving signal generation unit 205 also has a high or vertical frequency detection signal hsdet vsdet input from the horizontal and vertical frequency detection units 203 and 204 and a signal cable connection signal STn input from the outside. In response to the connector connection signal BNC / BSUBn input from the outside, a high or low standby signal or a power off signal is output and applied to the horizontal and vertical driving / deflection parts 201 and 202 of the monitor.

Now, the specific operation of the horizontal frequency detector 203 will be described in detail with reference to FIGS. 3 and 4. The configuration of the vertical frequency detection unit 204 is the same as that of the horizontal frequency detection unit 203, and thus the operation of the vertical frequency detection unit 204 is not described separately.

3 is an internal configuration of the horizontal frequency detection unit 203, and FIG. 4 is an operation waveform diagram of the count cycle design / count value load unit 203-1 among the horizontal frequency detection unit 203. As shown in FIG.

As shown in FIG. 3, the horizontal frequency detector 203 outputs a counter clear signal DCNT ^* CLR when one cycle of the horizontal frequency signal Hs input to the horizontal drive / deflector 201 passes. A count period setting / count value loading unit 203-1 for outputting a data load signal DATA ^* LD when the next one period of the horizontal frequency signal Hs has passed; Count operation is performed until the counter clear signal (DCNT ^* CLR) is input from the count period setting / count value loading unit 203-1, and a data load signal from the count period setting / count value loading unit 203-1. When (DATA ^* LD) is input, the count value (b) obtained by the counting operation is compared with the count value (a) corresponding to the constant frequency to determine whether the frequency of the horizontal frequency signal (Hs) is less than the constant frequency. An input frequency count / comparison output section 203-3; The counter overflow clear section 203-2 is configured to maintain the count value when an overflow occurs in the count value of the input frequency count / comparison output section 203-3.

First, the horizontal frequency signal Hs as shown in FIG. 4A to the notch knit NOT1 in the count cycle setting / count value loading section 203-1 of FIG. 3 through a signal cable (not shown) from the computer main body. ) Is inputted, the notch knit (NOT1) inverts the horizontal frequency signal (Hs), inverts the inverted horizontal frequency signal (fls) as shown in (b), and inverts the horizontal level as (b). The frequency signal Hs is generated and input to the clock terminal CK of the first stage flip-flop DFF1.

The first flip-flop DFF1 receives the inverted horizontal frequency signal Hs to generate a 1/2 horizontal frequency signal 1 / 2Hs divided in half through the inverting output terminal Q. Input to gate AND1.

The AND gate ANDl receiving the 1/2 horizontal frequency signal 1 / 2Hs receives the 1/2 horizontal frequency signal 1 / 2Hs and the inverted horizontal frequency signal delayed through the delay unit 301. Logical multiplication of (Hs) and (a) produces a pulse signal P1 that becomes high every two periods of the horizontal frequency signal Hs as shown in (a), and the clock terminal of the second flip-flop DFF2. Enter in (CK).

(2) The second flip-flop DFF2, which receives the pulse signal P1 that becomes high every two cycles of the horizontal frequency signal Hs of (A), turns the inverted output terminal Q when the pulse signal P1 is high. The second counter 302, which outputs a low signal and is applied to the clear terminal CLR of the first counter 302, receives the low signal through the clear terminal CLR, through the clock input terminal CK. The count operation is performed on the clock signal CLK / 2 input from the outside.

When the fourth count value q3 outputted from the first counter 302 becomes high as a result of the count operation, as shown in Fig. 4, the fourth count value q3 of this high is better. The second de-flip flop DFF2 is cleared by being applied to the clear terminal CDN of the second de-flip flip DFF2 through NOT4 and AND gate AND2. In the clear, the pulse signal P2 output from the output terminal Q of the second deflip-flop DFF2 becomes 'high' as shown in (bar), and this high pulse signal P2 becomes the first counter. The first counter 302 stops the counting operation by being input to the clear terminal CLR of 302.

4 to 4 show waveforms of the first counter value q0 and the fourth counter value q3 output from the first counter 302, and the first count value of the waveform. The AND signal with the clock signal CLK / 2 inverted by the (q0) to the third counter value q2 and the knock gate NOT3, in particular, the inverted gate with the first counter value q0 inverted by the knock gate NOT2. Logically multiplied by AND3 to form a data load signal DATALD via the third deflip-flop DFF3, as shown in (c) of the latch 32 of the input frequency count / comparison output section 203-3. It is input to the clock terminal CK.

And. The first, second, and third counter values q0-q2 and the clock signal CLK / 2 inverted by the knock gate NOT3 are logically multiplied by the AND gate AND4 to deflect the fourth flip-flop DFF4. The counter clear signal (DCNT ^* CLR) is input to the single input terminal of the OR gate OR2 in the input frequency count / comparison output unit 203-3 as shown in (wave).

In summary, the count period setting / count value loading section 203-1 determines how long the input frequency count / comparison output section 203-3 in the next stage should finish counting and finishing the horizontal frequency signal. In order to determine when to use the obtained count value for frequency discrimination, the counter clear signal (DCNT ^* CLR) and data load signal (DATA ^* LD) are generated.

Hereinafter, the input frequency count / comparison output unit 203-3 receiving the data load signal DATA ^* LD and the counter clear signal DCNT ^* CLR from the count period setting / count value loading unit 203-1. Will be described.

The input frequency count / comparison output unit 203-3 performs a count operation on the horizontal frequency signal until the counter clear signal DCNTCLR is input from the count period setting / count value load unit 203-1. The frequency discrimination is not performed until the data load signal DATA ^* LD is input from the count period setting / count value load unit 203-1, but when the data load signal DATA ^* LD is input, the horizontal frequency signal is input. The frequency of Hs is discriminated, and a high or low horizontal frequency detection signal hsdet is output.

That is, the second counter 31 of the input frequency count / comparison output unit 203-3 has a counter overflow clear unit 203-1 (Olgate ORl connected to the enable terminal en). The horizontal frequency signal Hs input to the horizontal drive / deflection portion 201 of the monitor in a state where the enable clear signal en ^* clr is input to 'low', more precisely, the count period. 1/2 horizontal frequency signal (1 / 2Hs) of FIG. 4 (C) output from the inverted output terminal T-1 of the first dip-flop DFF1 of the setting / count value loading section 203-1 Is input to the enable terminal (en) through the oragate (OR1).

Accordingly, the second counter 31 of the input frequency count / comparison output section 203-3 is enabled while the 1/2 horizontal frequency signal 1 / 2Hs inputted to the enable terminal en is low. While enabled, the counting operation is performed on the clock signal CLK / 2560 input from the outside through the knock gate NOT7 frame connected to the clock terminal CK.

When the counter clear signal DCNT ^* LR is input from the count period setting / count value loading unit 203-1 through the OR gate OR2 while the count operation is being performed, the second counter 31 performs the counter operation being performed. Quit.

Thus, the count value obtained by the counting operation performed by the second counter 31 over one period of the horizontal frequency signal Hs can be obtained by the following equation (1).

T-2

However, the horizontal frequency is the frequency of the horizontal frequency signal.

According to this equation (1), when using the clock signal CLK having a frequency of 4 MHz, if the horizontal frequency is 10 [Hz], the count value output from the second counter 31 is 156, and the horizontal frequency is 50 [. Hz], the count is 31. If the horizontal frequency is 120 [Hz], the count is 13.

When the actual count value output from the second counter 31 at the end of the count exceeds the limit value ( ⁸ = 256) of the octal counter (for example, when the horizontal frequency is 5 [Hz], the counter value) Is 312 in accordance with Equation (1), and since the overflow occurs, the counter overflow clearing unit 203-2 is used as the second counter 31 so that the value 312 can be used later for large and small judgments. When the count value becomes '255' by receiving the counter value (binary data) output from the input, in particular, 'q0' is input through the not gate (NOT8), and the AND logic operation is performed on the AND gate AND5. And outputting the enable clear signal (en ^* clr) through the sixth flip-flop (DFF5) (DFF ·) and the second counter through the OR gate of the input frequency count / comparison output unit 203-3. Input in enable terminal (en) of (31). At this time, the clear terminal CDN of the sixth flip-flop DFF6 is provided from the reset signal RST and the count period setting / count value loading unit 203-1 through the AND gate AND6 and the knock gate NOT12. The counter clear signal (DCNT ^* CLR) is inputted.

On the other hand, when the count value previously output from the second counter 31 is input to the latch 32, when the data load signal DATA ^* LD is input from the count period setting / count value loading unit 203-1, The latch 32 transmits the count value to the first and second comparators 33 and 34 of the comparator 35.

At this time, in the first and second comparators 33 and 34, the count value '156' (= a) corresponding to the horizontal frequency 10 [Hz] is previously set as a reference value in the above-described equation (1).

As described above, the 'preset count value' is a counter value (a = 156) corresponding to 10 [Hz] according to Equation (1). In the first comparator 33, the input terminals a0 and a3 are used. ) Is set by grounding and applying the power supply voltage Vcc to the input terminals a1 and a2. In the second comparator 34, the input terminals a0 and a2 are grounded and the power supply voltage to the input terminal a3. It is set by applying (Vcc).

On the other hand, the first comparator 33 compares the count value (= b) and the count value (a) input from the latch 32 to the input terminals b0-b3, so that the count value b is the count value ( If greater than a) (ab), a high signal is output and input to one input terminal of the AND gate AND7.

The second comparator 34 compares the counter value b inputted from the latch 32 to the input terminals b0-b3 and the count value a, and the input count value b is the count value a. Equal to (a = b), a high signal is output through the output terminal O1 and input to the other input terminal of the AND gate AND7, and when the count value b is greater than the count value a (ab) ), The high signal is outputted through the output terminal O1 to the one input terminal of the OR gate OR5.

The AND gate AND7, which receives the high signal at both input terminals, outputs a high signal and inputs it to the other input terminal of the OR gate OR5.

When the high signal is input to the two input terminals as described above, the OR gate OR5 outputs a high horizontal frequency detection signal hsdet and inputs it to the power saving signal generator 205 of FIG.

In summary, the input frequency count / comparison output unit 203-3 is set to 'low' if the frequency of the horizontal frequency signal Hs input to the horizontal drive / deflection unit 201 is less than a predetermined frequency (10 [Hz]). The horizontal frequency detection signal hsdet is output, and the horizontal frequency detection signal hsdet is input to the power saving signal generation unit 205 shown in FIG.

Now, the operation of the power saving signal generation unit 205 will be described with reference to FIG. The power saving signal generation unit 205 includes horizontal and vertical frequency detection signals hsdet vsstt input from the horizontal and vertical frequency detection units 203 and 264; A standby signal or a power-off signal is output by inputting the signal cable connection signal STn and the connector connection signal BNC / DSUBn whose high and low are determined depending on whether the signal cable is connected to the monitor.

That is, when the signal cable connection signal STn and the connector connection signal BNC / DSUBn are inputted, the signal cable connection signal STn and the connector connection signal BNC / DSUBn are subjected to an ological operation by the ORA gate OR2. The AND signal AND2 outputs the output of the OR gate OR2 and the vertical frequency detection signal vsdet input from the vertical frequency detection unit 204, and performs an AND logic operation, and outputs and knock gates of the AND gate AND2. The output of the OR gate OR2 through the NOT2) is orally logically operated by the OR gate OR4 and input to one input terminal of the NO gate NORl.

In addition, when the signal cable connection signal STn and the connector connection signal BNC / DSUBn are input to the two input terminals of the OR gate OR1, the signal cable connection signal STn and the connector are connected by the OR gate OR1. The signal BNC / DSUBn is orally-operated, and the AND of the OR gate ORl and the horizontal frequency detection signal Hsdet input from the horizontal frequency detector 203 are AND-operated by the AND gate ANDl. The output of the AND gate ANDl and the output of the OR gate ORl through the knock gate NOT1 are orally-calculated by the OR gate OR3 and are input to one input terminal of the exclusive OR gate XORl.

Therefore, the exclusive ogate XORl outputs a wait signal by exclusively summing the two gates OR3 and OR4, and the no-question NORl is connected to the two outputs of the ORA OR3 OR4. Noa operation is performed to output a power-off signal.

6 shows the standby signal and power off according to the horizontal and vertical frequency detection signals hsdet (vsdrt), the signal cable connection signal STn, and the connector connection signal BNC / DSUBn input to the power saving signal generation unit 205. This is a chart of the level of the signal.

Here, if 'STn' is '0', the signal cable of the computer main body is disconnected from the monitor, and if '1', the signal cable of the commuter main body is connected to the monitor. If 'BNC / DSUBn' is '0', DSUBn connector is connected and if it is '1', BNC is connected. In addition, if 'Hs' or 'Vs' is '1', the frequency is 10 Hz or more, and if '0', the frequency is less than 10 Hz or Hs or Vs is not input at all.

The power off signal is output from the power saving signal generator 205 as follows.

In the diagram, with the DSUBn connector connected (BNC / DSUBn → 0) and the signal cable connected (STn → 1), as shown in NO.5, the vertical and horizontal frequency signals are vertical, horizontal drive / deflector 201 If it is not inputted to 202 (Hs, Vs → 0), there are no vertical and horizontal frequency signals detected (hsdt, vsdt → 0), and a high power-off signal is output.

As in NO.9 in the table, BNC connector is connected (BNC / DSUBn → 1), and with signal cable disconnected (STn → 0), the vertical and horizontal frequency signals are vertical, horizontal drive / deflector 201 If it is not input to (202) (Hs, Vs-> 0), since there are no vertical and horizontal frequency signals detected (hsdt, vsdt->), a high power-off signal is output.

As in NO.13 in the table, with the BNC / DSUBn connector connected (BNC / DSUBn → 1) and with the signal cable connected (STn → 1), the vertical and horizontal frequency signals are vertical, horizontal drive / deflection If it is not inputted to (201) and 202 (Hs, Vs-> 0), since there are no vertical and horizontal frequency signals detected (hsdt, vsdt-> 0), a high power-off signal is output.

When the standby signal is output from the power saving signal generator 205 is as follows.

As in NO.6 in the diagram, with the DSUBn connector connected (BNC / DSUBn → 0), with the signal cable connected (STn → 1), the vertical frequency signal is input to the vertical drive / deflection section 202. If present (Vs? 1), the vertical frequency signal is detected (vsdt? 1), and a high wait signal is output. The same applies to the case of NO.7 in which the horizontal frequency signal is inputted to the horizontal drive / deflection section 20l.

As in NO.10 in the diagram, with the BNC connector connected (BNC / DSUBn → 1) and with the signal cable connected (STn → 1), a vertical frequency signal is input to the vertical drive / deflection section 202. (VS → 1), the vertical frequency signal is detected (vsdt-1), and a high wait signal is output. The same applies to the case of NO.15 in which the horizontal frequency signal is input to the horizontal drive / deflection section 201.

As in NO.14 in the diagram, the BNC connector is connected (BNC / DSUBn → 1), and with the signal cable connected (STn →) 1, the vertical frequency signal is input to the vertical drive / deflection section 202. If present (Vs? 1), the vertical frequency signal is detected (vsdt? 1), and a high wait signal is output. The same applies to the case of NO.15 in which the horizontal frequency signal is input to the horizontal drive / deflection section 201.

On the other hand, as shown in the figures NO.1 to NO.4, the DSUBn connector is not connected (BNC / DSUBn → 1), the signal cable is not connected (STn → 0), and horizontal in heat run conditions during production. Since the vertical frequency detection signal (hsdt) (vsdt) is all high, the low power off signal and the standby signal are output.

As such, when neither horizontal nor vertical frequency signals are input to the horizontal and vertical driving / deflection units 201 and 202, a high power off signal is output, and if only one is input, a high standby signal is output. In the vertical drive / deflection unit 201 and 202, there is no power waste.

Then, in the cases other than the case described above, the high power standby signal and the power off signal are not output from the power saving signal generator 205, so that the horizontal drive / deflection unit 201 and the vertical drive / deflection unit 202 are used. Will operate normally.

As described in detail above, in the present invention, when the horizontal and vertical frequency signals are not input to the horizontal and vertical driving / deflection parts, the power-off signal is output, and when only one is input, the standby signal is output, thereby providing horizontal, The vertical drive / deflection unit does not waste power unnecessarily, and even when the frequency of the horizontal and vertical frequency signals is very low, it outputs a standby signal or a power-off signal so that the horizontal and vertical drive / deflection units do not waste power even at low frequencies. Has an effect.

Claims (7)

A horizontal frequency detector for judging whether the frequency of the horizontal frequency signal inputted to the horizontal drive / deflection portion of the monitor from the computer main body via the signal cable is below a predetermined frequency; and vertical drive / vertical operation of the monitor through the signal cable from the computer main body. A vertical frequency detector which determines whether the frequency of the vertical frequency signal inputted to the deflection unit is less than a predetermined frequency, the determination result of the horizontal frequency detector and the vertical frequency detector, and whether the signal cable is connected to the monitor and the BNC / DSUBn connector Power saving circuit of the monitor comprising a power saving signal generating unit for generating a standby signal or a power off signal according to the connection. The power supply power saving circuit of the monitor according to claim 1, wherein the constant frequency is 10 [Hz]. The method of claim 1, wherein the horizontal frequency detector determines that the frequency of the horizontal frequency signal is greater than or equal to the predetermined frequency under a heat run condition, and the vertical frequency detector determines that the frequency of the vertical frequency signal is greater than or equal to the predetermined frequency under a heat run condition. Power saving circuit of the monitor, characterized in that. The power saving circuit of the monitor according to claim 1, wherein the horizontal frequency detector and the vertical frequency detector have the same configuration. The counter of claim 3, wherein the horizontal frequency detector outputs a counter clear signal after one cycle of the horizontal frequency signal input to the horizontal drive / deflection unit, and outputs a data load signal when the next cycle of the horizontal frequency signal passes. A cycle setting / count value loading section; When the data load signal is input from the count period setting / count value load unit, an input frequency for comparing the count value obtained by the count operation with a count value corresponding to the constant frequency to determine whether the frequency of the horizontal frequency is less than the constant frequency A count / comparison output unit; And a counter overflow clearing unit for maintaining the count value when an overflow occurs in the count value of the input frequency count / comparison output unit. According to claim 1, wherein the power saving signal generation unit is input a horizontal frequency signal of less than a certain frequency in the horizontal drive / deflection unit according to the determination result of the horizontal frequency detector and the vertical frequency detector, and at the same time less than the constant frequency in the horizontal drive / deflection unit Outputs a power-off signal when a vertical frequency signal is input, and a horizontal frequency detection signal of less than a certain frequency is input to the horizontal drive / deflection unit or a vertical frequency detection signal of less than a certain frequency is input to the vertical drive / deflection unit. A power saving circuit of a monitor, characterized by outputting a standby signal. 7. The power saving signal generating unit according to claim 1 or 6, wherein the power saving signal generating unit comprises an oragate ORl (OR2) which performs an ological operation on the signal cable connection signal and the connector connection signal, and an output and a horizontal frequency of the oragate ORl, respectively. An AND gate ANDl that performs an AND logic operation on a detection signal and an AND gate AND2 that performs an AND logic operation on a vertical frequency detection signal with the OR gate OR2, and a nat gate for inverting the outputs of the OR gate ORl. (NOTl), a natgate (NOT2) for inverting the output of the oragate (OR2), and an oragate (OR3) for oranically performing an output of the natgate (NOTl) and an output of the AND gate (ANDl). And an oragate OR4 that performs an oron operation on the output of the natgate NOTZ and the output of the AND gate ANDZ, the output of the oragate OR4 and the output of the oragate OR3. Logical operation of the NOA gate NOR1 and the OR gate OR4 And an exclusive oragate (XORl) for performing an exclusive anoresis operation on an output and an output of the orate (OR3).