KR0125266B1 - A method of determining contact quality and line integrity in a tft/lcd array tester - Google Patents

Abstract

The present invention relates to a method and apparatus for electrically inspecting an electrical inspector, in particular a thin film transistor liquid crystal tray (TFT / LCD), in accordance with the method and contact characteristics for determining contact characteristics for pads in a TFT / LCD array. By estimating the obtained waveform, it is for identifying the specific shape according to the defect of the TFT / LCD.

The present invention applies a gate pulse to a known gate line having completeness; Observe the presence of a corresponding signature pulse on the data line to indicate that the data line is continuous; In the same way, the TFT / LCD array can be inspected by examining the data lines continuously to determine the right and leftmost data lines and estimating all gate lines using the right and left data lines with completeness. have.

Description

How to determine contact characteristics and line integrity in thin film transistor / liquid crystal display (TFT / LCD) array inspectors

1 is a schematic / partial perspective view of an arrangement checker system according to the invention using the described method.

2 is an enlarged schematic plan view of a substrate including a thin film transistor / liquid crystal display array.

3 illustrates a method of arranging openings within data lines of the array of FIG.

4 illustrates a method of placing openings in the gate lines of the array of FIG.

5 shows an array inspector waveform that is characteristic of normal operation.

6 shows an array inspector waveform characterized by the absence of a gate contact.

7 shows an array inspector waveform that is characteristic of an opening line.

8 illustrates an array inspector waveform that is characteristic of resistive cross defects.

9 illustrates an array inspector waveform that is characteristic of adjacent shorted lines.

FIG. 10 is a generalized flowchart for inspecting an array of the type shown in FIG.

11 is a flowchart for explaining a control procedure for the apparatus of FIG.

FIG. 12 is a flowchart useful for analyzing the waveforms of FIGS. 5-8 to determine if there is a defect and if so, its nature.

13 is a generalized timing diagram illustrating an operation using interleaved timing.

FIG. 14 is a flowchart similar to FIG. 11 for operation using interleaved timing.

* Explanation of symbols for main parts of the drawings

10 substrate 12 TFT array

14 substrate holder 18 alignment pin

20: data line 22: data line pad

24: gate line 26: gate line pad

28: conductivity test probe 32: cable

34: data line drive / sensing unit 44: gate line drive unit

46: inspection controller 52: computer

60: connection ring 64: resistive element

66: inspection line 67: inspection pad

68: Isolator 68A: Isolator

The present invention relates to an electrical inspector. In particular, the present invention relates to methods and apparatus for electrically inspecting thin film transistors / liquid crystal arrays (TFT / LCDs).

The array inspector described in US Pat. No. 5,179,345 provides a means for comprehensively inspecting all cells in a TFT / LCD array using only the edge connection of the array. The basic inspection performed by the array inspector writes charge onto the cell (by good biasing the gate and data line), stores the charge on the cell by biasing off the gate, connects the charge integrated circuit to the data line, By biasing the gate line, the retained charge of the cell is read to measure the charge transferred to the charge integrated circuit to determine the final value of the charge.

Electrical inspection of many arrays inherently embedded in a TFT / LCD display at some stage prior to the attachment of the line drivers requires contacting a large number of pads (typically thousands). Contaminants (such as residual photoresist, oxide film, etc.) and uneven substrates can interfere with good electrical connection between the tester probe and the array pad. In order to ensure the usefulness of many tests that write charges to selected pixels and read charges from selected pixels, it is necessary to determine whether or not the inspector probes will actually contact the array pads.

There are various mechanical methods to ensure electrical contact with the pads. However, they require the use of additional probes to determine at least one mechanical action, completeness of electrical contact or mechanical wear of the pads or gate lines between the pads and the probes. This procedure is wasteful and time consuming, and these procedures can provide the possibility of an array malfunctioning during inspection. Thus, various electrical integrity checks are generally required to contact the pads, and it is highly desirable to be able to use only probes used in the general manner described in the patents mentioned above.

It is an object of the present invention to provide a method for determining contact characteristics for pads in a TFT / LCD array.

Another object of the present invention is to identify specific types of defects in the TFT / LCD array by evaluating the electrical waveform obtained according to the contact characteristics.

Prior to applying the present invention, the TFT / LCD array applies a driving pulse to the driving ends of the gate lines, and the first data line near the driving end and the first end of the end opposite the driving end to indicate that the gate lines are continuous. Observe the presence of a corresponding signature pulse on the two data lines; Examine the gate lines continuously to determine the topmost and bottom most consecutive gate lines in the same manner; It is checked by evaluating the completeness of all data lines by using the top and bottom gate lines with completeness.

The method applies a gate pulse to a known gate line with completeness; Observe the presence of the corresponding signature pulse on the data line to indicate that the data line is continuous, and examine the data lines continuously to determine the right most and left most consecutive data lines in the same way. The TFT / LCD array can be examined by evaluating the integration of all gate lines using the rightmost and leftmost data lines with completeness.

The present invention contemplates the use of data regarding the integrity of gate lines and data lines to isolate at least one defective line and contact defects to the line.

According to the present invention, a method for checking probe contact integrity with electrodes of a TFT / LCD array includes providing a conductive connection ring for an electrode; Providing an electrical connection between the connection ring and each of these electrodes; Electrically applying conductive probe contacts to at least two of the electrodes; Applying a voltage between the at least two probe contacts; And measuring a current between the at least two contacts to determine a property of electrical continuity between the probe contacts and the electrodes. The electrical connection is made by a high resistance element.

The invention further includes a method of checking probe contact integrity for electrode connection regions of a TFT / LCD array having gate lines and data lines, the method intersecting and insulating from the electrodes. Providing a conductive line adjacent to said row of connection regions; Providing a small capacitance between the line and each of the electrodes; Placing a conductive probe in contact with each of the connection regions; Continuously applying a voltage pulse to each of the connection regions through the probe; And observing the presence of a signature pulse on the line for each applied pulse to determine a characteristic of the electrical connection between the probe and the connection regions.

The invention also includes a method of inspecting a TFT / LCD array having a data line and a gate line, the method comprising applying a pulse to one of the gate lines; Integrating a final signature pulse on a continuous line of data lines to obtain an integral waveform; And observing the integral waveform to obtain information regarding the functional minimum level of the TFT / LCD and the contact characteristics for the lines.

Referring to FIG. 1, the upper planar surface 16 is placed on the substrate hole diagram 14 at a position where the substrate 10 on which the TFT array 12 is formed is selected by at least three alignment pins 18. Supported. The substrate 10 has a large number of data lines 20 for driving a TFT / LCD array. Each data line terminates at a data line electrode or data line pad 22. In addition, a large number of gate lines 24 terminating from the gate line electrodes or the gate line pads 26 are formed in the substrate 10.

Each data line pad 22 is contacted by a conductive test probe 28 extending from the data line probe holding fixture 30. The cable 32 contacts each test probe 28 to a drive circuit in the data line drive / sensing unit 34. Each gate line pad 26 is contacted by a conductive probe 38 extending from the fixture 40. The cable 42 has wiring for connecting each probe 38 to each gate line driver in the gate line unit 44. The manner of operation of data line drive / sensing unit 34 and gate line drive unit 44 is described in detail in the above-mentioned US patents issued to Jenkinds and Wisnieff.

The data line / sensing unit 34 and the gate line driving unit 44 are controlled by the inspection controller 46. The controller 46 includes a series of latches, registers, memory buffers, and control logic so that various gate lines 24 and data lines 20 may be appropriately sequentially activated. In particular, commands are sent to the inspection controller 46 as to how to perform the inspection, such as the voltage to be popular, the lines to be activated and the time and length of activation. The controller 46 sequences the operation of the circuits in the gate line drive unit 44 via the bus 47, and the interaction with the data line drive / sensing unit 34 is via the bidirectional bus 48. In particular, there is a facility for obtaining signals from analytical data lines in the manner described below.

The inspection controller 46 is connected to the computer 52 by a bidirectional bus 50 by a standard digital interface board 54 disposed inside the computer 52. The computer 52 can be any one of many personal computers, such as the IBM PS / 2 modem 80 with appropriate software to help program in the C language to achieve the functions described below. The computer 52 is connected to a large capacity data storage device 56 such as a magnetic disk array known in the art.

Referring to FIG. 2 for a more detailed description of the substrate 10, the connecting ring 60 on the upper surface of the substrate 10 forms a continuous conductive loop. The connection ring 60 is electrically connected to the connection ring contact or pad 62 to provide a convenient location for electrical connection of the connection ring contact or pad. Each data line pad 22 and gate line pad 26 are electrically connected to a connection ring 60 through an electrically resistive element 64. Device 64 is preferably a high resistance, 1000 megohm thin film (silicon plane) resistor, but a pair of back to back diodes or thin film with connections that allow for good resistance. It may be a transistor. Those skilled in the art will clearly understand that the conductive connection ring 60 and the resistive element 64 are not required if the substrate 10 is assembled with a second substrate, spacer, liquid crystal material and seal. will be. In other words, the substrate 10 can be cut to remove these devices.

One method for checking probe contact with the array pad is to apply a DC voltage to the selected gate line or data line probe and measure the current flowing in the connection ring 60. The complete circuit is made of a probe that contacts pad 62. When the probe is in contact with the gate line or data line pad, if a voltage of 1 volt is applied to the probe, a current of about 1 nA will flow through the connection ring. If the probe is not in contact with the pad, a negligible current of 1 pA will flow.

Various methods of eliminating the need for contacting the short ring 60 are by measuring the current flowing between each adjacent pair of probes. If both probe contacts are good, the final current is about half of the above value since the current now flows through the two resistive elements 64 detected. If either probe does not touch the pad, the current is again negligible. By comparing the current when successive pairs of probes are measured, the bad contact (or contacts) are easily separated. For example, if negligible current appears in two adjacent pairs, the probe common to both pairs is separated as bad contacts, in general, n + 1 consecutive bad pairs separate n consecutive bad contacts. Let's do it. However, this change could not detect a single good probe contact sandwiched between two bad contacts. This method will not be able to detect a bad contact between the gate line pad and its respective probe.

The substrate 10 of FIG. 2 also includes a structure that allows the use of other methods to determine probes for pad contact properties. An inspection line 66 to be in the form of a conductive loop is connected to the inspection pad 676. Line 66 is insulated from pad 22 by a series of insulators 68. Thus, a small capacitor is formed between each pad 22 and line 66. Alternatively, as shown for pad 26, an insulating layer or series of other insulators 68A may be formed over line 66, and pads 26 extend over insulator 68A. It is possible to have each of the extension portion 26A to form a capacitor. Moreover, line 66 may be formed under isolator 68A and extender 26A.

This alternate structural inspection line 66 may be connected via a pad 67 to a detector of the type described in the above-mentioned patent that can recognize the signature of a good working probe for pad contact. Thus, if desired the properties of the probe to pad contact can be checked without the connection ring 60.

Conductive line 66 may also be disposed in the fan-out area of the gate and data lines, that is, between the pads 22 or 26 and the TFT / LCD array 12. In this case, it is possible to determine whether there is an opening in the region of the gate line or data line adjacent to each pad via a capacitor formed between the gate line or the data line and the line 66.

Referring schematically to FIG. 3, vertical data lines 20 emerge from pads on the top and bottom of the substrate. Gate line 24 emerges horizontally from the pads on the left and right edges. The thin film insulator insulates the gate and data lines that cross each other, forming an overlap capacitor. Electrical pulses can be applied to individual gate lines at their edge connectors. This pulse is capacitively coupled to the data line and sensed by a circuit connected to the data line. Many data lines ejected across the display can be sampled in parallel, and their waveforms can be analyzed. The normal waveform sensed at the data line crossing at each end of the gate line demonstrates that the gate line is continuous. This procedure can be repeated for all gate lines. Two gate lines identified as good, one near the top of the display and the other near the bottom of the display, are then used for data line inspection. In this case all data lines are sensed and their contacts and continuity verified. Various malfunction mechanisms (short circuits of lines, bad connections to lines, line damages) can also be determined from this inspection as described in more detail below.

Thus, in FIG. 3 a pulse is applied to the driving end of the gate line. If the end of the corresponding signature pulse on the first data line near the drive end and the second data line at the end opposite the drive end is observed, this indicates that the gate line is continuous. Successive gate lines are examined in this manner to determine the top and bottom consecutive gate lines. Finally, the completeness of all data lines is evaluated by using the top and bottom gate lines with completeness. In FIG. 3, data lines 3 and 4 are identified as having openings by this method. A sense amplifier of the type described in the above-mentioned US patent is connected to the defective data lines 3 and 4, and gate line pulse excitation is sequentially applied to the gate line starting from the upper gate line. This is a normal excitation procedure, and no special logic is needed to determine the sequence of operation of the gate line driver. Note that the position at which the data line response varies from normal to zero defines the position of the opening in the data line. For data lines sensed at the top (such as data line 3), the response after gate line 2 is deactivated changes from normal to zero, and data sensed below (such as data line 4). The response to the line changes from zero to normal (when gate line 5 is activated).

In the alternative, if additional logic can be used to control the degree of gate line driver excitation, there is a certain number of search algorithms that can be used to find the opening position. One example is to use the Newton half interval algorithm.

Referring to FIG. 4, the gate line 3 has been identified as having an opening by the method described above with reference to FIG. Gate line pulse excitation is applied to gate line 3. Reactions on various data lines are observed as determined by sense amplifiers connected through multiplex switches as described in the above-mentioned US patent. A second gate line pulse is applied for the next setting of the multiplex switch and the responses of all sense amplifiers are stored. This procedure continues until sensing is done for all data lines. The position at which the reaction changes from normal to zero indicates the position of the opening in the gate line in a manner similar to that described above with respect to FIG.

5-9, when a pulse is applied to one of the gate lines, the last pulse with a particular signature will appear continuously in one of the data lines. The pulse can be integrated using the sensing circuit described in the above-mentioned US patent. The pulse, or preferably the waveform finally integrated from the pulse, can be analyzed to obtain information regarding the functional minimum level of the TFT / LCD and the contact characteristics for the lines.

In order to inspect a TFT / LCD array, it is important to assess whether there is a defect and if so, the nature of the defect. One approach is to digitize the entire waveform. This has become quite expensive in terms of time to acquire the data, memory required to store the data and time needed to analyze the data. Surprisingly, it has been found that this procedure can be automated by sampling the waveform at various points in time. In particular, each waveform has a time A before application of the gate pulse, a time B just after that time, and a time C at the approximate center of the gate pulse (actually for a normal waveform in which the total voltage change is shown in FIG. 5). Sampled at time D just before the end of the gate pulse and time E just after the end of the gate pulse. Although this general description of time is fairly accurate, the actual sampling time is adjusted for various widths of gate pulses, various designs of TFT / LCD arrays, and particularly various pixel designs. Moreover, time is chosen to facilitate the analysis performed as described below with respect to FIG. 12.

Referring to FIG. 10, a generalized sequence for inspecting a TFT / LCD array is shown. If the computer 52 receives the start command in step 70, the program proceeds to step 72 where a line check is performed. Data points are obtained along the length of each gate line. In step 74, a search is performed for normal gate lines at the top and bottom of the panel. However, data is obtained and stored for every gate line. In step 76, two gate lines with completeness are used to obtain data on all data lines. In step 78 the data obtained is used to characterize the data lines. Waveforms of the type shown in FIGS. 5-9 are obtained and analyzed in the manner described below in more detail with respect to FIG.

In step 80, the panel is scanned to cross the short. In the case of a short, the waveforms of the type shown in FIG. 8 will appear, but the voltage drop will be more pronounced. By comparing the voltages at points A and E and indicating a large difference, the presence of a short is detected, it is advantageous to do this early in the entire inspection sequence for the TFT / LCD array. If a reasonable number of shorts appear, the array will immediately be determined to be defective and the test will end.

In step 82, the panel is scanned to collect data on cell charge conservation of individual cells. The way this is done is described in more detail with reference to FIG.

In step 84, waveforms for individual cells are collected. In step 86, a check is performed to obtain a characterization curve for the thin film transistor. The manner in which steps 84 and 86 are performed is fully described in the above-mentioned US patent.

In step 88, the inspection for the given TFT / LCD array is finished. The substrate is removed from the inspector. Then a new substrate 10 having the TFT / LCD array to be inspected is placed on the substrate holder 14 (FIG. 1). Upon receipt of the appropriate command by the computer 52, the inspection sequence for the new substrate starting at step 70 is repeated.

FIG. 11 shows a control sequence for the apparatus of FIG. 1 accomplished with the program term of FIG. In step 100, all outputs from the digital interface board 54 (FIG. 1) to the inspection controller 46 are initialized by being set equal to a predetermined logic level (e.g., logic zero state). In step 102, a so-called hand shaking latch in the inspection controller 46 is cleared. This handshaking latch responds to a register that can only be reset by software so that hardware and software are synchronized and functions can be performed in hardware while other operations occur in software.

Step 104 is a mode selection step. If the so-called single cell mode is selected (steps 84 and 86 in FIG. 10), repeat measurements are generated on a single pixel. Curved bacteria can occur or waveforms can be analyzed. When the so-called scanning mode is selected, the inspection is performed at all times (read selection), and the number of gate lines in the inspection increases by one. For example, scanning modes such as charge retention checking on all pixels on the panel should be used. Because of the automatic sequence across the gate lines, it is unnecessary to manually select the gate lines in the scan mode.

In step 106, a logic operation is performed to clear all data in the shift register driving the gate lines. Then a subroutine called go gate set automatically increments the logic 1 signal through the shift register when the scan mode of step 104 is selected, or the pulse is applied to the correct gate line when the single cell mode is selected. Increment the logic 1 signal through the shift register to the proper position. Then another subroutine called do gate end ensures that the appropriate gate line is activated by checking the handshaking latch, thus ensuring the completion of this process before the check begins.

In step 108, all test parameters selected by using the computer 52 are sent to the test controller 46 by operation of the digital interface board 54 and transmission by the bus 50. These values are latched into the appropriate registers by the control check controller 46.

In step 110, the address in the memory buffer at the check controller 46 is set to a value of 000 to proceed with the check.

In step 112, the appropriate multiplexer is turned on to proceed with the test. As a result, even or odd data line drivers of the type described in the above patents and respective sensing circuits are selected.

Steps 100 through 112 are common to almost all forms of inspection to be performed. However, in step 114 a particular type of test is selected. For example, if a waveform check is made to obtain a waveform of the type shown in FIGS. 5-9, the analog-to-digital converter operates to sample the waveform at time, A, B, C, D, and E. It is necessary to specify the time to be. Thus, a sampling time of TCONV. Is sent to the latch in the inspection controller 46. This may be the last data of the data needed to specify the conditions needed to perform the test.

In step 116, the check is actually done. Once all necessary circuitry is activated, the appropriate gate pulses are provided, the data voltage is turned on, reading is performed by the analog-to-digital converter, and the final digital data is stored in a memory buffer in the inspection controller. The actual nature of the tests performed is described in detail in the above patents.

In step 118, a determination is made as to whether the inspection is complete. If the check is not complete, program branches return to step 114 where TCONV. Is incremented and the check is performed again. The test is performed at T _conv. It is done repeatedly.

When the test ends, a branch to step 120 occurs. In step 120, a calculation is performed to determine whether to store the desired data in memory. All data may be required for a complete scan of the panel. However, for individual cells only selected data may be required since a large number of cells are checked at the same time. The calculation at step 120 also determines whether the data is an odd data buffer or an even data buffer. In step 122, according to the calculation in step 120, an even or odd data buffer is selected. Finally, the data read from the data buffer in step 124 enters the computer 52 via the bus 50 and the digital interface board 54.

In accordance with the present invention, FIG. 12 is used to analyze the integral waveform obtained by the method outlined in the above-mentioned US patent. The general shape of the waveform can be obtained as shown in FIGS. 12 illustrates the execution of step 78 of FIG. 10 in detail.

Referring to FIG. 12, symbols represent logic and operations, and expressions are in parentheses. To simplify the discussion, the letters A, B, C, D, and E are used to indicate voltage levels at times A, B, C, D, and E, respectively. The difference between the voltage levels is DIFF1, DIFF2... Characterized for DIFF8, the values for a typical panel are specified in FIG. 12 with one count equal to about 2.5 millivolts, for example.

When proper initialization of the software takes place, the operation is initiated in step 200. In step 202, initial characteristics of the waveform are performed. It is based on the voltage relationship at A, B, C, D, and E. If the mathematical conditions described herein match the data obtained from the data line connected to the cells at both ends of the data line, then branching to step 204 occurs. In other words, there must be five different conditions for the two selected pixels to generate a branch to step 204. Difference DIFF1, DIFF2 used in FIG. Once DIFF8 has been determined for the characteristic TFT / LCD array to be inspected, certain general waveform characteristics are required for the operation to be judged normal (FIG. 5). For example, in normal cases, the difference in voltage between point A and point B should be significant. In particular, the voltage at point A (A in this discussion) should be at least (more positive) higher than the voltage at point B (B in this discussion) by at least DIFF1 (eg, 40 counts). B must be at least as high as C by DIFF2 (for example, 70 counts). Thus, they must drop the voltage from point B to point C more steeply than from point A to point B. But C needs to be larger than D-DIFF3. In other words, the voltage between point C and point D should be relatively constant. Also, the voltage at point D must be less than the voltage at point E. Finally, the voltage at point A is less than the voltage at point E + DIFF5 (eg, 80 counts).

In step 204, two additional checks are made on both lines. First, A must exceed E-DIFF6 (eg, a relatively small change of 30 counts). Also, A must be less than E + DIFF7 (100 counts). If all of these conditions are met, a branch to step 206 occurs, where it is determined that the signal is normal and the waveform is terminated at step 210. However, if the condition of step 204 is not met, the program branches to step 208. The waveform is identified as the form of FIG. 8, which is a characteristic of the resistive crossover, provided that the gate line and the data line are relatively high impedance short circuits. The analysis then ends at 210.

If the condition in step 202 is not met for both lines, then branching to step 212 occurs. In step 212, if two first and fourth conditions of the five conditions specified in step 202 are satisfied for only one line, then branching to step 214 occurs. At step 214, a determination is made whether D + DIFF4 (e.g. 60 counts) is less than E. If this case is for both lines, then branching to step 216 occurs. The decision tree leads to the identification of the waveform of FIG. 9 and indicates the identification of shorted adjacent data lines. The analysis ends at step 210.

If the condition of step 214 is not met for both lines, then branching to step 218 occurs. The waveform of FIG. 7 is identified with a broken data line representation. The analysis ends at step 210.

If the condition specified in step 212 is met for at least one line, then branching to step 220 occurs. Five conditions are checked in step 220. These are A less than B + DIFF3 (20 counts), B less than C + DIFF3 (60 counts), C less than D + DIFF3 (20 counts), D less than E + DIFF3, and A Is less than E + DIFF3. If these conditions exist for both lines, then branching to step 222 occurs. This represents the basic flat waveform of FIG. 6, indicating that there is no contact of each gate pad by the gate probe. This condition is identified and analysis ends at step 210.

In step 220, branching to step 224 occurs if all five conditions are not met for both lines. The check determines for which line A is greater than E + DIFF (800 counts). If this is the case, for step 80 of FIG. 10, a branch to step 226 occurs as described above, and the presence of a short is indicated. The analysis ends at step 210.

If the conditions specified in step 224 are not met for any line, then branching to step 228 occurs. This indicates that waveforms other than those shown in FIGS. 5 to 9 appear. Waveforms of known type are inspected according to the manual and treated as defective until a determination is made that constitutes an acceptable deviation or whether the TFT / LCD array needs to be considered defective.

Thus, the flowchart representing the decision tree used in FIG. 12 provides the maximum efficient way possible to characterize the waveform received from the sensing circuit. Since the waveforms are only sampled at a few points, the analysis is performed by a simple software method.

Since each cell in turn needs to hold a charge at frame time (16.7 msec) before being sampled, it is slow to manipulate all pixels in the display as described above. Even when using multiple detectors to inspect a set of pixels along a selected line, this takes several minutes per array. For example, the time required to sequentially perform a single write-hold-dollar cycle for all pixels in a VGA display (480 × 640 × 3) using 120 sense channels is more than 2 minutes, and many tests require multiple Requires a cycle. The entire array is inspected in a manner described below, 10 to 100 times faster than sufficient time for use in a prefabricated production line.

As described in the above patent, the array inspector writes charge on the storage capacitor of the pixel by pulsed the gate line while holding the data line with a voltage specified above ground potential. After a period of time, referred to as hold time T _H , the charge from the pixel capacitance is read by pulsing the gate line while integrating the data line current in the sense integrator. The hold period is needed to check for charge loss. The final value of the integrator has a known relationship to the cell charge. When all the pixels are checked sequentially, the pulse write for gate line G _{n + 1} cannot be started until the pulse on gate line Gn is read.

The order of a simple write-hold-read in which multiple read-write cycles have been performed is changed during the hold time by interleaving the same number of reads and the number of writes. The timing for this is shown in FIG. If the number N of write operations is performed, after the hold time T _H , the same N cells are read in the same order as they were written. Assuming that the write time and read time are equal to γ, then Nγ + T _D = T _H (where T _D is an appropriate delay and may be zero). Usually, the hold time T _H is equal to the frame time (commonly 16.7 ms) but is not required. The above equation determines the number N sets that can be recorded within the holding time T _H. Finally, it is necessary to provide a buffer structure so that the charge data is stored without interruption, and to keep the checker at a constant reading time interval.

The charge is actually read from the first set of pixels at time T _H after they are written and until all N sets are read. Each time the charge is read from the set of pixels along the selected gate line and placed in the data buffer. After N sets of first blocks are placed in the buffer, the contents of the buffer are transferred to the storage medium along the high data rate path. The full array check is processed until all the gate lines are evaluated by checking the N blocks of the first block following the second block.

The instruction from the computer 52 (FIG. 1) initializes the charge write order by the charge read order for the 1N set. Data from the integrator is converted to digital form and placed in the data buffer. Buffer size (bytes) S = BxNxC, where B is the number of bytes required to store the read from one cell and C is the number of sense channels operating in parallel. The hardware is designed to transfer the data independently from the data buffer and write the charge to the pixels so that the buffer data can be transferred to the computer 52 during the next write operation simultaneously. The charge in the N sets of second blocks is ready to be read and placed in a buffer and sent to the computer 52.

Referring to FIG. 14, a control sequence for the interleaving operation is described, except for the following, which indicates a corresponding operation with a similar reference number 200 units higher than that used in FIG. Descriptions not added to these steps are described below.

In step 313, recording or transfer of charge to the block of cells is initiated. In step 314, a determination is made whether the desired number of gates have been activated to complete the block. If the block is not complete, the program branches back to step 313. Upon completion of the block the program branches back to step 315.

Note that a parameter is applied from the computer 52 to the inspection controller 46 to specify the number of gate lines to be activated in the block as part of the operation performed in step 308 for interleaving.

In step 315, the charge written into the cell of the selected block during step 313 is read out, and the appropriate data is stored in the buffer. In step 316, a determination is made as to whether the entire block has been read and data is stored. If the read operation has not ended, the program branches back to step 315.

Upon completion of the read and store operations, the program branches to step 317 where the buffer address is set to 000.

In step 318, an even data buffer is selected. At step 319, data from the buffer is read into computer 52.

In step 322, an odd data buffer is selected. At step 324 data is read into computer 52 from an odd data buffer.

At step 325, a determination is made whether all blocks have been examined. If all blocks have not been checked, the program branches to step 313, and the sequence of steps 313 to 325 is repeated. This happens for the number of blocks required to examine the entire array.

At step 326, a determination is made whether all multiplexer switch types have been used for inspection. If all states have not been used, the program branches to step 312, another multiplexer is used, and the check sequence starting at step 313 and ending at step 326 is repeated. This happens for a number of times equal to the number of multiplexer locations when all locations of the multiplexer are used for ending the test sequence.

While the invention has been particularly shown and described with respect to preferred embodiments, it will be understood by those skilled in the art that changes may be made without departing from the spirit and scope of the invention.

Claims (13)

A method for checking probe contact integrity with electrodes on a TFT / LCD display includes providing a conductive connection ring for the electrodes, providing an electrical connection between the connection ring and each of the electrodes. For providing conductive probe contacts to at least two of the electrodes, applying a voltage between the at least two probe contacts, and electrical continuity between the probe contacts and the electrodes. Measuring the current between the at least two contacts to determine a characteristic of the method. The method of claim 1 wherein the electrical connection is made by one of a high resistance, at least one diode and at least one thin film transistor. A method for checking probe contact integrity on an electrode connection area on a TFT / LCD display with gate lines and data lines intersects with and insulates the electrodes, adjacent to the row of the connection area. Providing a conductive line, a small capacitance between the line and each of the electrodes, disposing a conductive probe in contact with each of the connection regions, each of the above through the probe Continuously applying a voltage pulse to the connection regions, and observing the presence of a signature pulse on the line for each applied pulse to determine a characteristic of the electrical connection between the probe and the connection region. Characterized in that. A method for inspecting a TFT / LCD having data lines and gate lines includes applying a pulse to one of the gate lines, integrating the final signature pulse on successive lines in the data line to obtain an integral waveform. And observing an integral waveform to obtain information about the minimum functional level of the TFT / LCD and information about the contact characteristics of the lines. 5. The method of claim 4, further comprising interpreting the waveform as having a contact defect with the data line or the gate line when an integral waveform is observed and no voltage output is shown. 5. The method of claim 4, further comprising interpreting the waveform as either an opening gate line or an opening data line if the voltage at the beginning and end of the pulse has only two small changes when an integral waveform is observed. Method comprising a. 5. The waveform of claim 4, wherein when an integral waveform is observed, the waveform comprises one of a smaller integral voltage and a voltage representing the saturation of the integrator amplifier, wherein the waveform is characterized by a conductive intersection between the gate line and the data line. Further comprising interpreting. 5. The method of claim 4, wherein when the integral waveform is observed, the waveform includes a low impedance response and further comprising interpreting the waveform as having a short between adjacent lines. An apparatus for inspecting a TFT / LCD array having gate lines and data lines, and for classifying defects, for activating cells in the array by applying gate pulses to the gate lines and pulses to the data lines. Means, means for obtaining a waveform from data lines of the array, means for sampling the waveform at a selected time point, and detecting the presence of a defect, and comparing the voltage of the waveform at the selected time point to indicate the nature of the defect. Means for classifying the waveform to produce. 10. The apparatus of claim 9, comprising means for selecting five viewpoints. 11. The apparatus of claim 10, wherein the five time points are selected before the gate pulse, after the start of the gate pulse, substantially at the center of the gate pulse, before the end of the gate pulse and after the end of the gate pulse. 10. The apparatus of claim 9, wherein the array is inspected by placing charge in successive blocks of the array and reading each block before writing to the next successive block. A substrate comprising a TFT / LCD having gate lines, data lines and connection pads for the gate lines and the data lines, the substrate intersecting the pads such that a capacitor is formed between each of the pads and the conductive line. However, the substrate comprising conductive lines arranged to be insulated from the pads.