KR0123423B1 - Lead frame of semiconductor - Google Patents
Lead frame of semiconductorInfo
- Publication number
- KR0123423B1 KR0123423B1 KR1019940010938A KR19940010938A KR0123423B1 KR 0123423 B1 KR0123423 B1 KR 0123423B1 KR 1019940010938 A KR1019940010938 A KR 1019940010938A KR 19940010938 A KR19940010938 A KR 19940010938A KR 0123423 B1 KR0123423 B1 KR 0123423B1
- Authority
- KR
- South Korea
- Prior art keywords
- lead frame
- semiconductor
- mold
- mounting plate
- tie bar
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
제1도는 본 발명의 리드프레임 개략평면도.1 is a schematic plan view of a leadframe of the present invention.
제2도는 타이바의 요부확대도.2 is an enlarged view of the tie bar.
제3도는 탑재판의 요부확대도.3 is an enlarged view of the main part of the mounting plate.
제4도는 인너리드 요부확대도.4 is an enlarged view of inner lead.
제5도는 종래의 일반적인 리드프레임.5 is a conventional general leadframe.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 리드프레임 2 : 타이바1: lead frame 2: tie bar
3 : 구멍 4 : 내부리드3: hole 4: inner lead
5 : 탑재판 6 : 반도체 및 PCB5: mounting plate 6: semiconductor and PCB
본 발명은 반도체의 리드프레임에 관한 것으로서, 특히 반도체 칩과 인쇄회로기판(PCB)을 연결시켜 주기 위한 리드프레임(LEAD FRAME)의 타이바에 구멍을 형성하고, 탑재판 외주연부에는 파형형상을 갖도록 하며, 내부리드에는형의 형상을 갖도록 하며 크기가 큰 반도체 칩 및 인쇄회로기판의 접착시 반도체의 패키지몰드성을 좋게 한 반도체의 리드프레임에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame of a semiconductor. In particular, a hole is formed in a tie bar of a lead frame for connecting a semiconductor chip and a printed circuit board (PCB), and the outer periphery of the mounting plate has a wave shape. Inside the lead The present invention relates to a lead frame of a semiconductor having a mold shape and having a good package moldability of the semiconductor when bonding a large semiconductor chip and a printed circuit board.
일반적으로 리드프레임은 반도체 칩과 인쇄회로 기판을 연결시켜주고 반도체회로를 보호하기 위한 패키지몰드를 구비하도록 한 것으로서, 종래에는 도시된 도면 제5도에서와 같이 리드프레임(1)에 반도체 칩 및 PCB(6)을 부착시킬 수 있는 탑재판(5)과 이 탑재판(5)을 잡아주기 위한 타이바(2)와 반도체 칩의 패드와 연결하기 위한 리드등으로 구비되어 있으나 반도체 칩이 크거나 또는 PCB를 부착하는 경우 내부리드(4)의 외부측으로 많은 면적을 침범하여 패키지몰드되는 범위를 축소시킴에 따라 상대적으로 패키지몰드 접착력을 약화시키므로서 완제품의 회로부에로 습기등이 쉽게 침투하여 누설전류가 흐르게 되어 반도체의 불량이 발생하게 되어 신뢰성에 많은 문제점이 있었다.In general, the lead frame includes a package mold for connecting the semiconductor chip and the printed circuit board and protecting the semiconductor circuit. In the related art, the lead frame 1 includes a semiconductor chip and a PCB in the lead frame 1 as shown in FIG. (6) is provided with a mounting plate (5) to which it can be attached, a tie bar (2) for holding the mounting plate (5), and a lead for connecting with a pad of the semiconductor chip, but the semiconductor chip is large or In the case of attaching the PCB, it invades a large area to the outside of the inner lead 4 and reduces the package mold range, thereby weakening the adhesion of the package mold relatively. There was a problem in the reliability caused by the failure of the semiconductor flow.
본 발명은 종래의 문제점을 해결하기 위하여 안출한 것으로서, 리드프레임의 타이바에 구멍과, 내부리드는형상과, 탑재판의 외주연부를 파형형상으로 하여 크기가 큰 반도체 칩 및 PCB 접착시 패키지몰드 성형을 좋게하여 제품의 품질을 높일 수 있도록 한 것을 목적으로 한다.The present invention has been made to solve the conventional problems, the hole in the tie bar of the lead frame, the inner lead The shape and the outer periphery of the mounting plate has a waveform shape to improve the quality of the product by forming a good package mold when bonding a large semiconductor chip and PCB.
이하 첨부된 도면에 의하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
반도체 칩과 인쇄회로기판을 연결시켜주기 위한 소재로 사용되는 리드프레임을 구성함에 있어서, 상기 리드프레임(1)의 타이바(2)에 구멍(3)을 여러 형태로 형성하되 본 발명 실시예의 바람직한 예로는형으로 하고, 내부리드(4)의 각각에는한 형상을 구비하며, 탑재판(5)의 외주연부에는 파형형상을 갖는형을 형성하여 된 것이다.In constructing a lead frame used as a material for connecting a semiconductor chip and a printed circuit board, holes 3 are formed in various forms in the tie bar 2 of the lead frame 1, but preferred embodiments of the present invention For example And each of the inner leads 4 It has a shape and has a wavy shape at the outer periphery of the mounting plate 5 It was made by forming a mold.
이와같이 구성된 본 발명을 상세하게 설명하면 다음과 같다.Referring to the present invention configured in this way in detail as follows.
제2도에서와 같이 리드프레임(1)의 4개소 모서리에 형성되는 각 타이바(2)에 구멍(3)을형으로 형성하여 반도체의 회로를 보호하기 위한 패키지몰드시 몰딩접착력을 좋게 하여 리드프레임(1)상에 몰드재가 견고하게 몰드되게 하고 제3도에 도시된 탑재판(5)의 외주연부에는 파형의 형상을 갖는형으로 형성하여 크기가 큰 반도체 칩 및 PCB(6)를 탑재판(5)에 접착시 이용되는 에폭시(EPOXY)재 및 테이프(TAPE)의 접착 강도를 높이는 동시에 패키지몰드후에 외부에서 침투되는 수분을 파형으로 된형에서 억제시키도록 한 것이다.As shown in FIG. 2, a hole 3 is formed in each tie bar 2 formed at four corners of the lead frame 1. It is formed into a mold to improve the molding adhesion during package molding to protect the circuit of the semiconductor so that the mold material is firmly molded on the lead frame 1, and the outer periphery of the mounting plate 5 shown in FIG. Having a shape It increases the adhesive strength of EPOXY material and tape (TAPE), which is used to bond large-sized semiconductor chip and PCB 6 to the mounting plate 5, and forms moisture to penetrate from outside after package molding. Waveform It is to be suppressed in the sentence.
또한 다수개의 내부리드(4)를형으로 하므로서 리드프레임의 각 내부리드(4)와 패키지몰드되는 컴파운드간의 접착력을 강화시킬 수 있도록 함은 물론 댐바(DAMBAR) 컷팅시 외부충격으로 인한 완충역할을형부에서 흡수하여 패키지 자체의 접착력으로 외부충격에 의한 마이크로갭(MICRO GAP)의 발생을 방지할 수 있도록 하였다.In addition, a plurality of internal leads (4) It can be used to strengthen the adhesive force between each lead (4) of the lead frame and the compound that is molded in the package, as well as cushioning due to external impact when cutting the DAMBAR. Absorbed from the mold, the adhesive force of the package itself prevents the occurrence of MICRO GAP due to external impact.
상술한 바와같이 본 발명은 리드프레임에 성형되는 패키지몰드의 접착성을 좋게 하기 위해 타이바에 구멍을 갖도록 하고 내부리드에는형의 형상을 갖도록 하며 탑재판의 외주연부를 파형 형상으로 하므로서 패키지몰드내로 투입되는 수분을 억제시키고 댐바 컷팅시 발생하는 외부충격으로부터의 완충역할을 하여 제품의 손상을 방지할 수 있는 효과가 있다.As described above, the present invention has a hole in the tie bar to improve the adhesion of the package mold to be molded to the lead frame, It has the shape of a mold, and the outer periphery of the mounting plate has a wave shape to suppress the water introduced into the package mold and to act as a buffer against the external shock generated when cutting the dam bar, thereby preventing damage to the product.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940010938A KR0123423B1 (en) | 1994-05-19 | 1994-05-19 | Lead frame of semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940010938A KR0123423B1 (en) | 1994-05-19 | 1994-05-19 | Lead frame of semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950034701A KR950034701A (en) | 1995-12-28 |
| KR0123423B1 true KR0123423B1 (en) | 1997-11-12 |
Family
ID=19383382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940010938A KR0123423B1 (en) | 1994-05-19 | 1994-05-19 | Lead frame of semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0123423B1 (en) |
-
1994
- 1994-05-19 KR KR1019940010938A patent/KR0123423B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR950034701A (en) | 1995-12-28 |
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