KR0123067B1 - Digital frequency detector - Google Patents

Abstract

a clock distributor(1) distributing self-oscillation clock from the external; a synchronization clock generator(2) generating a synchronization clock by receiving the oscillation clock from the external; a synchronization reference signal generator(3) generating a synchronization reference signal having a period corresponding to one period of the synchronization clock inputted from the synchronization clock generator(2); an ascending counter(4) counting by ascending the number of the self oscillation clock of the clock distributor(1); a latch clock generator(5) generating a latch clock by receiving the synchronization reference signal from the synchronization reference signal generator(3); a latch means(6) latching the number of the self oscillation clock continuously; a frequency comparator(7) comparing the number of the self oscillation clock counted for one period of the synchronization reference signal inputted from the latch means(6) with the theoretical number of the self oscillation clock; a frequency adjusting signal generator(8); and an ascending and descending counter(9) outputting the frequency adjusted value.

Description

Digital frequency detector adjusts sync time and amount of sync

1 is a block diagram of a digital frequency detector according to the present invention.

2 is a detailed block diagram of a rise counter, a latch and a frequency comparator according to the present invention.

* Explanation of symbols for main parts of the drawings

1: Oscillator Clock Splitter 2: Synchronous Clock Generator

3: synchronization reference signal generator 4: rising counter

5: Latch Clock Generator 6: Latch

7: frequency comparator 8: frequency adjustment signal generator

9: rising and falling counter

411, 412,... , 41 (n-2), 41 (n-1), 41n: m-bit rise counter

421, 422,... , 42 (n-2), 42 (n-1): Ripple carry output controller

61, 62,... , 6 (n-2), 6 (n-1), 6n: m-bit latch

71, 72,... , 7 (n-2), 7 (n-1), 7n: m-bit comparator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital frequency detector having a function of self-adjusting the synchronization time required and the degree of synchronization (hereinafter referred to as resolution) among the frequency detectors constituting the digital synchronization device.

The present invention operates to reduce the time required for initial synchronization even if the resolution decreases slightly in the initial synchronization process, so that the digital synchronization device can have sufficient resolution after a predetermined time has elapsed in synchronization with the minimum time. After synchronization is achieved, the purpose is to provide a digital frequency detector configured to sequentially increase the resolution to ensure sufficient resolution after a certain time passes.

The present invention devised to achieve the above object, the clock distribution means for receiving and distributing its own oscillation clock from the outside; Synchronization clock generation means for receiving an oscillation clock from the outside to generate a synchronization clock; Synchronizing reference signal generating means for generating a synchronizing reference signal having one period width of the self-oscillating clock input from the clock distribution means and a period corresponding to one period of the synchronization clock input from the synchronization clock generating means; Rising coefficient means for continuously increasing the number of self-oscillating clocks of the clock distribution means at intervals of one period of the synchronization reference signal received from the synchronization reference signal generating means; Latch clock generation means for receiving a synchronization reference signal from the synchronization reference signal generation means and generating a latch clock; Latch means for continuously latching the number of self-oscillating clocks counted by the rising coefficient means for one period of the synchronization reference signal to the latch clock inputted from the latch clock generating means; The rising coefficient means and the latch means by comparing the number of the self-oscillating clocks included in one period of the synchronization reference signal input from the latch means with the number of theoretical self-oscillating clocks to be included in one preset synchronization reference signal period. Frequency comparing means for outputting a synchronization confirmation signal and outputting a comparison result to respective signal lines indicating 'large' and 'small'; Frequency adjustment which converts the output of the frequency comparison means into a frequency adjustment signal that increases or decreases the frequency, outputs each signal line indicating 'increase' or 'decrease' of the frequency, and clears it before the next signal indicating the number of clocks is input. Signal generating means; And a frequency adjustment value such that the number of self-oscillating clocks included in one period of the synchronization reference signal after receiving the output of the frequency adjustment signal generating means is ultimately equal to the number of theoretical self-oscillation clocks to be included in one period of the synchronization reference signal. And the initial value is provided with the rising and falling coefficient means set to the number of theoretical self-oscillating clocks to be included in one period of the synchronization reference signal.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention;

1 is a configuration diagram of a digital frequency detector according to the present invention, as shown in the drawings, 1 is an oscillator clock divider, 2 is a synchronous clock generator, 3 is a synchronization reference signal generator, 4 is a rising counter, 5 is a latch clock generator, 6 denotes a latch, 7 denotes a frequency comparator, 8 denotes a frequency adjustment signal generator, and 9 denotes a rising and falling coefficient.

2 is a detailed block diagram for explaining the operation principle of the rise counter, the latch and the frequency comparison period according to the present invention. , 41 (n-2), 41 (n-1), 41n are m-bit ascending counters, 421, 422,... , 42 (n-2), 42 (n-1) are ripple carry output controllers, 61, 62,... , 6 (n-2), 6 (n-1), 6n are m bit latches, 71, 72,... , 7 (n-2), 7 (n-1), 7n represent m-bit comparators, respectively, and E1, E2,... , E (n-2), E (n-1) are ripple carry output enable signals, OE1, OE2,... , OE (n-2), OE (n-1), OEn are latch enable signals, TC1, TC2,... , TC (n-2), TC (n-1), and TCn represent the ripple carry output, respectively.

The operation of the present invention will be described with reference to FIGS. 1 and 2.

The oscillator clock divider 1 receives and distributes an oscillation clock from an oscillator constituting a digital synchronizer.

The synchronous clock generator 2 receives an oscillation clock from an external source providing a synchronization source to the digital synchronization device, generates and outputs a synchronization clock used for the digital synchronization device.

The synchronization reference signal generator 3 receives its own oscillation clock from the oscillator clock divider 1 and receives the synchronization clock from the synchronization clock generator 2 and has a period width of its own oscillation clock and corresponds to one period of the synchronization clock. A synchronization reference signal having a period of time is generated and output.

The rising counter 4 has n number of m bits (m is any natural number) unit counters {411, 412,... , 41 (n-2), 41 (n-1), 41n: n is an arbitrary natural number} and (n-1) ripple carry output controllers {421, 422,... , 42 (n-2), 42 (n-1)}, and the final resolution becomes the frequency change degree of oscillator / 2 ^mn , and receives its oscillation clock from the oscillator clock divider 1 and receives the synchronization reference. Receives the synchronization reference signal output from the signal generator 3 and increments the number of self-oscillating clocks in the interval of one period of the synchronization reference signal by m incremental unit by the gradual and sequential method from the upper bit to the lower bit in the unit of m bit unit That is, the n-th unit counter 41n continuously counts the number of self-oscillating clocks at one cycle interval of the synchronization reference signal, so that the number of two clocks that the n-th unit comparator 7n compares in the frequency comparator 7 to be described later is compared. When the signal {E (n-1)} of the same degree of synchronization is sent, the (n-1) th ripple carry output controller {42 (n-1)} is driven to {n, (n-1)} th. Connect unit counters {41n, 41 (n-1)} serially and synchronize the reference signal for one period The number of self-oscillating clocks is continuously increased and the number of two clocks compared by the {n, (n-1)} th unit comparator {7n, 7 (n-1)} in the frequency comparator 7 to be described later is the same. When the signal {E (n-2)} indicating the degree of synchronization is transmitted, the (n-2) th ripple carry output controller {42 (n-2)} is driven again, and {n, (n-1), ( n-2)} th unit counters {41n, 41 (n-1), 41 (n-2)} by serially connecting n unit counters {411, 412,... , 41 (n-2), 41 (n-1), and 41n} are all driven, and the number of self-oscillating clocks is continuously raised at the interval of one period of the synchronization reference signal and outputted.

The latch clock generator 5 receives the synchronization reference signal output from the synchronization reference signal generator 3 and the number of self-oscillating clocks which the rising counter 4 raises and counts for one period of the synchronization reference signal, that is, the rising counter. (4) starts the rising coefficient by the synchronization reference signal and generates and outputs a clock which correctly latches the value to be finally output immediately before being reset by the next synchronization reference signal.

The latch 6 has n number of m-bit latches {61, 62,... , 6 (n-2), 6 (n-1), and 6n}, and the number of self-oscillating clocks counted by the rising counter 4 during one period of the synchronization reference signal from the latch clock generator 5 Using the latch clock input, the latch is latched by a progressive and sequential method from the upper bit to the lower bit in m bit unit latch units, that is, the nth unit counter of the rising counter 4 with the nth unit latch 6n. The number of self-oscillating clocks (41n) counted for one period of the synchronization reference signal was continuously latched, and then the number of two clocks compared by the n-th unit comparator 7n in the frequency comparator 7 described later achieved the same degree of synchronization. When the signal {OE (n-1)} is sent, the (n-1) th unit latch {6 (n-1)} is driven to drive the {n, (n-1)} th unit latch {6n, 6 (n -1)} continuously latches the number of self-oscillating clocks counted by the {n, (n-1)} th counter {4n, 4 (n-1)} of the rising counter 4 during one period of the synchronization reference signal. One In the frequency comparator 7, which will be described later, a signal {OE () indicating that the number of two clocks compared by the {n, (n-1)} th unit comparators {7n, 7 (n-1)} is equal to each other. n-2)}, the (n-2) th unit latch {6 (n-2)} is driven again. Finally, n unit latches {61,62,... , 6 (n-2), 6 (n-1), and 6n} are all driven and continuously latched and output by their latch clocks counted for one period of the synchronization reference signal.

The frequency comparator 7 is composed of n m-bit unit comparators {71, 72,... , 7 (n-2), 7 (n-1), and 7n}, and the synchronization in which the number of self-oscillating clocks included in one cycle of the synchronization reference signal latched and output by the latch 6 is preset. The number of theoretical self-oscillating clocks to be included in one reference signal period is compared with a gradual and sequential method from the upper bit to the lower bit in mbit unit comparator units, that is, two clocks in the nth unit comparator 7n. If the number of clocks is the same, the control signals {E (n-1), OE (n-1)} are outputted by comparing the magnitudes of the two and the number of clocks, and the (n-1) th ripple carry output controller of the rising counter 4 { 42 (n-1)} to connect the {n, (n-1)} th unit counters {41n, 41 (n-1)} in series and {n, (n-1) of the latch 6 )} Th unit latch {6n, 6 (n-1)} is driven together to output the {n, (n-1)} th unit counter {41n, 41 (n-1)} of the rising counter 4; To the {n, (n-1)} th unit latch {6n, 6 (n-1)} of the latch 6 Compare the number of the two clocks with the {n, (n-1)} th unit comparator {7n, 7 (n-1)} connected to the output by inputting the control signal {E (n -2), OE (n-2)} is output and the (n-2) th ripple carry output controller {42 (n-2)} of the rising counter 4 is driven to {n, (n-1) , (n-2)} th unit counters {41n, 41 (n-1), 41 (n-2)} in series and {n, (n-1), (n−) of the latch 6 2)} th unit latch {6n, 6 (n-1), 6 (n-2)} together to drive {n, (n-1), (n-2)} th of the rising counter 4 {N, (n-1), (n-2)} th unit latch {6n, 6 of the output of the unit counter {41n, 41 (n-1), 41 (n-2)} of the latch 6 (n-1), 6 (n-2)} inputs the latched outputs and compares them again. Finally, all n unit comparators are driven to theoretically oscillate to be included in one period of the sync reference signal. For one period of the synchronization reference signal latched and output by the latch 6 for the number of clocks. The number of self-oscillating clocks included in the unit is compared in units of mn bits, and the result is output to each signal line indicating 'large' and 'small' so that the corresponding signal line becomes the logic level 'High'.

The frequency adjustment signal generator 8 is a 'large' number of the number of self-oscillating clocks included in one period of the synchronization reference signal from the frequency comparator 7 for the number of theoretical self-oscillation clocks to be included in one period of the synchronization reference signal. And two signal lines indicating 'small' are input, and the signal line indicating 'large' is selected among the signal lines input by receiving the oscillation clock from the oscillator clock divider 1 and the synchronization clock from the sync clock generator 3 respectively. In the case of the level 'High', a signal for increasing the frequency is generated, and in the case where the signal line indicating 'small' is a logic level 'High', a signal for reducing the frequency is generated and output as a signal line for each signal line. The signal line is cleared before the next signal indicating the magnitude is input.

The rising and falling counter (9) consists of n counters (mn-bit counters) whose m-bit counters are set to the number of theoretical self-oscillating clocks whose initial values are to be included in one period of the synchronization reference signal. In theory, the frequency adjustment signal generator 8 inputs two signal lines indicating the frequency 'increase' and 'decrease' so that the number of self-oscillating clocks included in one period of the synchronization reference signal should be included in one period of the synchronization reference signal. Adjust and output the oscillator control value in the following way so that the number of oscillation clocks is equal to the number of self-oscillating clocks.

If the oscillator in the digital synchronizer has a positive propagation characteristic, connect the signal line which transmits the signal of increasing frequency to the lower part of the counter, and the signal line which transmit the signal of decreasing frequency to the rising part of the counter. do.

If the oscillator in the digital synchronizer has 'negative' propagation characteristics, connect the signal line which transmits the signal of increasing frequency to the rising part of the counter, and the signal line which transmit the signal of decreasing frequency to the falling part of the counter. do.

The present invention as described above allows the frequency detector constituting the digital synchronization device to adjust the synchronization time and resolution itself, and has the following effects.

First, the digital synchronizer can be synchronized in a minimum amount of time, thereby minimizing the time required to stabilize the synchronizer.

Secondly, once the digital synchronizer is synchronized, the resolution is increased in order to maintain a high resolution after a certain period of time.

Third, by using mbit unit devices, semiconductor integration is possible, and the size of the frequency detector can be arbitrarily reduced and expanded according to the resolution of the synchronization device required by the user.

Claims (5)

Clock distribution means (1) for receiving and distributing the oscillation clock from the outside; Synchronization clock generation means (2) for receiving an oscillation clock from outside to generate a synchronization clock; Generation of a synchronization reference signal having a period width of one oscillation clock input from the clock distribution means 1 and generating a synchronization reference signal having a period corresponding to one period of the synchronization clock input from the synchronization clock generation means 2. Means (3); Rising coefficient means (4) for continuously increasing the number of self-oscillating clocks of the clock distribution means (1) at intervals of one period of the synchronization reference signal received from the synchronization reference signal generating means (3); Latch clock generation means (5) for receiving a synchronization reference signal from said synchronization reference signal generation means (3) and generating a latch clock; Latch means (6) for continuously latching the number of self-oscillating clocks counted by the rising coefficient means (4) for one period of the synchronization reference signal by the latch clock inputted from the latch clock generating means (5); The rising coefficient means by comparing the number of self-oscillating clocks included in one period of the synchronization reference signal input from the latch means 6 with the number of theoretical self-oscillating clocks to be included in one preset synchronization reference signal period. Frequency comparison means (7) for outputting a synchronization confirmation signal to (4) and the latch means (6) and for outputting the comparison result to respective signal lines indicating 'large' and 'small'; The output of the frequency comparison means 7 is converted into a frequency adjustment signal that increases or decreases the frequency, and is output to each signal line indicating 'increase' and 'decrease' of the frequency, and cleared before the next signal indicating the magnitude of the clock number is input. Frequency adjusting signal generating means (8); And receiving the output of the frequency adjustment signal generating means 8 so that the number of self-oscillating clocks included in one period of the synchronization reference signal is ultimately equal to the number of theoretical self-oscillating clocks to be included in one period of the synchronization reference signal. Outputs a frequency adjustment value and the initial value includes a rising and falling count means (9) set to the number of theoretical self-oscillating clocks to be included in one period of the synchronization reference signal. Digital frequency detector to adjust. 2. The clock distribution means (1) according to claim 1, wherein the clock distribution means (1) receives and distributes its own oscillation clock from an oscillator in an external digital synchronization device, and the synchronization clock generation means (2) provides a synchronization source to the digital synchronization device. Receiving an oscillation clock from an external synchronization source to generate a synchronization clock, and the synchronization reference signal generating means 3 receives its own oscillation clock from the clock distribution means 1 and receives the synchronization clock from the synchronization clock generation means 2. Receives a signal and generates a synchronization reference signal having a period of one oscillation clock and a period corresponding to one period of the synchronization clock, and the rising coefficient means 4 inputs its oscillation clock from the clock distribution means 1. Receiving the synchronization reference signal output from the synchronization reference signal generating means 2, and counting the number of self-oscillating clocks at one cycle interval of the synchronization reference signal. As a result of the incremental coefficient from the upper bit to the lower bit, the rising coefficient is gradually driven. Finally, all the unit counters are driven to continuously increase the number of self-oscillating clocks at intervals of one period of the synchronization reference signal. (5) receives a synchronization reference signal output from the synchronization reference signal generating means 3 and generates a clock for latching the number of self-oscillating clocks counted by the rising coefficient means 4 for one period of the synchronization reference signal; The latch means (6) uses the latch clock inputted from the latch clock generating means (5) in units of unit latches to determine the number of self-oscillating clocks counted by the rising coefficient means 4 during one period of the synchronization reference signal. The latch clock is generated by latching in a progressive and sequential manner from the upper bit to the lower bit to drive all of the unit latches. A latch clock outputted from stage 5 continuously latches the number of self-oscillating clocks counted by the rising coefficient means 4 for one period of the synchronization reference signal, and the frequency comparing means 7 performs the latch means 6 The number of self-oscillating clocks included in one latch reference period and the number of theoretical self-oscillating clocks to be included in one preset synchronization reference signal period is the unit bit comparison unit. The synchronous reference latched by the latch means 6 outputs the number of theoretical self-oscillating clocks to be included in one period of the synchronous reference signal by driving all of the unit comparators in a gradual and sequential manner. Compare the number of self-oscillating clocks included in one period of the signal and output the result to each signal line indicating 'large' and 'small' A confirmation signal is output to the rising coefficient means 4 and the latch means 6, and the frequency adjustment signal generating means 8 is theoretically to be included in one period of the synchronization reference signal from the frequency comparing means 7. Synchronous reference signal for the number of self-oscillating clocks A signal indicating 'large' and 'small' of the number of self-oscillating clocks included in one period is input, and the self-oscillating clock and the synchronous clock are generated from the clock distribution means 1. The signal of each of the 'clock' and 'small' of the number of clocks outputted from the frequency comparison means 7 is converted into a frequency adjustment signal that increases or decreases the frequency by receiving the sync clocks from the means 2 respectively. Outputs to respective signal lines indicating 'increase' and 'decrease', and clears before the next signal indicating the magnitude of the clock number from the frequency comparing means 7 is input, The falling coefficient means 9 receives a signal indicating 'increase' or 'decrease' of the frequency output from the frequency adjustment signal generating means 8, and the number of self-oscillating clocks included in one period of the synchronization reference signal is the synchronization reference. The frequency adjustment value is output so that it is ultimately equal to the number of theoretical self-oscillating clocks to be included in one cycle of the signal, and the initial value is set to the number of theoretical self-oscillating clocks to be included in one synchronization reference signal. Digital frequency detector that adjusts the synchronization time required and the degree of synchronization. The counter of claim 1 or 2, wherein the rising coefficient means (4) comprises: n m-bits (m is any natural number) unit counters {411, 412,... , 41 (n-2), 41 (n-1), 41n: n is an arbitrary natural number} and (n-1) ripple carry output controllers 421,422,... 42 (n-2), 42 (n-1)} to receive its own oscillation clock from the clock distribution means 1 and to receive the synchronization reference signal outputted from the synchronization reference signal generation means 3; The number of self-oscillating clocks is incremented by the gradual and sequential method from the upper bit to the lower bit in units of m-bit counters at intervals of one period of the synchronization reference signal, that is, the n-th unit counter 41n performs one cycle of synchronization reference signal. The number of self-oscillating clocks is continuously increased at regular intervals so that the frequency comparison means 7 signals that the number of two clocks compared by the n-th unit comparator 7n is equally synchronized {E (n-1). )} To send the (n-1) th ripple carry output controller {42 (n-1)} to serialize the {n, (n-1)} th unit counters {41n, 41 (n-1)}. And the number of self-oscillating clocks continues to increase in the interval of one period of the synchronization reference signal. The signal {E (n-2) indicating that the number of two clocks compared by the {n (n-1)} th unit comparator {7n, 7 (n-1)} in the frequency comparison means 7 is equally synchronized. )} Again, it drives the (n-2) th ripple carry output controller {42 (n-2)} and the {n, (n-1), (n-2)} th unit counter {41n, 41 ( n-1), 41 (n-2)} by serial connection. Finally, n unit counters {411,412,... , 41 (n-2), 41 (n-1), and 41n} to drive all of the oscillation clocks at the interval of one period of the synchronization reference signal, and output the result by increasing the coefficient of synchronization. Digital frequency detector to adjust the degree of 3. The latch means (6) according to claim 1 or 2, wherein the latch means (6) comprises n number of m-bit latches (61, 62,... The number of self-oscillating clocks provided by the ascending coefficient means 4 during one period of the synchronization reference signal, comprising 6 (n-2), 6 (n-1), 6n} (n, m is an arbitrary natural number). Using the latch clock inputted from the latch clock generating means 5, latching by a sequential method in the direction of the upper bit to the lower bit in m bit unit latch units, that is, the n th unit latch 6n. The n-th unit counter 41n of the rising coefficient means 4 continuously latches the number of self-oscillating clocks counted for one period of the synchronization reference signal, and the n-th unit comparator 7n compares the frequency comparison means 7. When the signal {OE (n-1)} that the number of two clocks is equally synchronized is sent, the (n-1) th unit latch {6 (n-1)} is driven to {n, (n-1). The {n, (n-1)} th counter {4n, 4 (n-1)} of the ascending coefficient means 4 with the {} nth unit latch {6n, 6 (n-1)} Counting during the period After continuously latching the number of sieve oscillation clocks, the frequency comparison means 7 performs the same number of two clocks compared by the {n, (n-1)} th unit comparators {7n, 7 (n-1)}. When the signal {OE (n-2)} is transmitted, the (n-2) th unit latch {6 (n-2)} is driven again. Finally, n unit latches {61,62 ,… , 6 (n-2), 6 (n-1), and 6n}, so that the number of self-oscillating clocks counted by the rising-counter means 4 for one period of the synchronization reference signal is used as the latch clock generating means ( A digital frequency detector for adjusting the synchronization time required and the degree of synchronization, characterized in that the latch is continuously latched and output by the latch clock output in step 5). 3. A frequency comparison means (7) according to claim 1 or 2, characterized in that the frequency comparison means (7) comprises n m-bit unit comparators (71, 72,... , 7 (n-2), 7 (n-1), 7n} (n, m are arbitrary natural numbers), and are included in one period of the synchronization reference signal latched and output by the latch means 6 The number of theoretical self-oscillating clocks to be included in one period of the synchronization reference signal with preset number of oscillation clocks is compared with a gradual and sequential method from the upper bit to the lower bit in the unit of m-bit comparator. In the n-th unit comparator 7n, the magnitudes of the two clocks are compared, and if the number of the two clocks is the same, the control signal {E (n-1), OE (n-1)} is output and the rising coefficient means 4 The (n-1) th ripple carry output controller {42 (n-1)} is driven to connect the {n, (n-1)} th unit counters {41n, 41 (n-1)} in series and the latch The {n, (n-1)} th unit counter of the rising counter 4 is driven by driving the {n, (n-1)} th unit latch {6n, 6 (n-1)} together of the means 6; Output of {41n, 41 (n-1)} of the latch means 6 {n, (n-1)} th unit comparator connected in series by inputting output latched with {n, (n-1)} th unit latch {6n, 6 (n-1)} {7n, 7 (n -1)} by comparing the number of two clocks and outputting the control signals {E (n-2), OE (n-2)} when the number of two clocks is the same. 2) the ripple carry output controller {42 (n-2)} to drive {n, (n-1), (n-2)} th unit counters {41n, 41 (n-1), 41 (n- 2)} in series and the {n, (n-1), (n-2)} th unit latch {6n, 6 (n-1), 6 (n-2)} of the latch means 6; Are driven together to output the {n, (n-1), (n-2)} th unit counters {41n, 41, (n-1), 41 (n-2)} of the rising coefficient means 4; To the {n, (n-1), (n-2)} th unit latch {6n, 6 (n-1), 6 (n-2)} of the latch means 6, Finally, all of the n unit comparators are driven again to compare the number of theoretical self-oscillating clocks to be included in one period of the synchronization reference signal. The number of self-oscillating clocks included in one period of the synchronization reference signal latched and output by the value means 6 is compared in units of mn bits, and the result is a signal line representing 'large' and 'small'. A digital frequency detector for controlling the synchronization time required and the degree of synchronization, characterized by outputting the logic level 'High'.