JPWO2023037595A1 - - Google Patents

Info

Publication number
JPWO2023037595A1
JPWO2023037595A1 JP2023546747A JP2023546747A JPWO2023037595A1 JP WO2023037595 A1 JPWO2023037595 A1 JP WO2023037595A1 JP 2023546747 A JP2023546747 A JP 2023546747A JP 2023546747 A JP2023546747 A JP 2023546747A JP WO2023037595 A1 JPWO2023037595 A1 JP WO2023037595A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2023546747A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2023037595A1 publication Critical patent/JPWO2023037595A1/ja
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815Cache consistency protocols
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2023546747A 2021-09-07 2022-03-04 Pending JPWO2023037595A1 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021145665 2021-09-07
PCT/JP2022/009370 WO2023037595A1 (ja) 2021-09-07 2022-03-04 情報処理装置及び情報処理方法

Publications (1)

Publication Number Publication Date
JPWO2023037595A1 true JPWO2023037595A1 (ja) 2023-03-16

Family

ID=85507329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023546747A Pending JPWO2023037595A1 (ja) 2021-09-07 2022-03-04

Country Status (4)

Country Link
JP (1) JPWO2023037595A1 (ja)
CN (1) CN117882056A (ja)
DE (1) DE112022004300T5 (ja)
WO (1) WO2023037595A1 (ja)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07262089A (ja) * 1994-03-17 1995-10-13 Fujitsu Ltd ロックアクセス制御方法および情報処理装置
JP2006276901A (ja) * 2005-03-25 2006-10-12 Nec Corp マルチプロセッサ計算機、そのキャッシュコヒーレンシ保証方法及びキャッシュコヒーレンシ保証プログラム

Also Published As

Publication number Publication date
CN117882056A (zh) 2024-04-12
DE112022004300T5 (de) 2024-07-18
WO2023037595A1 (ja) 2023-03-16

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