JPWO2023032764A1 - - Google Patents
Info
- Publication number
- JPWO2023032764A1 JPWO2023032764A1 JP2023545481A JP2023545481A JPWO2023032764A1 JP WO2023032764 A1 JPWO2023032764 A1 JP WO2023032764A1 JP 2023545481 A JP2023545481 A JP 2023545481A JP 2023545481 A JP2023545481 A JP 2023545481A JP WO2023032764 A1 JPWO2023032764 A1 JP WO2023032764A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Architecture (AREA)
- Computer Networks & Wireless Communication (AREA)
- Measurement Of Resistance Or Impedance (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2021145013 | 2021-09-06 | ||
| PCT/JP2022/031766 WO2023032764A1 (ja) | 2021-09-06 | 2022-08-23 | 多端子キャパシタの等価回路モデル作成方法、等価回路モデル作成プログラム、等価回路モデル作成プログラムを記憶した記憶媒体、シミュレーション方法およびシミュレーション装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPWO2023032764A1 true JPWO2023032764A1 (ja) | 2023-03-09 |
| JPWO2023032764A5 JPWO2023032764A5 (ja) | 2024-04-17 |
Family
ID=85412508
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023545481A Pending JPWO2023032764A1 (ja) | 2021-09-06 | 2022-08-23 |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPWO2023032764A1 (ja) |
| KR (1) | KR20240034846A (ja) |
| CN (1) | CN117882079A (ja) |
| WO (1) | WO2023032764A1 (ja) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4507421B2 (ja) * | 2001-02-27 | 2010-07-21 | パナソニック株式会社 | 受動素子の等価回路モデル導出方法、シミュレータ、及び記憶媒体 |
| JP5246785B2 (ja) * | 2009-03-04 | 2013-07-24 | 国立大学法人東京工業大学 | 回路モデル作成装置、回路モデル作成方法、シミュレーション装置、及び、シミュレーション方法 |
| JP5573868B2 (ja) * | 2012-03-07 | 2014-08-20 | 株式会社村田製作所 | 等価回路作成方法、等価回路作成プログラム及び等価回路作成装置 |
-
2022
- 2022-08-23 CN CN202280058904.2A patent/CN117882079A/zh active Pending
- 2022-08-23 JP JP2023545481A patent/JPWO2023032764A1/ja active Pending
- 2022-08-23 WO PCT/JP2022/031766 patent/WO2023032764A1/ja active Application Filing
- 2022-08-23 KR KR1020247006020A patent/KR20240034846A/ko unknown
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023032764A1 (ja) | 2023-03-09 |
| KR20240034846A (ko) | 2024-03-14 |
| CN117882079A (zh) | 2024-04-12 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20240122 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20240122 |