JPWO2022091957A1 - - Google Patents
Info
- Publication number
- JPWO2022091957A1 JPWO2022091957A1 JP2022559082A JP2022559082A JPWO2022091957A1 JP WO2022091957 A1 JPWO2022091957 A1 JP WO2022091957A1 JP 2022559082 A JP2022559082 A JP 2022559082A JP 2022559082 A JP2022559082 A JP 2022559082A JP WO2022091957 A1 JPWO2022091957 A1 JP WO2022091957A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2020183053 | 2020-10-30 | ||
JP2020183054 | 2020-10-30 | ||
PCT/JP2021/039046 WO2022091957A1 (ja) | 2020-10-30 | 2021-10-22 | 電子部品内蔵基板 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPWO2022091957A1 true JPWO2022091957A1 (ja) | 2022-05-05 |
Family
ID=81383853
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2022559082A Pending JPWO2022091957A1 (ja) | 2020-10-30 | 2021-10-22 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20240014112A1 (ja) |
JP (1) | JPWO2022091957A1 (ja) |
WO (1) | WO2022091957A1 (ja) |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002198629A (ja) * | 2000-12-26 | 2002-07-12 | Kyocera Corp | 配線基板およびその製法 |
JP2003332716A (ja) * | 2002-03-04 | 2003-11-21 | Ngk Spark Plug Co Ltd | 配線基板及び配線基板の製造方法 |
JP2005050999A (ja) * | 2003-07-28 | 2005-02-24 | Toyota Motor Corp | 配線基板および配線の形成方法 |
JP2012212867A (ja) * | 2011-03-30 | 2012-11-01 | Ibiden Co Ltd | プリント配線板及びその製造方法 |
JP7486934B2 (ja) * | 2018-12-25 | 2024-05-20 | Tdk株式会社 | 回路基板 |
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2021
- 2021-10-22 WO PCT/JP2021/039046 patent/WO2022091957A1/ja active Application Filing
- 2021-10-22 JP JP2022559082A patent/JPWO2022091957A1/ja active Pending
- 2021-10-22 US US18/249,862 patent/US20240014112A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
WO2022091957A1 (ja) | 2022-05-05 |
US20240014112A1 (en) | 2024-01-11 |