JPWO2021255926A5 - - Google Patents

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Publication number
JPWO2021255926A5
JPWO2021255926A5 JP2022531226A JP2022531226A JPWO2021255926A5 JP WO2021255926 A5 JPWO2021255926 A5 JP WO2021255926A5 JP 2022531226 A JP2022531226 A JP 2022531226A JP 2022531226 A JP2022531226 A JP 2022531226A JP WO2021255926 A5 JPWO2021255926 A5 JP WO2021255926A5
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JP
Japan
Prior art keywords
processes
execution unit
instruction
specifying
control method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP2022531226A
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English (en)
Japanese (ja)
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JPWO2021255926A1 (https=
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Publication date
Application filed filed Critical
Priority claimed from PCT/JP2020/024186 external-priority patent/WO2021255926A1/ja
Publication of JPWO2021255926A1 publication Critical patent/JPWO2021255926A1/ja
Publication of JPWO2021255926A5 publication Critical patent/JPWO2021255926A5/ja
Ceased legal-status Critical Current

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JP2022531226A 2020-06-19 2020-06-19 Ceased JPWO2021255926A1 (https=)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/024186 WO2021255926A1 (ja) 2020-06-19 2020-06-19 制御方法、情報処理装置、及び制御プログラム

Publications (2)

Publication Number Publication Date
JPWO2021255926A1 JPWO2021255926A1 (https=) 2021-12-23
JPWO2021255926A5 true JPWO2021255926A5 (https=) 2022-11-25

Family

ID=79267735

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022531226A Ceased JPWO2021255926A1 (https=) 2020-06-19 2020-06-19

Country Status (5)

Country Link
US (1) US20230063497A1 (https=)
EP (1) EP4170487A4 (https=)
JP (1) JPWO2021255926A1 (https=)
CN (1) CN115698943A (https=)
WO (1) WO2021255926A1 (https=)

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62233874A (ja) * 1986-04-03 1987-10-14 Nec Corp 情報処理方式
JP3392545B2 (ja) * 1994-09-30 2003-03-31 株式会社東芝 命令列最適化装置
US7401208B2 (en) * 2003-04-25 2008-07-15 International Business Machines Corporation Method and apparatus for randomizing instruction thread interleaving in a multi-thread processor
US7941643B2 (en) * 2006-08-14 2011-05-10 Marvell World Trade Ltd. Multi-thread processor with multiple program counters
US20100281234A1 (en) * 2009-04-30 2010-11-04 Novafora, Inc. Interleaved multi-threaded vector processor
JP2011141756A (ja) * 2010-01-07 2011-07-21 Yokogawa Electric Corp Ｃｐｕ故障検出方法およびｃｐｕ故障検出装置
GB2489708B (en) * 2011-04-05 2020-04-15 Advanced Risc Mach Ltd Thread selection for multithreaded processing
JP2013054625A (ja) * 2011-09-06 2013-03-21 Toyota Motor Corp 情報処理装置、情報処理方法
US9395992B2 (en) * 2012-11-19 2016-07-19 International Business Machines Corporation Instruction swap for patching problematic instructions in a microprocessor
KR20150019349A (ko) 2013-08-13 2015-02-25 삼성전자주식회사 다중 쓰레드 실행 프로세서 및 이의 동작 방법

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