JPWO2021171506A1 - - Google Patents

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Publication number
JPWO2021171506A1
JPWO2021171506A1 JP2021572484A JP2021572484A JPWO2021171506A1 JP WO2021171506 A1 JPWO2021171506 A1 JP WO2021171506A1 JP 2021572484 A JP2021572484 A JP 2021572484A JP 2021572484 A JP2021572484 A JP 2021572484A JP WO2021171506 A1 JPWO2021171506 A1 JP WO2021171506A1
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JP
Japan
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JP2021572484A
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JP7051024B2 (ja
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Publication of JPWO2021171506A1 publication Critical patent/JPWO2021171506A1/ja
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Publication of JP7051024B2 publication Critical patent/JP7051024B2/ja
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/1134—Full parallel processing, i.e. all bit nodes or check nodes are processed in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/114—Shuffled, staggered, layered or turbo decoding schedules
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1145—Pipelined decoding at code word level, e.g. multiple code words being decoded simultaneously
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1168—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices wherein the sub-matrices have column and row weights greater than one, e.g. multi-diagonal sub-matrices

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Error Detection And Correction (AREA)
JP2021572484A 2020-02-27 2020-02-27 復号方法、復号装置、制御回路およびプログラム記憶媒体 Active JP7051024B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/008111 WO2021171506A1 (ja) 2020-02-27 2020-02-27 復号方法、復号装置、制御回路およびプログラム記憶媒体

Publications (2)

Publication Number Publication Date
JPWO2021171506A1 true JPWO2021171506A1 (ja) 2021-09-02
JP7051024B2 JP7051024B2 (ja) 2022-04-08

Family

ID=77492079

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021572484A Active JP7051024B2 (ja) 2020-02-27 2020-02-27 復号方法、復号装置、制御回路およびプログラム記憶媒体

Country Status (3)

Country Link
US (1) US20220329261A1 (ja)
JP (1) JP7051024B2 (ja)
WO (1) WO2021171506A1 (ja)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009100422A (ja) * 2007-10-19 2009-05-07 Sony Corp 受信装置および方法、並びにプログラム
US20100275088A1 (en) * 2009-04-22 2010-10-28 Agere Systems Inc. Low-latency decoder
US20180157551A1 (en) * 2016-12-01 2018-06-07 Western Digital Technologies, Inc. Ecc decoder with selective component disabling based on decoding message resolution

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4225163B2 (ja) * 2003-05-13 2009-02-18 ソニー株式会社 復号装置および復号方法、並びにプログラム
JP4672015B2 (ja) * 2004-07-27 2011-04-20 エルジー エレクトロニクス インコーポレイティド 低密度パリティ検査コードを用いた符号化及び復号化方法
US8418023B2 (en) * 2007-05-01 2013-04-09 The Texas A&M University System Low density parity check decoder for irregular LDPC codes
JP2009100222A (ja) * 2007-10-16 2009-05-07 Toshiba Corp 低密度パリティ検査符号の復号装置およびその方法
JP5320964B2 (ja) * 2008-10-08 2013-10-23 ソニー株式会社 サイクリックシフト装置、サイクリックシフト方法、ｌｄｐｃ復号装置、テレビジョン受像機、及び、受信システム
US9459956B2 (en) * 2013-07-19 2016-10-04 Seagate Technology Llc Data decoder with trapping set flip bit mapper
US10530392B2 (en) * 2017-07-31 2020-01-07 Codelucida, Inc. Vertical layered finite alphabet iterative decoding

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009100422A (ja) * 2007-10-19 2009-05-07 Sony Corp 受信装置および方法、並びにプログラム
US20100275088A1 (en) * 2009-04-22 2010-10-28 Agere Systems Inc. Low-latency decoder
US20180157551A1 (en) * 2016-12-01 2018-06-07 Western Digital Technologies, Inc. Ecc decoder with selective component disabling based on decoding message resolution

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ZTE, ZTE MICROELECTRONICS: "Complexity, throughput and latency considerations on LDPC codes for eMBB", 3GPP TSG RAN WG1 #88 R1-1701599, JPN6020017120, 7 February 2017 (2017-02-07), pages 1 - 12, ISSN: 0004717135 *

Also Published As

Publication number Publication date
US20220329261A1 (en) 2022-10-13
WO2021171506A1 (ja) 2021-09-02
JP7051024B2 (ja) 2022-04-08

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