JPWO2021149770A5 - - Google Patents

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JPWO2021149770A5
JPWO2021149770A5 JP2021572793A JP2021572793A JPWO2021149770A5 JP WO2021149770 A5 JPWO2021149770 A5 JP WO2021149770A5 JP 2021572793 A JP2021572793 A JP 2021572793A JP 2021572793 A JP2021572793 A JP 2021572793A JP WO2021149770 A5 JPWO2021149770 A5 JP WO2021149770A5
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semiconductor layer
layer
type semiconductor
metal
type
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Priority claimed from PCT/JP2021/002060 external-priority patent/WO2021149770A1/en
Publication of JPWO2021149770A1 publication Critical patent/JPWO2021149770A1/ja
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Claims (13)

ガラス転移点が600℃以下の基材と、
前記基材の一面に形成され、第14族元素の単体または化合物、およびn型不純物元素を固溶限相当の濃度で含むn型半導体層と、を備え、
前記n型半導体層を構成する結晶格子の平均粒径が、1nm以上100μm以下であり、
前記第14族元素は、50℃以上600℃以下の温度範囲において、拡散速度が結晶化速度を上回る元素であることを特徴とする半導体素子。
a base material having a glass transition point of 600° C. or lower;
an n-type semiconductor layer formed on one surface of the base material and containing an element or compound of a group 14 element and an n-type impurity element at a concentration corresponding to the solid solubility limit,
The average grain size of the crystal lattice that constitutes the n-type semiconductor layer is 1 nm or more and 100 μm or less,
A semiconductor device, wherein the Group 14 element is an element having a diffusion rate higher than a crystallization rate in a temperature range of 50°C or higher and 600°C or lower.
前記n型半導体層の厚みが10nm以上50μm以下であることを特徴とする請求項1に記載の半導体素子。 2. The semiconductor device according to claim 1, wherein the n-type semiconductor layer has a thickness of 10 nm or more and 50 [mu]m or less. 前記n型不純物元素がAs、P、Sb、Biであることを特徴とする請求項1または2のいずれかに記載の半導体素子。 3. A semiconductor device according to claim 1, wherein said n-type impurity element is As, P, Sb or Bi. 前記第14族元素の単体または化合物が、Si、SiGe、Ge、GeSn、SiSnのうち少なくとも一つを含むことを特徴とする請求項1~3のいずれか一項に記載の半導体素子。 4. The semiconductor device according to any one of claims 1 to 3, wherein the element or compound of the group 14 element contains at least one of Si, SiGe, Ge, GeSn and SiSn. 前記基材の一面に形成され、前記第14族元素の単体または化合物、およびp型不純物元素を含むp型半導体層を、さらに備えていることを特徴とする請求項1~4のいずれか一項に記載の半導体素子。 5. The substrate according to any one of claims 1 to 4, further comprising a p-type semiconductor layer formed on one surface of the base material and containing the element or compound of the Group 14 element and a p-type impurity element. The semiconductor device according to item 1. 請求項4に記載の半導体素子を備えた熱電変換装置であって、
前記n型半導体層および前記p型半導体層が、一方向に延在する形状を有し、交互に並んで配置され、
前記n型半導体層、前記p型半導体層の一端側に、単数または複数の第一金属電極層が配置され、
前記n型半導体層、前記p型半導体層の他端側に、単数または複数の第二金属電極層が配置され、
片方に隣接する前記n型半導体層の一端、前記p型半導体層の一端が、共通の第一金属電極層に接続され、
隣接する前記n型半導体層の他端、前記p型半導体層の他端が、それぞれ異なる前記第二金属電極層に接続されていることを特徴とする熱電変換装置。
A thermoelectric conversion device comprising the semiconductor element according to claim 4,
wherein the n-type semiconductor layer and the p-type semiconductor layer have a shape extending in one direction and are arranged alternately;
A single or a plurality of first metal electrode layers are arranged on one end side of the n-type semiconductor layer and the p-type semiconductor layer,
A single or a plurality of second metal electrode layers are arranged on the other end side of the n-type semiconductor layer and the p-type semiconductor layer,
one end of the n-type semiconductor layer and one end of the p-type semiconductor layer adjacent to one side are connected to a common first metal electrode layer;
A thermoelectric conversion device, wherein the other end of the n-type semiconductor layer and the other end of the p-type semiconductor layer adjacent to each other are connected to different second metal electrode layers.
前記n型半導体層の他端が接続されている前記第二金属電極層に対し、他の隣接する前記p型半導体層の他端が、さらに接続されていることを特徴とする請求項6に記載の熱電変換装置。 7. The other end of the p-type semiconductor layer adjacent to the second metal electrode layer to which the other end of the n-type semiconductor layer is connected is further connected to the other end of the p-type semiconductor layer. The thermoelectric conversion device described. 前記p型半導体層の他端が接続されている前記第二金属電極層に対し、他の隣接する前記n型半導体層の他端が、さらに接続されていることを特徴とする請求項6または7のいずれかに記載の熱電変換装置。 7. The other end of the adjacent n-type semiconductor layer is further connected to the second metal electrode layer to which the other end of the p-type semiconductor layer is connected. 8. The thermoelectric conversion device according to any one of 7. ガラス転移点が600℃以下の基材と、
前記基材の一面に形成され、第14族元素の単体または化合物、およびn型不純物元素を固溶限相当の濃度で含むn型半導体層と、を備えている半導体素子の製造方法であって、
前記基材の一面に、第一金属元素および前記n型不純物元素を含む第一金属層を形成する第一金属層形成工程と、
前記第一金属層の上に、前記第14族元素の単体または化合物を含む第一半導体層を形成する第一半導体層形成工程と、
熱処理を行い、前記第一金属層と前記第一半導体層の積層順序を交換する層交換工程と、
前記層交換工程後の前記第一金属層を除去する第一金属層除去工程と、を有することを特徴とする半導体素子の製造方法。
a base material having a glass transition point of 600° C. or lower;
A method for manufacturing a semiconductor device comprising: an n-type semiconductor layer formed on one surface of the base material and containing an element or compound of a group 14 element and an n-type impurity element at a concentration corresponding to the solid solubility limit, ,
a first metal layer forming step of forming a first metal layer containing a first metal element and the n-type impurity element on one surface of the substrate;
a first semiconductor layer forming step of forming a first semiconductor layer containing the element or compound of the group 14 element on the first metal layer;
a layer exchange step of performing a heat treatment and exchanging the stacking order of the first metal layer and the first semiconductor layer;
and a first metal layer removing step of removing the first metal layer after the layer exchange step.
前記第一金属元素として、Zn、Ag、Au、Cu、Al、In、Sn、Sb、Biのうち少なくとも一つを用いることを特徴とする請求項9に記載の半導体素子の製造方法。 10. The method of manufacturing a semiconductor device according to claim 9, wherein at least one of Zn, Ag, Au, Cu, Al, In, Sn, Sb and Bi is used as the first metal element. 前記熱処理の温度を600℃以下とすることを特徴とする請求項9または10のいずれかに記載の半導体素子の製造方法。 11. The method of manufacturing a semiconductor device according to claim 9, wherein the heat treatment temperature is 600[deg.] C. or lower. 前記層交換工程の前に、
前記基材の一面に、第二金属元素およびp型不純物元素を含む第二金属層を形成する第二金属層形成工程と、
前記第二金属層の上に、前記第14族元素の単体または化合物を含む第二半導体層を形成する第二半導体層形成工程と、を有し、
前記層交換工程において積層順序を交換された、前記第二金属層を除去する第二金属層除去工程を、さらに有することを特徴とする請求項9~11のいずれか一項に記載の半導体素子の製造方法。
Before the layer exchange step,
a second metal layer forming step of forming a second metal layer containing a second metal element and a p-type impurity element on one surface of the substrate;
a second semiconductor layer forming step of forming a second semiconductor layer containing the single substance or compound of the Group 14 element on the second metal layer,
12. The semiconductor device according to claim 9, further comprising a second metal layer removing step of removing the second metal layer whose stacking order has been changed in the layer changing step. manufacturing method.
請求項12に記載の半導体素子の製造方法を用いた、請求項6~8のいずれか一項に記載の熱電変換装置の製造方法であって、
前記第一半導体層の一端、前記第二半導体層の一端を接続する第一電極金属層と、前記第一半導体層の他端、前記第二半導体層の他端を接続する第二電極金属層と、を形成する電極金属層形成工程を、さらに有することを特徴とする熱電変換装置の製造方法。
A method for manufacturing a thermoelectric conversion device according to any one of claims 6 to 8, using the method for manufacturing a semiconductor element according to claim 12,
A first electrode metal layer connecting one end of the first semiconductor layer and one end of the second semiconductor layer, and a second electrode metal layer connecting the other end of the first semiconductor layer and the other end of the second semiconductor layer. A method for manufacturing a thermoelectric conversion device, further comprising a step of forming an electrode metal layer.
JP2021572793A 2020-01-24 2021-01-21 Pending JPWO2021149770A1 (en)

Applications Claiming Priority (2)

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JP2020010274 2020-01-24
PCT/JP2021/002060 WO2021149770A1 (en) 2020-01-24 2021-01-21 Semiconductor element and manufacturing method thereof, thermoelectric conversion device and manufacturing method thereof

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JPWO2021149770A1 JPWO2021149770A1 (en) 2021-07-29
JPWO2021149770A5 true JPWO2021149770A5 (en) 2022-10-28

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JPH06318736A (en) * 1993-05-06 1994-11-15 Canon Inc Thin film peltier thermoelectric element
JPH0856020A (en) * 1994-06-08 1996-02-27 Nissan Motor Co Ltd Thermoelectric material and thermionic element
WO2005117154A1 (en) * 2004-05-31 2005-12-08 Kazukiyo Yamada High-density integrated type thin-layer thermoelectric module and hybrid power generating system
JP4756856B2 (en) * 2004-12-15 2011-08-24 AvanStrate株式会社 Glass composition and method for producing the same

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