JPWO2021101601A5 - - Google Patents
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- JPWO2021101601A5 JPWO2021101601A5 JP2022529077A JP2022529077A JPWO2021101601A5 JP WO2021101601 A5 JPWO2021101601 A5 JP WO2021101601A5 JP 2022529077 A JP2022529077 A JP 2022529077A JP 2022529077 A JP2022529077 A JP 2022529077A JP WO2021101601 A5 JPWO2021101601 A5 JP WO2021101601A5
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Claims (9)
1つ以上のマイクロプロセッサと、
第1のサブネットとを備え、前記第1のサブネットは、
複数のスイッチを含み、前記複数のスイッチは少なくともリーフスイッチを含み、前記複数のスイッチの各々は複数のスイッチポートを含み、前記第1のサブネットはさらに、
複数のホストチャネルアダプタを含み、前記ホストチャネルアダプタの各々は、少なくとも1つのホストチャネルアダプタポートを含み、前記複数のホストチャネルアダプタは、前記複数のスイッチを介して相互接続され、前記第1のサブネットはさらに、
複数の仮想マシンを含む複数のエンドノードを含み、
前記複数のスイッチのうちの2つのスイッチ間のスイッチ間リンクまたは前記複数のスイッチのうちのあるスイッチのポートのうちの少なくとも1つにおいて、ターゲットグループが定義され、前記ターゲットグループは、前記複数のスイッチのうちの2つのスイッチ間のスイッチ間リンクまたは前記複数のスイッチのうちのあるスイッチのポートのうちの前記少なくとも1つにおいて帯域幅制限を定義し、
ホストチャネルアダプタは、前記ホストチャネルアダプタのメモリに記憶されるターゲットグループリポジトリを含み、
前記定義されたターゲットグループは、前記ターゲットグループリポジトリに記録される、システム。 A system for supporting target groups for congestion control in a private fabric in a high performance computing environment, comprising:
one or more microprocessors;
a first subnet, said first subnet comprising:
comprising a plurality of switches, the plurality of switches comprising at least a leaf switch, each of the plurality of switches comprising a plurality of switch ports, the first subnet further comprising:
a plurality of host channel adapters, each of said host channel adapters including at least one host channel adapter port; said plurality of host channel adapters interconnected via said plurality of switches; furthermore,
contains multiple end nodes containing multiple virtual machines,
A target group is defined in at least one of an inter-switch link between two switches of the plurality of switches or a port of a switch of the plurality of switches, wherein the target group comprises the plurality of switches. defining a bandwidth limit on said at least one of an inter-switch link between two switches of or a port of a switch of said plurality of switches;
the host channel adapter includes a target group repository stored in memory of said host channel adapter;
The system, wherein the defined target groups are recorded in the target group repository.
前記複数のエンドノードのうちの第1のエンドノードは、前記ターゲットグループリポジトリを含む前記ホストチャネルアダプタに設けられ、
前記第1のエンドノードは、前記ターゲットグループリポジトリを含む前記ホストチャネルアダプタにおいて定義される第1のエグレス帯域幅制限に関連付けられ、前記第1のエグレス帯域幅制限は、前記第1のエンドノードの第1のQoS(quality of service)合意に関連付けられる、請求項1に記載のシステム。 the target group is defined on the inter-switch link between two switches of the plurality of switches;
a first end node of the plurality of end nodes is provided on the host channel adapter containing the target group repository;
The first end node is associated with a first egress bandwidth limit defined in the host channel adapter containing the target group repository, the first egress bandwidth limit being the first end node's 2. The system of claim 1, associated with a first quality of service (QoS) agreement.
1つ以上のマイクロプロセッサにおいて、第1のサブネットを提供することを含み、前記第1のサブネットは、
複数のスイッチを含み、前記複数のスイッチは少なくともリーフスイッチを含み、前記複数のスイッチの各々は複数のスイッチポートを含み、前記第1のサブネットはさらに、
複数のホストチャネルアダプタを含み、前記ホストチャネルアダプタの各々は、少なくとも1つのホストチャネルアダプタポートを含み、前記複数のホストチャネルアダプタは、前記複数のスイッチを介して相互接続され、前記第1のサブネットはさらに、
複数の仮想マシンを含む複数のエンドノードを含み、前記方法はさらに、
前記複数のスイッチのうちの2つのスイッチ間のスイッチ間リンクまたは前記複数のスイッチのうちのあるスイッチのポートのうちの少なくとも1つにおいて、ターゲットグループを定義することを含み、前記ターゲットグループは、前記複数のスイッチのうちの2つのスイッチ間のスイッチ間リンクまたは前記複数のスイッチのうちのあるスイッチのポートのうちの前記少なくとも1つにおいて帯域幅制限を定義し、前記方法はさらに、
ホストチャネルアダプタにおいて、前記ホストチャネルアダプタのメモリに記憶されるターゲットグループリポジトリを提供することと、
前記定義されたターゲットグループを前記ターゲットグループリポジトリに記録することとを含む、方法。 A method for supporting target groups for congestion control in a private fabric in a high performance computing environment, comprising:
providing a first subnet in one or more microprocessors, the first subnet comprising:
comprising a plurality of switches, the plurality of switches comprising at least a leaf switch, each of the plurality of switches comprising a plurality of switch ports, the first subnet further comprising:
a plurality of host channel adapters, each of said host channel adapters including at least one host channel adapter port; said plurality of host channel adapters interconnected via said plurality of switches; furthermore,
Including a plurality of end nodes including a plurality of virtual machines, the method further comprising:
defining a target group in at least one of an inter-switch link between two switches of the plurality of switches or a port of a switch of the plurality of switches, wherein the target group comprises the defining a bandwidth limit on said at least one of an inter-switch link between two switches of a plurality of switches or a port of a switch of said plurality of switches, said method further comprising:
in a host channel adapter, providing a target group repository stored in memory of the host channel adapter;
recording the defined target groups in the target group repository.
1つ以上のマイクロプロセッサにおいて、第1のサブネットを提供することを含み、前記第1のサブネットは、
複数のスイッチを含み、前記複数のスイッチは少なくともリーフスイッチを含み、前記複数のスイッチの各々は複数のスイッチポートを含み、前記第1のサブネットはさらに、
複数のホストチャネルアダプタを含み、前記ホストチャネルアダプタの各々は、少なくとも1つのホストチャネルアダプタポートを含み、前記複数のホストチャネルアダプタは、前記複数のスイッチを介して相互接続され、前記第1のサブネットはさらに、
複数の仮想マシンを含む複数のエンドノードを含み、前記ステップはさらに、
前記複数のスイッチのうちの2つのスイッチ間のスイッチ間リンクまたは前記複数のスイッチのうちのあるスイッチのポートのうちの少なくとも1つにおいて、ターゲットグループを定義することを含み、前記ターゲットグループは、前記複数のスイッチのうちの2つのスイッチ間のスイッチ間リンクまたは前記複数のスイッチのうちのあるスイッチのポートのうちの前記少なくとも1つにおいて帯域幅制限を定義し、前記ステップはさらに、
ホストチャネルアダプタにおいて、前記ホストチャネルアダプタのメモリに記憶されたターゲットグループリポジトリを提供することと、
前記定義されたターゲットグループを前記ターゲットグループリポジトリに記録することとを含む、コンピュータ可読プログラム。 1. A computer readable program having instructions for supporting target groups for congestion control in a private fabric in a high performance computing environment, said instructions being read and executed to cause a computer to perform the following steps: and wherein said step includes:
providing a first subnet in one or more microprocessors, the first subnet comprising:
comprising a plurality of switches, the plurality of switches comprising at least a leaf switch, each of the plurality of switches comprising a plurality of switch ports, the first subnet further comprising:
a plurality of host channel adapters, each of said host channel adapters including at least one host channel adapter port; said plurality of host channel adapters interconnected via said plurality of switches; furthermore,
comprising a plurality of end nodes comprising a plurality of virtual machines, said step further comprising:
defining a target group in at least one of an inter-switch link between two switches of the plurality of switches or a port of a switch of the plurality of switches, wherein the target group comprises the defining a bandwidth limit on said at least one of an inter-switch link between two switches of a plurality of switches or a port of a switch of said plurality of switches, said step further comprising:
in a host channel adapter, providing a target group repository stored in memory of the host channel adapter;
recording the defined target groups in the target group repository .
Applications Claiming Priority (11)
Application Number | Priority Date | Filing Date | Title |
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US201962937594P | 2019-11-19 | 2019-11-19 | |
US62/937,594 | 2019-11-19 | ||
US16/872,038 | 2020-05-11 | ||
US16/872,035 US11700206B2 (en) | 2019-11-19 | 2020-05-11 | System and method for supporting RDMA bandwidth restrictions in a private fabric in a high performance computing environment |
US16/872,038 US11256655B2 (en) | 2019-11-19 | 2020-05-11 | System and method for providing bandwidth congestion control in a private fabric in a high performance computing environment |
US16/872,035 | 2020-05-11 | ||
US16/872,039 | 2020-05-11 | ||
US16/872,043 US11444881B2 (en) | 2019-11-19 | 2020-05-11 | System and method for supporting use of forward and backward congestion notifications in a private fabric in a high performance computing environment |
US16/872,043 | 2020-05-11 | ||
US16/872,039 US11341082B2 (en) | 2019-11-19 | 2020-05-11 | System and method for supporting target groups for congestion control in a private fabric in a high performance computing environment |
PCT/US2020/045272 WO2021101601A1 (en) | 2019-11-19 | 2020-08-06 | System and method for supporting target groups for congestion control in a private fabric in a high performance computing environment |
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JP2023503273A JP2023503273A (en) | 2023-01-27 |
JPWO2021101601A5 true JPWO2021101601A5 (en) | 2023-06-22 |
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JP2022529054A Pending JP2023503063A (en) | 2019-11-19 | 2020-08-06 | Systems and methods for providing bandwidth congestion control in private fabrics in high performance computing environments |
JP2022529052A Pending JP2023502397A (en) | 2019-11-19 | 2020-08-06 | Systems and methods for supporting RDMA bandwidth limitations in private fabrics in high performance computing environments |
JP2022529078A Pending JP2023503274A (en) | 2019-11-19 | 2020-08-06 | Systems and methods for supporting the use of forward and reverse congestion notification in private fabrics in high performance computing environments |
JP2022529077A Pending JP2023503273A (en) | 2019-11-19 | 2020-08-06 | System and method for supporting target groups for congestion control in private fabrics in high performance computing environments |
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JP2022529052A Pending JP2023502397A (en) | 2019-11-19 | 2020-08-06 | Systems and methods for supporting RDMA bandwidth limitations in private fabrics in high performance computing environments |
JP2022529078A Pending JP2023503274A (en) | 2019-11-19 | 2020-08-06 | Systems and methods for supporting the use of forward and reverse congestion notification in private fabrics in high performance computing environments |
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US (7) | US11341082B2 (en) |
EP (4) | EP4062601A1 (en) |
JP (4) | JP2023503063A (en) |
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WO (4) | WO2021101601A1 (en) |
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