JPWO2021049354A1 - - Google Patents
Info
- Publication number
- JPWO2021049354A1 JPWO2021049354A1 JP2021545228A JP2021545228A JPWO2021049354A1 JP WO2021049354 A1 JPWO2021049354 A1 JP WO2021049354A1 JP 2021545228 A JP2021545228 A JP 2021545228A JP 2021545228 A JP2021545228 A JP 2021545228A JP WO2021049354 A1 JPWO2021049354 A1 JP WO2021049354A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0697—Synchronisation in a packet node
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40169—Flexible bus arrangements
- H04L12/40176—Flexible bus arrangements involving redundancy
- H04L12/40189—Flexible bus arrangements involving redundancy by using a plurality of bus systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/0033—Correction by delay
- H04L7/0041—Delay of data signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/60—Control of cameras or camera modules
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Theoretical Computer Science (AREA)
- Multimedia (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Studio Devices (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019166895 | 2019-09-13 | ||
JP2019166895 | 2019-09-13 | ||
PCT/JP2020/032877 WO2021049354A1 (ja) | 2019-09-13 | 2020-08-31 | 通信装置および通信方法、並びにプログラム |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2021049354A1 true JPWO2021049354A1 (ja) | 2021-03-18 |
JP7571034B2 JP7571034B2 (ja) | 2024-10-22 |
Family
ID=74866072
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2021545228A Active JP7571034B2 (ja) | 2019-09-13 | 2020-08-31 | 通信装置および通信方法、並びにプログラム |
Country Status (4)
Country | Link |
---|---|
US (1) | US20220345287A1 (ja) |
JP (1) | JP7571034B2 (ja) |
DE (1) | DE112020004344T5 (ja) |
WO (1) | WO2021049354A1 (ja) |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015076805A (ja) | 2013-10-10 | 2015-04-20 | セイコーエプソン株式会社 | 機能デバイス、電子機器、移動体、同期制御システム、機能デバイスの動作方法及び同期制御方法 |
JP2015198399A (ja) * | 2014-04-02 | 2015-11-09 | 三菱電機株式会社 | 通信装置 |
-
2020
- 2020-08-31 WO PCT/JP2020/032877 patent/WO2021049354A1/ja active Application Filing
- 2020-08-31 US US17/753,523 patent/US20220345287A1/en active Pending
- 2020-08-31 DE DE112020004344.4T patent/DE112020004344T5/de active Pending
- 2020-08-31 JP JP2021545228A patent/JP7571034B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
DE112020004344T5 (de) | 2022-06-02 |
WO2021049354A1 (ja) | 2021-03-18 |
JP7571034B2 (ja) | 2024-10-22 |
US20220345287A1 (en) | 2022-10-27 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20230706 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20240604 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20240726 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20240910 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20241009 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7571034 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |